1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_QCOM_GENI_SE 7 #define _LINUX_QCOM_GENI_SE 8 9 #include <linux/interconnect.h> 10 11 /** 12 * enum geni_se_xfer_mode: Transfer modes supported by Serial Engines 13 * 14 * @GENI_SE_INVALID: Invalid mode 15 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO 16 * by programmed IO method 17 * @GENI_SE_DMA: Serial Engine DMA mode. Data is transferred 18 * with SE by DMAengine internal to SE 19 * @GENI_GPI_DMA: GPI DMA mode. Data is transferred using a DMAengine 20 * configured by a firmware residing on a GSI engine. This DMA name is 21 * interchangeably used as GSI or GPI which seem to imply the same DMAengine 22 */ 23 24 enum geni_se_xfer_mode { 25 GENI_SE_INVALID, 26 GENI_SE_FIFO, 27 GENI_SE_DMA, 28 GENI_GPI_DMA, 29 }; 30 31 /* Protocols supported by GENI Serial Engines */ 32 enum geni_se_protocol_type { 33 GENI_SE_NONE, 34 GENI_SE_SPI, 35 GENI_SE_UART, 36 GENI_SE_I2C, 37 GENI_SE_I3C, 38 }; 39 40 struct geni_wrapper; 41 struct clk; 42 43 enum geni_icc_path_index { 44 GENI_TO_CORE, 45 CPU_TO_GENI, 46 GENI_TO_DDR 47 }; 48 49 struct geni_icc_path { 50 struct icc_path *path; 51 unsigned int avg_bw; 52 }; 53 54 /** 55 * struct geni_se - GENI Serial Engine 56 * @base: Base Address of the Serial Engine's register block 57 * @dev: Pointer to the Serial Engine device 58 * @wrapper: Pointer to the parent QUP Wrapper core 59 * @clk: Handle to the core serial engine clock 60 * @num_clk_levels: Number of valid clock levels in clk_perf_tbl 61 * @clk_perf_tbl: Table of clock frequency input to serial engine clock 62 * @icc_paths: Array of ICC paths for SE 63 */ 64 struct geni_se { 65 void __iomem *base; 66 struct device *dev; 67 struct geni_wrapper *wrapper; 68 struct clk *clk; 69 unsigned int num_clk_levels; 70 unsigned long *clk_perf_tbl; 71 struct geni_icc_path icc_paths[3]; 72 }; 73 74 /* Common SE registers */ 75 #define GENI_FORCE_DEFAULT_REG 0x20 76 #define SE_GENI_STATUS 0x40 77 #define GENI_SER_M_CLK_CFG 0x48 78 #define GENI_SER_S_CLK_CFG 0x4c 79 #define GENI_IF_DISABLE_RO 0x64 80 #define GENI_FW_REVISION_RO 0x68 81 #define SE_GENI_CLK_SEL 0x7c 82 #define SE_GENI_DMA_MODE_EN 0x258 83 #define SE_GENI_M_CMD0 0x600 84 #define SE_GENI_M_CMD_CTRL_REG 0x604 85 #define SE_GENI_M_IRQ_STATUS 0x610 86 #define SE_GENI_M_IRQ_EN 0x614 87 #define SE_GENI_M_IRQ_CLEAR 0x618 88 #define SE_GENI_S_CMD0 0x630 89 #define SE_GENI_S_CMD_CTRL_REG 0x634 90 #define SE_GENI_S_IRQ_STATUS 0x640 91 #define SE_GENI_S_IRQ_EN 0x644 92 #define SE_GENI_S_IRQ_CLEAR 0x648 93 #define SE_GENI_TX_FIFOn 0x700 94 #define SE_GENI_RX_FIFOn 0x780 95 #define SE_GENI_TX_FIFO_STATUS 0x800 96 #define SE_GENI_RX_FIFO_STATUS 0x804 97 #define SE_GENI_TX_WATERMARK_REG 0x80c 98 #define SE_GENI_RX_WATERMARK_REG 0x810 99 #define SE_GENI_RX_RFR_WATERMARK_REG 0x814 100 #define SE_GENI_IOS 0x908 101 #define SE_DMA_TX_IRQ_STAT 0xc40 102 #define SE_DMA_TX_IRQ_CLR 0xc44 103 #define SE_DMA_TX_FSM_RST 0xc58 104 #define SE_DMA_RX_IRQ_STAT 0xd40 105 #define SE_DMA_RX_IRQ_CLR 0xd44 106 #define SE_DMA_RX_LEN_IN 0xd54 107 #define SE_DMA_RX_FSM_RST 0xd58 108 #define SE_HW_PARAM_0 0xe24 109 #define SE_HW_PARAM_1 0xe28 110 111 /* GENI_FORCE_DEFAULT_REG fields */ 112 #define FORCE_DEFAULT BIT(0) 113 114 /* GENI_STATUS fields */ 115 #define M_GENI_CMD_ACTIVE BIT(0) 116 #define S_GENI_CMD_ACTIVE BIT(12) 117 118 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ 119 #define SER_CLK_EN BIT(0) 120 #define CLK_DIV_MSK GENMASK(15, 4) 121 #define CLK_DIV_SHFT 4 122 123 /* GENI_IF_DISABLE_RO fields */ 124 #define FIFO_IF_DISABLE (BIT(0)) 125 126 /* GENI_FW_REVISION_RO fields */ 127 #define FW_REV_PROTOCOL_MSK GENMASK(15, 8) 128 #define FW_REV_PROTOCOL_SHFT 8 129 130 /* GENI_CLK_SEL fields */ 131 #define CLK_SEL_MSK GENMASK(2, 0) 132 133 /* SE_GENI_DMA_MODE_EN */ 134 #define GENI_DMA_MODE_EN BIT(0) 135 136 /* GENI_M_CMD0 fields */ 137 #define M_OPCODE_MSK GENMASK(31, 27) 138 #define M_OPCODE_SHFT 27 139 #define M_PARAMS_MSK GENMASK(26, 0) 140 141 /* GENI_M_CMD_CTRL_REG */ 142 #define M_GENI_CMD_CANCEL BIT(2) 143 #define M_GENI_CMD_ABORT BIT(1) 144 #define M_GENI_DISABLE BIT(0) 145 146 /* GENI_S_CMD0 fields */ 147 #define S_OPCODE_MSK GENMASK(31, 27) 148 #define S_OPCODE_SHFT 27 149 #define S_PARAMS_MSK GENMASK(26, 0) 150 151 /* GENI_S_CMD_CTRL_REG */ 152 #define S_GENI_CMD_CANCEL BIT(2) 153 #define S_GENI_CMD_ABORT BIT(1) 154 #define S_GENI_DISABLE BIT(0) 155 156 /* GENI_M_IRQ_EN fields */ 157 #define M_CMD_DONE_EN BIT(0) 158 #define M_CMD_OVERRUN_EN BIT(1) 159 #define M_ILLEGAL_CMD_EN BIT(2) 160 #define M_CMD_FAILURE_EN BIT(3) 161 #define M_CMD_CANCEL_EN BIT(4) 162 #define M_CMD_ABORT_EN BIT(5) 163 #define M_TIMESTAMP_EN BIT(6) 164 #define M_RX_IRQ_EN BIT(7) 165 #define M_GP_SYNC_IRQ_0_EN BIT(8) 166 #define M_GP_IRQ_0_EN BIT(9) 167 #define M_GP_IRQ_1_EN BIT(10) 168 #define M_GP_IRQ_2_EN BIT(11) 169 #define M_GP_IRQ_3_EN BIT(12) 170 #define M_GP_IRQ_4_EN BIT(13) 171 #define M_GP_IRQ_5_EN BIT(14) 172 #define M_IO_DATA_DEASSERT_EN BIT(22) 173 #define M_IO_DATA_ASSERT_EN BIT(23) 174 #define M_RX_FIFO_RD_ERR_EN BIT(24) 175 #define M_RX_FIFO_WR_ERR_EN BIT(25) 176 #define M_RX_FIFO_WATERMARK_EN BIT(26) 177 #define M_RX_FIFO_LAST_EN BIT(27) 178 #define M_TX_FIFO_RD_ERR_EN BIT(28) 179 #define M_TX_FIFO_WR_ERR_EN BIT(29) 180 #define M_TX_FIFO_WATERMARK_EN BIT(30) 181 #define M_SEC_IRQ_EN BIT(31) 182 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ 183 M_IO_DATA_DEASSERT_EN | \ 184 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ 185 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ 186 M_TX_FIFO_WR_ERR_EN) 187 188 /* GENI_S_IRQ_EN fields */ 189 #define S_CMD_DONE_EN BIT(0) 190 #define S_CMD_OVERRUN_EN BIT(1) 191 #define S_ILLEGAL_CMD_EN BIT(2) 192 #define S_CMD_FAILURE_EN BIT(3) 193 #define S_CMD_CANCEL_EN BIT(4) 194 #define S_CMD_ABORT_EN BIT(5) 195 #define S_GP_SYNC_IRQ_0_EN BIT(8) 196 #define S_GP_IRQ_0_EN BIT(9) 197 #define S_GP_IRQ_1_EN BIT(10) 198 #define S_GP_IRQ_2_EN BIT(11) 199 #define S_GP_IRQ_3_EN BIT(12) 200 #define S_GP_IRQ_4_EN BIT(13) 201 #define S_GP_IRQ_5_EN BIT(14) 202 #define S_IO_DATA_DEASSERT_EN BIT(22) 203 #define S_IO_DATA_ASSERT_EN BIT(23) 204 #define S_RX_FIFO_RD_ERR_EN BIT(24) 205 #define S_RX_FIFO_WR_ERR_EN BIT(25) 206 #define S_RX_FIFO_WATERMARK_EN BIT(26) 207 #define S_RX_FIFO_LAST_EN BIT(27) 208 #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \ 209 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN) 210 211 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ 212 #define WATERMARK_MSK GENMASK(5, 0) 213 214 /* GENI_TX_FIFO_STATUS fields */ 215 #define TX_FIFO_WC GENMASK(27, 0) 216 217 /* GENI_RX_FIFO_STATUS fields */ 218 #define RX_LAST BIT(31) 219 #define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28) 220 #define RX_LAST_BYTE_VALID_SHFT 28 221 #define RX_FIFO_WC_MSK GENMASK(24, 0) 222 223 /* SE_GENI_IOS fields */ 224 #define IO2_DATA_IN BIT(1) 225 #define RX_DATA_IN BIT(0) 226 227 /* SE_DMA_TX_IRQ_STAT Register fields */ 228 #define TX_DMA_DONE BIT(0) 229 #define TX_EOT BIT(1) 230 #define TX_SBE BIT(2) 231 #define TX_RESET_DONE BIT(3) 232 233 /* SE_DMA_RX_IRQ_STAT Register fields */ 234 #define RX_DMA_DONE BIT(0) 235 #define RX_EOT BIT(1) 236 #define RX_SBE BIT(2) 237 #define RX_RESET_DONE BIT(3) 238 #define RX_FLUSH_DONE BIT(4) 239 #define RX_DMA_PARITY_ERR BIT(5) 240 #define RX_DMA_BREAK GENMASK(8, 7) 241 #define RX_GENI_GP_IRQ GENMASK(10, 5) 242 #define RX_GENI_CANCEL_IRQ BIT(11) 243 #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12) 244 245 /* SE_HW_PARAM_0 fields */ 246 #define TX_FIFO_WIDTH_MSK GENMASK(29, 24) 247 #define TX_FIFO_WIDTH_SHFT 24 248 /* 249 * For QUP HW Version >= 3.10 Tx fifo depth support is increased 250 * to 256bytes and corresponding bits are 16 to 23 251 */ 252 #define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) 253 #define TX_FIFO_DEPTH_MSK GENMASK(21, 16) 254 #define TX_FIFO_DEPTH_SHFT 16 255 256 /* SE_HW_PARAM_1 fields */ 257 #define RX_FIFO_WIDTH_MSK GENMASK(29, 24) 258 #define RX_FIFO_WIDTH_SHFT 24 259 /* 260 * For QUP HW Version >= 3.10 Rx fifo depth support is increased 261 * to 256bytes and corresponding bits are 16 to 23 262 */ 263 #define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) 264 #define RX_FIFO_DEPTH_MSK GENMASK(21, 16) 265 #define RX_FIFO_DEPTH_SHFT 16 266 267 #define HW_VER_MAJOR_MASK GENMASK(31, 28) 268 #define HW_VER_MAJOR_SHFT 28 269 #define HW_VER_MINOR_MASK GENMASK(27, 16) 270 #define HW_VER_MINOR_SHFT 16 271 #define HW_VER_STEP_MASK GENMASK(15, 0) 272 273 #define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT) 274 #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT) 275 #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK) 276 277 /* QUP SE VERSION value for major number 2 and minor number 5 */ 278 #define QUP_SE_VERSION_2_5 0x20050000 279 280 /* 281 * Define bandwidth thresholds that cause the underlying Core 2X interconnect 282 * clock to run at the named frequency. These baseline values are recommended 283 * by the hardware team, and are not dynamically scaled with GENI bandwidth 284 * beyond basic on/off. 285 */ 286 #define CORE_2X_19_2_MHZ 960 287 #define CORE_2X_50_MHZ 2500 288 #define CORE_2X_100_MHZ 5000 289 #define CORE_2X_150_MHZ 7500 290 #define CORE_2X_200_MHZ 10000 291 #define CORE_2X_236_MHZ 16383 292 293 #define GENI_DEFAULT_BW Bps_to_icc(1000) 294 295 #if IS_ENABLED(CONFIG_QCOM_GENI_SE) 296 297 u32 geni_se_get_qup_hw_version(struct geni_se *se); 298 299 /** 300 * geni_se_read_proto() - Read the protocol configured for a serial engine 301 * @se: Pointer to the concerned serial engine. 302 * 303 * Return: Protocol value as configured in the serial engine. 304 */ 305 static inline u32 geni_se_read_proto(struct geni_se *se) 306 { 307 u32 val; 308 309 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); 310 311 return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT; 312 } 313 314 /** 315 * geni_se_setup_m_cmd() - Setup the primary sequencer 316 * @se: Pointer to the concerned serial engine. 317 * @cmd: Command/Operation to setup in the primary sequencer. 318 * @params: Parameter for the sequencer command. 319 * 320 * This function is used to configure the primary sequencer with the 321 * command and its associated parameters. 322 */ 323 static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params) 324 { 325 u32 m_cmd; 326 327 m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK); 328 writel(m_cmd, se->base + SE_GENI_M_CMD0); 329 } 330 331 /** 332 * geni_se_setup_s_cmd() - Setup the secondary sequencer 333 * @se: Pointer to the concerned serial engine. 334 * @cmd: Command/Operation to setup in the secondary sequencer. 335 * @params: Parameter for the sequencer command. 336 * 337 * This function is used to configure the secondary sequencer with the 338 * command and its associated parameters. 339 */ 340 static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params) 341 { 342 u32 s_cmd; 343 344 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); 345 s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK); 346 s_cmd |= (cmd << S_OPCODE_SHFT); 347 s_cmd |= (params & S_PARAMS_MSK); 348 writel(s_cmd, se->base + SE_GENI_S_CMD0); 349 } 350 351 /** 352 * geni_se_cancel_m_cmd() - Cancel the command configured in the primary 353 * sequencer 354 * @se: Pointer to the concerned serial engine. 355 * 356 * This function is used to cancel the currently configured command in the 357 * primary sequencer. 358 */ 359 static inline void geni_se_cancel_m_cmd(struct geni_se *se) 360 { 361 writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG); 362 } 363 364 /** 365 * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary 366 * sequencer 367 * @se: Pointer to the concerned serial engine. 368 * 369 * This function is used to cancel the currently configured command in the 370 * secondary sequencer. 371 */ 372 static inline void geni_se_cancel_s_cmd(struct geni_se *se) 373 { 374 writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG); 375 } 376 377 /** 378 * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer 379 * @se: Pointer to the concerned serial engine. 380 * 381 * This function is used to force abort the currently configured command in the 382 * primary sequencer. 383 */ 384 static inline void geni_se_abort_m_cmd(struct geni_se *se) 385 { 386 writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG); 387 } 388 389 /** 390 * geni_se_abort_s_cmd() - Abort the command configured in the secondary 391 * sequencer 392 * @se: Pointer to the concerned serial engine. 393 * 394 * This function is used to force abort the currently configured command in the 395 * secondary sequencer. 396 */ 397 static inline void geni_se_abort_s_cmd(struct geni_se *se) 398 { 399 writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG); 400 } 401 402 /** 403 * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine 404 * based on QUP HW version 405 * @se: Pointer to the concerned serial engine. 406 * 407 * This function is used to get the depth i.e. number of elements in the 408 * TX fifo of the serial engine. 409 * 410 * Return: TX fifo depth in units of FIFO words. 411 */ 412 static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se) 413 { 414 u32 val, hw_version, hw_major, hw_minor, tx_fifo_depth_mask; 415 416 hw_version = geni_se_get_qup_hw_version(se); 417 hw_major = GENI_SE_VERSION_MAJOR(hw_version); 418 hw_minor = GENI_SE_VERSION_MINOR(hw_version); 419 420 if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) 421 tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK_256_BYTES; 422 else 423 tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK; 424 425 val = readl_relaxed(se->base + SE_HW_PARAM_0); 426 427 return (val & tx_fifo_depth_mask) >> TX_FIFO_DEPTH_SHFT; 428 } 429 430 /** 431 * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine 432 * @se: Pointer to the concerned serial engine. 433 * 434 * This function is used to get the width i.e. word size per element in the 435 * TX fifo of the serial engine. 436 * 437 * Return: TX fifo width in bits 438 */ 439 static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se) 440 { 441 u32 val; 442 443 val = readl_relaxed(se->base + SE_HW_PARAM_0); 444 445 return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT; 446 } 447 448 /** 449 * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine 450 * based on QUP HW version 451 * @se: Pointer to the concerned serial engine. 452 * 453 * This function is used to get the depth i.e. number of elements in the 454 * RX fifo of the serial engine. 455 * 456 * Return: RX fifo depth in units of FIFO words 457 */ 458 static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se) 459 { 460 u32 val, hw_version, hw_major, hw_minor, rx_fifo_depth_mask; 461 462 hw_version = geni_se_get_qup_hw_version(se); 463 hw_major = GENI_SE_VERSION_MAJOR(hw_version); 464 hw_minor = GENI_SE_VERSION_MINOR(hw_version); 465 466 if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) 467 rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK_256_BYTES; 468 else 469 rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK; 470 471 val = readl_relaxed(se->base + SE_HW_PARAM_1); 472 473 return (val & rx_fifo_depth_mask) >> RX_FIFO_DEPTH_SHFT; 474 } 475 476 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr); 477 478 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode); 479 480 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, 481 bool msb_to_lsb, bool tx_cfg, bool rx_cfg); 482 483 int geni_se_resources_off(struct geni_se *se); 484 485 int geni_se_resources_on(struct geni_se *se); 486 487 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl); 488 489 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, 490 unsigned int *index, unsigned long *res_freq, 491 bool exact); 492 493 void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); 494 495 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, 496 dma_addr_t *iova); 497 498 void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); 499 500 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, 501 dma_addr_t *iova); 502 503 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); 504 505 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); 506 507 int geni_icc_get(struct geni_se *se, const char *icc_ddr); 508 509 int geni_icc_set_bw(struct geni_se *se); 510 void geni_icc_set_tag(struct geni_se *se, u32 tag); 511 512 int geni_icc_enable(struct geni_se *se); 513 514 int geni_icc_disable(struct geni_se *se); 515 #endif 516 #endif 517