1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2020 Mellanox Technologies Ltd. */ 3 4 #ifndef __MLX5_IFC_VDPA_H_ 5 #define __MLX5_IFC_VDPA_H_ 6 7 enum { 8 MLX5_VIRTIO_Q_EVENT_MODE_NO_MSIX_MODE = 0x0, 9 MLX5_VIRTIO_Q_EVENT_MODE_QP_MODE = 0x1, 10 MLX5_VIRTIO_Q_EVENT_MODE_MSIX_MODE = 0x2, 11 }; 12 13 enum { 14 MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_SPLIT = 0x1, // do I check this caps? 15 MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_PACKED = 0x2, 16 }; 17 18 enum { 19 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_SPLIT = 0, 20 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_PACKED = 1, 21 }; 22 23 struct mlx5_ifc_virtio_q_bits { 24 u8 virtio_q_type[0x8]; 25 u8 reserved_at_8[0x5]; 26 u8 event_mode[0x3]; 27 u8 queue_index[0x10]; 28 29 u8 full_emulation[0x1]; 30 u8 virtio_version_1_0[0x1]; 31 u8 reserved_at_22[0x2]; 32 u8 offload_type[0x4]; 33 u8 event_qpn_or_msix[0x18]; 34 35 u8 doorbell_stride_index[0x10]; 36 u8 queue_size[0x10]; 37 38 u8 device_emulation_id[0x20]; 39 40 u8 desc_addr[0x40]; 41 42 u8 used_addr[0x40]; 43 44 u8 available_addr[0x40]; 45 46 u8 virtio_q_mkey[0x20]; 47 48 u8 max_tunnel_desc[0x10]; 49 u8 reserved_at_170[0x8]; 50 u8 error_type[0x8]; 51 52 u8 umem_1_id[0x20]; 53 54 u8 umem_1_size[0x20]; 55 56 u8 umem_1_offset[0x40]; 57 58 u8 umem_2_id[0x20]; 59 60 u8 umem_2_size[0x20]; 61 62 u8 umem_2_offset[0x40]; 63 64 u8 umem_3_id[0x20]; 65 66 u8 umem_3_size[0x20]; 67 68 u8 umem_3_offset[0x40]; 69 70 u8 counter_set_id[0x20]; 71 72 u8 reserved_at_320[0x8]; 73 u8 pd[0x18]; 74 75 u8 reserved_at_340[0xc0]; 76 }; 77 78 struct mlx5_ifc_virtio_net_q_object_bits { 79 u8 modify_field_select[0x40]; 80 81 u8 reserved_at_40[0x20]; 82 83 u8 vhca_id[0x10]; 84 u8 reserved_at_70[0x10]; 85 86 u8 queue_feature_bit_mask_12_3[0xa]; 87 u8 dirty_bitmap_dump_enable[0x1]; 88 u8 vhost_log_page[0x5]; 89 u8 reserved_at_90[0xc]; 90 u8 state[0x4]; 91 92 u8 reserved_at_a0[0x5]; 93 u8 queue_feature_bit_mask_2_0[0x3]; 94 u8 tisn_or_qpn[0x18]; 95 96 u8 dirty_bitmap_mkey[0x20]; 97 98 u8 dirty_bitmap_size[0x20]; 99 100 u8 dirty_bitmap_addr[0x40]; 101 102 u8 hw_available_index[0x10]; 103 u8 hw_used_index[0x10]; 104 105 u8 reserved_at_160[0xa0]; 106 107 struct mlx5_ifc_virtio_q_bits virtio_q_context; 108 }; 109 110 struct mlx5_ifc_create_virtio_net_q_in_bits { 111 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 112 113 struct mlx5_ifc_virtio_net_q_object_bits obj_context; 114 }; 115 116 struct mlx5_ifc_create_virtio_net_q_out_bits { 117 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 118 }; 119 120 struct mlx5_ifc_destroy_virtio_net_q_in_bits { 121 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_out_cmd_hdr; 122 }; 123 124 struct mlx5_ifc_destroy_virtio_net_q_out_bits { 125 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 126 }; 127 128 struct mlx5_ifc_query_virtio_net_q_in_bits { 129 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 130 }; 131 132 struct mlx5_ifc_query_virtio_net_q_out_bits { 133 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 134 135 struct mlx5_ifc_virtio_net_q_object_bits obj_context; 136 }; 137 138 enum { 139 MLX5_VIRTQ_MODIFY_MASK_STATE = (u64)1 << 0, 140 MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_PARAMS = (u64)1 << 3, 141 MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_DUMP_ENABLE = (u64)1 << 4, 142 }; 143 144 enum { 145 MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT = 0x0, 146 MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY = 0x1, 147 MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND = 0x2, 148 MLX5_VIRTIO_NET_Q_OBJECT_STATE_ERR = 0x3, 149 }; 150 151 enum { 152 MLX5_RQTC_LIST_Q_TYPE_RQ = 0x0, 153 MLX5_RQTC_LIST_Q_TYPE_VIRTIO_NET_Q = 0x1, 154 }; 155 156 struct mlx5_ifc_modify_virtio_net_q_in_bits { 157 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 158 159 struct mlx5_ifc_virtio_net_q_object_bits obj_context; 160 }; 161 162 struct mlx5_ifc_modify_virtio_net_q_out_bits { 163 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 164 }; 165 166 #endif /* __MLX5_IFC_VDPA_H_ */ 167