1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/if_ether.h> 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 #include <linux/radix-tree.h> 40 #include <linux/cpu_rmap.h> 41 #include <linux/crash_dump.h> 42 43 #include <linux/atomic.h> 44 45 #include <linux/timecounter.h> 46 47 #define MAX_MSIX_P_PORT 17 48 #define MAX_MSIX 64 49 #define MIN_MSIX_P_PORT 5 50 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ 51 (dev_cap).num_ports * MIN_MSIX_P_PORT) 52 53 #define MLX4_MAX_100M_UNITS_VAL 255 /* 54 * work around: can't set values 55 * greater then this value when 56 * using 100 Mbps units. 57 */ 58 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 59 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 60 #define MLX4_RATELIMIT_DEFAULT 0x00ff 61 62 #define MLX4_ROCE_MAX_GIDS 128 63 #define MLX4_ROCE_PF_GIDS 16 64 65 enum { 66 MLX4_FLAG_MSI_X = 1 << 0, 67 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 68 MLX4_FLAG_MASTER = 1 << 2, 69 MLX4_FLAG_SLAVE = 1 << 3, 70 MLX4_FLAG_SRIOV = 1 << 4, 71 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 72 MLX4_FLAG_BONDED = 1 << 7 73 }; 74 75 enum { 76 MLX4_PORT_CAP_IS_SM = 1 << 1, 77 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 78 }; 79 80 enum { 81 MLX4_MAX_PORTS = 2, 82 MLX4_MAX_PORT_PKEYS = 128, 83 MLX4_MAX_PORT_GIDS = 128 84 }; 85 86 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 87 * These qkeys must not be allowed for general use. This is a 64k range, 88 * and to test for violation, we use the mask (protect against future chg). 89 */ 90 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 91 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 92 93 enum { 94 MLX4_BOARD_ID_LEN = 64 95 }; 96 97 enum { 98 MLX4_MAX_NUM_PF = 16, 99 MLX4_MAX_NUM_VF = 126, 100 MLX4_MAX_NUM_VF_P_PORT = 64, 101 MLX4_MFUNC_MAX = 128, 102 MLX4_MAX_EQ_NUM = 1024, 103 MLX4_MFUNC_EQ_NUM = 4, 104 MLX4_MFUNC_MAX_EQES = 8, 105 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 106 }; 107 108 /* Driver supports 3 diffrent device methods to manage traffic steering: 109 * -device managed - High level API for ib and eth flow steering. FW is 110 * managing flow steering tables. 111 * - B0 steering mode - Common low level API for ib and (if supported) eth. 112 * - A0 steering mode - Limited low level API for eth. In case of IB, 113 * B0 mode is in use. 114 */ 115 enum { 116 MLX4_STEERING_MODE_A0, 117 MLX4_STEERING_MODE_B0, 118 MLX4_STEERING_MODE_DEVICE_MANAGED 119 }; 120 121 enum { 122 MLX4_STEERING_DMFS_A0_DEFAULT, 123 MLX4_STEERING_DMFS_A0_DYNAMIC, 124 MLX4_STEERING_DMFS_A0_STATIC, 125 MLX4_STEERING_DMFS_A0_DISABLE, 126 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED 127 }; 128 129 static inline const char *mlx4_steering_mode_str(int steering_mode) 130 { 131 switch (steering_mode) { 132 case MLX4_STEERING_MODE_A0: 133 return "A0 steering"; 134 135 case MLX4_STEERING_MODE_B0: 136 return "B0 steering"; 137 138 case MLX4_STEERING_MODE_DEVICE_MANAGED: 139 return "Device managed flow steering"; 140 141 default: 142 return "Unrecognize steering mode"; 143 } 144 } 145 146 enum { 147 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 148 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 149 }; 150 151 enum { 152 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 153 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 154 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 155 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 156 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 157 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 158 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 159 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 160 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 161 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 162 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 163 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 164 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 165 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 166 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 167 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 168 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 169 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 170 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 171 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 172 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 173 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 174 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 175 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 176 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 177 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, 178 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 179 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 180 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 181 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 182 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 183 }; 184 185 enum { 186 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 187 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 188 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 189 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 190 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 191 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 192 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 193 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 194 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 195 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 196 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 197 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, 198 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, 199 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, 200 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, 201 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 202 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 203 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 204 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 205 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, 206 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, 207 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, 208 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, 209 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, 210 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, 211 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, 212 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, 213 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, 214 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, 215 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29, 216 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30, 217 }; 218 219 enum { 220 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, 221 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 222 }; 223 224 enum { 225 MLX4_VF_CAP_FLAG_RESET = 1 << 0 226 }; 227 228 /* bit enums for an 8-bit flags field indicating special use 229 * QPs which require special handling in qp_reserve_range. 230 * Currently, this only includes QPs used by the ETH interface, 231 * where we expect to use blueflame. These QPs must not have 232 * bits 6 and 7 set in their qp number. 233 * 234 * This enum may use only bits 0..7. 235 */ 236 enum { 237 MLX4_RESERVE_A0_QP = 1 << 6, 238 MLX4_RESERVE_ETH_BF_QP = 1 << 7, 239 }; 240 241 enum { 242 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 243 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, 244 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, 245 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 246 }; 247 248 enum { 249 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 250 }; 251 252 enum { 253 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 254 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, 255 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 256 }; 257 258 259 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 260 261 enum { 262 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 263 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 264 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 265 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 266 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 267 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 268 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, 269 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 270 }; 271 272 enum { 273 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP 274 }; 275 276 enum mlx4_event { 277 MLX4_EVENT_TYPE_COMP = 0x00, 278 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 279 MLX4_EVENT_TYPE_COMM_EST = 0x02, 280 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 281 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 282 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 283 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 284 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 285 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 286 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 287 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 288 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 289 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 290 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 291 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 292 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 293 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 294 MLX4_EVENT_TYPE_CMD = 0x0a, 295 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 296 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 297 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 298 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 299 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 300 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 301 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 302 MLX4_EVENT_TYPE_NONE = 0xff, 303 }; 304 305 enum { 306 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 307 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 308 }; 309 310 enum { 311 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 312 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 313 }; 314 315 enum { 316 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 317 }; 318 319 enum slave_port_state { 320 SLAVE_PORT_DOWN = 0, 321 SLAVE_PENDING_UP, 322 SLAVE_PORT_UP, 323 }; 324 325 enum slave_port_gen_event { 326 SLAVE_PORT_GEN_EVENT_DOWN = 0, 327 SLAVE_PORT_GEN_EVENT_UP, 328 SLAVE_PORT_GEN_EVENT_NONE, 329 }; 330 331 enum slave_port_state_event { 332 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 333 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 334 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 335 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 336 }; 337 338 enum { 339 MLX4_PERM_LOCAL_READ = 1 << 10, 340 MLX4_PERM_LOCAL_WRITE = 1 << 11, 341 MLX4_PERM_REMOTE_READ = 1 << 12, 342 MLX4_PERM_REMOTE_WRITE = 1 << 13, 343 MLX4_PERM_ATOMIC = 1 << 14, 344 MLX4_PERM_BIND_MW = 1 << 15, 345 MLX4_PERM_MASK = 0xFC00 346 }; 347 348 enum { 349 MLX4_OPCODE_NOP = 0x00, 350 MLX4_OPCODE_SEND_INVAL = 0x01, 351 MLX4_OPCODE_RDMA_WRITE = 0x08, 352 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 353 MLX4_OPCODE_SEND = 0x0a, 354 MLX4_OPCODE_SEND_IMM = 0x0b, 355 MLX4_OPCODE_LSO = 0x0e, 356 MLX4_OPCODE_RDMA_READ = 0x10, 357 MLX4_OPCODE_ATOMIC_CS = 0x11, 358 MLX4_OPCODE_ATOMIC_FA = 0x12, 359 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 360 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 361 MLX4_OPCODE_BIND_MW = 0x18, 362 MLX4_OPCODE_FMR = 0x19, 363 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 364 MLX4_OPCODE_CONFIG_CMD = 0x1f, 365 366 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 367 MLX4_RECV_OPCODE_SEND = 0x01, 368 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 369 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 370 371 MLX4_CQE_OPCODE_ERROR = 0x1e, 372 MLX4_CQE_OPCODE_RESIZE = 0x16, 373 }; 374 375 enum { 376 MLX4_STAT_RATE_OFFSET = 5 377 }; 378 379 enum mlx4_protocol { 380 MLX4_PROT_IB_IPV6 = 0, 381 MLX4_PROT_ETH, 382 MLX4_PROT_IB_IPV4, 383 MLX4_PROT_FCOE 384 }; 385 386 enum { 387 MLX4_MTT_FLAG_PRESENT = 1 388 }; 389 390 enum mlx4_qp_region { 391 MLX4_QP_REGION_FW = 0, 392 MLX4_QP_REGION_RSS_RAW_ETH, 393 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, 394 MLX4_QP_REGION_ETH_ADDR, 395 MLX4_QP_REGION_FC_ADDR, 396 MLX4_QP_REGION_FC_EXCH, 397 MLX4_NUM_QP_REGION 398 }; 399 400 enum mlx4_port_type { 401 MLX4_PORT_TYPE_NONE = 0, 402 MLX4_PORT_TYPE_IB = 1, 403 MLX4_PORT_TYPE_ETH = 2, 404 MLX4_PORT_TYPE_AUTO = 3 405 }; 406 407 enum mlx4_special_vlan_idx { 408 MLX4_NO_VLAN_IDX = 0, 409 MLX4_VLAN_MISS_IDX, 410 MLX4_VLAN_REGULAR 411 }; 412 413 enum mlx4_steer_type { 414 MLX4_MC_STEER = 0, 415 MLX4_UC_STEER, 416 MLX4_NUM_STEERS 417 }; 418 419 enum { 420 MLX4_NUM_FEXCH = 64 * 1024, 421 }; 422 423 enum { 424 MLX4_MAX_FAST_REG_PAGES = 511, 425 }; 426 427 enum { 428 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 429 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 430 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 431 }; 432 433 /* Port mgmt change event handling */ 434 enum { 435 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 436 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 437 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 438 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 439 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 440 }; 441 442 enum { 443 MLX4_DEVICE_STATE_UP = 1 << 0, 444 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, 445 }; 446 447 enum { 448 MLX4_INTERFACE_STATE_UP = 1 << 0, 449 MLX4_INTERFACE_STATE_DELETION = 1 << 1, 450 }; 451 452 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 453 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 454 455 enum mlx4_module_id { 456 MLX4_MODULE_ID_SFP = 0x3, 457 MLX4_MODULE_ID_QSFP = 0xC, 458 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 459 MLX4_MODULE_ID_QSFP28 = 0x11, 460 }; 461 462 enum { /* rl */ 463 MLX4_QP_RATE_LIMIT_NONE = 0, 464 MLX4_QP_RATE_LIMIT_KBS = 1, 465 MLX4_QP_RATE_LIMIT_MBS = 2, 466 MLX4_QP_RATE_LIMIT_GBS = 3 467 }; 468 469 struct mlx4_rate_limit_caps { 470 u16 num_rates; /* Number of different rates */ 471 u8 min_unit; 472 u16 min_val; 473 u8 max_unit; 474 u16 max_val; 475 }; 476 477 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 478 { 479 return (major << 32) | (minor << 16) | subminor; 480 } 481 482 struct mlx4_phys_caps { 483 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 484 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 485 u32 num_phys_eqs; 486 u32 base_sqpn; 487 u32 base_proxy_sqpn; 488 u32 base_tunnel_sqpn; 489 }; 490 491 struct mlx4_caps { 492 u64 fw_ver; 493 u32 function; 494 int num_ports; 495 int vl_cap[MLX4_MAX_PORTS + 1]; 496 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 497 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 498 u64 def_mac[MLX4_MAX_PORTS + 1]; 499 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 500 int gid_table_len[MLX4_MAX_PORTS + 1]; 501 int pkey_table_len[MLX4_MAX_PORTS + 1]; 502 int trans_type[MLX4_MAX_PORTS + 1]; 503 int vendor_oui[MLX4_MAX_PORTS + 1]; 504 int wavelength[MLX4_MAX_PORTS + 1]; 505 u64 trans_code[MLX4_MAX_PORTS + 1]; 506 int local_ca_ack_delay; 507 int num_uars; 508 u32 uar_page_size; 509 int bf_reg_size; 510 int bf_regs_per_page; 511 int max_sq_sg; 512 int max_rq_sg; 513 int num_qps; 514 int max_wqes; 515 int max_sq_desc_sz; 516 int max_rq_desc_sz; 517 int max_qp_init_rdma; 518 int max_qp_dest_rdma; 519 u32 *qp0_qkey; 520 u32 *qp0_proxy; 521 u32 *qp1_proxy; 522 u32 *qp0_tunnel; 523 u32 *qp1_tunnel; 524 int num_srqs; 525 int max_srq_wqes; 526 int max_srq_sge; 527 int reserved_srqs; 528 int num_cqs; 529 int max_cqes; 530 int reserved_cqs; 531 int num_sys_eqs; 532 int num_eqs; 533 int reserved_eqs; 534 int num_comp_vectors; 535 int num_mpts; 536 int max_fmr_maps; 537 int num_mtts; 538 int fmr_reserved_mtts; 539 int reserved_mtts; 540 int reserved_mrws; 541 int reserved_uars; 542 int num_mgms; 543 int num_amgms; 544 int reserved_mcgs; 545 int num_qp_per_mgm; 546 int steering_mode; 547 int dmfs_high_steer_mode; 548 int fs_log_max_ucast_qp_range_size; 549 int num_pds; 550 int reserved_pds; 551 int max_xrcds; 552 int reserved_xrcds; 553 int mtt_entry_sz; 554 u32 max_msg_sz; 555 u32 page_size_cap; 556 u64 flags; 557 u64 flags2; 558 u32 bmme_flags; 559 u32 reserved_lkey; 560 u16 stat_rate_support; 561 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 562 int max_gso_sz; 563 int max_rss_tbl_sz; 564 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 565 int reserved_qps; 566 int reserved_qps_base[MLX4_NUM_QP_REGION]; 567 int log_num_macs; 568 int log_num_vlans; 569 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 570 u8 supported_type[MLX4_MAX_PORTS + 1]; 571 u8 suggested_type[MLX4_MAX_PORTS + 1]; 572 u8 default_sense[MLX4_MAX_PORTS + 1]; 573 u32 port_mask[MLX4_MAX_PORTS + 1]; 574 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 575 u32 max_counters; 576 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 577 u16 sqp_demux; 578 u32 eqe_size; 579 u32 cqe_size; 580 u8 eqe_factor; 581 u32 userspace_caps; /* userspace must be aware of these */ 582 u32 function_caps; /* VFs must be aware of these */ 583 u16 hca_core_clock; 584 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 585 int tunnel_offload_mode; 586 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; 587 u8 phv_bit[MLX4_MAX_PORTS + 1]; 588 u8 alloc_res_qp_mask; 589 u32 dmfs_high_rate_qpn_base; 590 u32 dmfs_high_rate_qpn_range; 591 u32 vf_caps; 592 struct mlx4_rate_limit_caps rl_caps; 593 }; 594 595 struct mlx4_buf_list { 596 void *buf; 597 dma_addr_t map; 598 }; 599 600 struct mlx4_buf { 601 struct mlx4_buf_list direct; 602 struct mlx4_buf_list *page_list; 603 int nbufs; 604 int npages; 605 int page_shift; 606 }; 607 608 struct mlx4_mtt { 609 u32 offset; 610 int order; 611 int page_shift; 612 }; 613 614 enum { 615 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 616 }; 617 618 struct mlx4_db_pgdir { 619 struct list_head list; 620 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 621 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 622 unsigned long *bits[2]; 623 __be32 *db_page; 624 dma_addr_t db_dma; 625 }; 626 627 struct mlx4_ib_user_db_page; 628 629 struct mlx4_db { 630 __be32 *db; 631 union { 632 struct mlx4_db_pgdir *pgdir; 633 struct mlx4_ib_user_db_page *user_page; 634 } u; 635 dma_addr_t dma; 636 int index; 637 int order; 638 }; 639 640 struct mlx4_hwq_resources { 641 struct mlx4_db db; 642 struct mlx4_mtt mtt; 643 struct mlx4_buf buf; 644 }; 645 646 struct mlx4_mr { 647 struct mlx4_mtt mtt; 648 u64 iova; 649 u64 size; 650 u32 key; 651 u32 pd; 652 u32 access; 653 int enabled; 654 }; 655 656 enum mlx4_mw_type { 657 MLX4_MW_TYPE_1 = 1, 658 MLX4_MW_TYPE_2 = 2, 659 }; 660 661 struct mlx4_mw { 662 u32 key; 663 u32 pd; 664 enum mlx4_mw_type type; 665 int enabled; 666 }; 667 668 struct mlx4_fmr { 669 struct mlx4_mr mr; 670 struct mlx4_mpt_entry *mpt; 671 __be64 *mtts; 672 dma_addr_t dma_handle; 673 int max_pages; 674 int max_maps; 675 int maps; 676 u8 page_shift; 677 }; 678 679 struct mlx4_uar { 680 unsigned long pfn; 681 int index; 682 struct list_head bf_list; 683 unsigned free_bf_bmap; 684 void __iomem *map; 685 void __iomem *bf_map; 686 }; 687 688 struct mlx4_bf { 689 unsigned int offset; 690 int buf_size; 691 struct mlx4_uar *uar; 692 void __iomem *reg; 693 }; 694 695 struct mlx4_cq { 696 void (*comp) (struct mlx4_cq *); 697 void (*event) (struct mlx4_cq *, enum mlx4_event); 698 699 struct mlx4_uar *uar; 700 701 u32 cons_index; 702 703 u16 irq; 704 __be32 *set_ci_db; 705 __be32 *arm_db; 706 int arm_sn; 707 708 int cqn; 709 unsigned vector; 710 711 atomic_t refcount; 712 struct completion free; 713 struct { 714 struct list_head list; 715 void (*comp)(struct mlx4_cq *); 716 void *priv; 717 } tasklet_ctx; 718 int reset_notify_added; 719 struct list_head reset_notify; 720 }; 721 722 struct mlx4_qp { 723 void (*event) (struct mlx4_qp *, enum mlx4_event); 724 725 int qpn; 726 727 atomic_t refcount; 728 struct completion free; 729 }; 730 731 struct mlx4_srq { 732 void (*event) (struct mlx4_srq *, enum mlx4_event); 733 734 int srqn; 735 int max; 736 int max_gs; 737 int wqe_shift; 738 739 atomic_t refcount; 740 struct completion free; 741 }; 742 743 struct mlx4_av { 744 __be32 port_pd; 745 u8 reserved1; 746 u8 g_slid; 747 __be16 dlid; 748 u8 reserved2; 749 u8 gid_index; 750 u8 stat_rate; 751 u8 hop_limit; 752 __be32 sl_tclass_flowlabel; 753 u8 dgid[16]; 754 }; 755 756 struct mlx4_eth_av { 757 __be32 port_pd; 758 u8 reserved1; 759 u8 smac_idx; 760 u16 reserved2; 761 u8 reserved3; 762 u8 gid_index; 763 u8 stat_rate; 764 u8 hop_limit; 765 __be32 sl_tclass_flowlabel; 766 u8 dgid[16]; 767 u8 s_mac[6]; 768 u8 reserved4[2]; 769 __be16 vlan; 770 u8 mac[ETH_ALEN]; 771 }; 772 773 union mlx4_ext_av { 774 struct mlx4_av ib; 775 struct mlx4_eth_av eth; 776 }; 777 778 /* Counters should be saturate once they reach their maximum value */ 779 #define ASSIGN_32BIT_COUNTER(counter, value) do { \ 780 if ((value) > U32_MAX) \ 781 counter = cpu_to_be32(U32_MAX); \ 782 else \ 783 counter = cpu_to_be32(value); \ 784 } while (0) 785 786 struct mlx4_counter { 787 u8 reserved1[3]; 788 u8 counter_mode; 789 __be32 num_ifc; 790 u32 reserved2[2]; 791 __be64 rx_frames; 792 __be64 rx_bytes; 793 __be64 tx_frames; 794 __be64 tx_bytes; 795 }; 796 797 struct mlx4_quotas { 798 int qp; 799 int cq; 800 int srq; 801 int mpt; 802 int mtt; 803 int counter; 804 int xrcd; 805 }; 806 807 struct mlx4_vf_dev { 808 u8 min_port; 809 u8 n_ports; 810 }; 811 812 struct mlx4_dev_persistent { 813 struct pci_dev *pdev; 814 struct mlx4_dev *dev; 815 int nvfs[MLX4_MAX_PORTS + 1]; 816 int num_vfs; 817 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; 818 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; 819 struct work_struct catas_work; 820 struct workqueue_struct *catas_wq; 821 struct mutex device_state_mutex; /* protect HW state */ 822 u8 state; 823 struct mutex interface_state_mutex; /* protect SW state */ 824 u8 interface_state; 825 }; 826 827 struct mlx4_dev { 828 struct mlx4_dev_persistent *persist; 829 unsigned long flags; 830 unsigned long num_slaves; 831 struct mlx4_caps caps; 832 struct mlx4_phys_caps phys_caps; 833 struct mlx4_quotas quotas; 834 struct radix_tree_root qp_table_tree; 835 u8 rev_id; 836 char board_id[MLX4_BOARD_ID_LEN]; 837 int numa_node; 838 int oper_log_mgm_entry_size; 839 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 840 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 841 struct mlx4_vf_dev *dev_vfs; 842 }; 843 844 struct mlx4_clock_params { 845 u64 offset; 846 u8 bar; 847 u8 size; 848 }; 849 850 struct mlx4_eqe { 851 u8 reserved1; 852 u8 type; 853 u8 reserved2; 854 u8 subtype; 855 union { 856 u32 raw[6]; 857 struct { 858 __be32 cqn; 859 } __packed comp; 860 struct { 861 u16 reserved1; 862 __be16 token; 863 u32 reserved2; 864 u8 reserved3[3]; 865 u8 status; 866 __be64 out_param; 867 } __packed cmd; 868 struct { 869 __be32 qpn; 870 } __packed qp; 871 struct { 872 __be32 srqn; 873 } __packed srq; 874 struct { 875 __be32 cqn; 876 u32 reserved1; 877 u8 reserved2[3]; 878 u8 syndrome; 879 } __packed cq_err; 880 struct { 881 u32 reserved1[2]; 882 __be32 port; 883 } __packed port_change; 884 struct { 885 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 886 u32 reserved; 887 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 888 } __packed comm_channel_arm; 889 struct { 890 u8 port; 891 u8 reserved[3]; 892 __be64 mac; 893 } __packed mac_update; 894 struct { 895 __be32 slave_id; 896 } __packed flr_event; 897 struct { 898 __be16 current_temperature; 899 __be16 warning_threshold; 900 } __packed warming; 901 struct { 902 u8 reserved[3]; 903 u8 port; 904 union { 905 struct { 906 __be16 mstr_sm_lid; 907 __be16 port_lid; 908 __be32 changed_attr; 909 u8 reserved[3]; 910 u8 mstr_sm_sl; 911 __be64 gid_prefix; 912 } __packed port_info; 913 struct { 914 __be32 block_ptr; 915 __be32 tbl_entries_mask; 916 } __packed tbl_change_info; 917 } params; 918 } __packed port_mgmt_change; 919 struct { 920 u8 reserved[3]; 921 u8 port; 922 u32 reserved1[5]; 923 } __packed bad_cable; 924 } event; 925 u8 slave_id; 926 u8 reserved3[2]; 927 u8 owner; 928 } __packed; 929 930 struct mlx4_init_port_param { 931 int set_guid0; 932 int set_node_guid; 933 int set_si_guid; 934 u16 mtu; 935 int port_width_cap; 936 u16 vl_cap; 937 u16 max_gid; 938 u16 max_pkey; 939 u64 guid0; 940 u64 node_guid; 941 u64 si_guid; 942 }; 943 944 #define MAD_IFC_DATA_SZ 192 945 /* MAD IFC Mailbox */ 946 struct mlx4_mad_ifc { 947 u8 base_version; 948 u8 mgmt_class; 949 u8 class_version; 950 u8 method; 951 __be16 status; 952 __be16 class_specific; 953 __be64 tid; 954 __be16 attr_id; 955 __be16 resv; 956 __be32 attr_mod; 957 __be64 mkey; 958 __be16 dr_slid; 959 __be16 dr_dlid; 960 u8 reserved[28]; 961 u8 data[MAD_IFC_DATA_SZ]; 962 } __packed; 963 964 #define mlx4_foreach_port(port, dev, type) \ 965 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 966 if ((type) == (dev)->caps.port_mask[(port)]) 967 968 #define mlx4_foreach_non_ib_transport_port(port, dev) \ 969 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 970 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) 971 972 #define mlx4_foreach_ib_transport_port(port, dev) \ 973 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 974 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 975 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 976 977 #define MLX4_INVALID_SLAVE_ID 0xFF 978 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1) 979 980 void handle_port_mgmt_change_event(struct work_struct *work); 981 982 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 983 { 984 return dev->caps.function; 985 } 986 987 static inline int mlx4_is_master(struct mlx4_dev *dev) 988 { 989 return dev->flags & MLX4_FLAG_MASTER; 990 } 991 992 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 993 { 994 return dev->phys_caps.base_sqpn + 8 + 995 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 996 } 997 998 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 999 { 1000 return (qpn < dev->phys_caps.base_sqpn + 8 + 1001 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && 1002 qpn >= dev->phys_caps.base_sqpn) || 1003 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); 1004 } 1005 1006 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 1007 { 1008 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 1009 1010 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 1011 return 1; 1012 1013 return 0; 1014 } 1015 1016 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 1017 { 1018 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 1019 } 1020 1021 static inline int mlx4_is_slave(struct mlx4_dev *dev) 1022 { 1023 return dev->flags & MLX4_FLAG_SLAVE; 1024 } 1025 1026 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) 1027 { 1028 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; 1029 } 1030 1031 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1032 struct mlx4_buf *buf, gfp_t gfp); 1033 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1034 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 1035 { 1036 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 1037 return buf->direct.buf + offset; 1038 else 1039 return buf->page_list[offset >> PAGE_SHIFT].buf + 1040 (offset & (PAGE_SIZE - 1)); 1041 } 1042 1043 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1044 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1045 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1046 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1047 1048 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1049 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1050 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1051 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1052 1053 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1054 struct mlx4_mtt *mtt); 1055 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1056 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1057 1058 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1059 int npages, int page_shift, struct mlx4_mr *mr); 1060 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1061 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1062 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1063 struct mlx4_mw *mw); 1064 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1065 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1066 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1067 int start_index, int npages, u64 *page_list); 1068 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1069 struct mlx4_buf *buf, gfp_t gfp); 1070 1071 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, 1072 gfp_t gfp); 1073 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1074 1075 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1076 int size, int max_direct); 1077 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1078 int size); 1079 1080 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1081 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 1082 unsigned vector, int collapsed, int timestamp_en); 1083 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1084 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1085 int *base, u8 flags); 1086 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1087 1088 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, 1089 gfp_t gfp); 1090 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1091 1092 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1093 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1094 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1095 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1096 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1097 1098 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1099 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1100 1101 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1102 int block_mcast_loopback, enum mlx4_protocol prot); 1103 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1104 enum mlx4_protocol prot); 1105 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1106 u8 port, int block_mcast_loopback, 1107 enum mlx4_protocol protocol, u64 *reg_id); 1108 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1109 enum mlx4_protocol protocol, u64 reg_id); 1110 1111 enum { 1112 MLX4_DOMAIN_UVERBS = 0x1000, 1113 MLX4_DOMAIN_ETHTOOL = 0x2000, 1114 MLX4_DOMAIN_RFS = 0x3000, 1115 MLX4_DOMAIN_NIC = 0x5000, 1116 }; 1117 1118 enum mlx4_net_trans_rule_id { 1119 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1120 MLX4_NET_TRANS_RULE_ID_IB, 1121 MLX4_NET_TRANS_RULE_ID_IPV6, 1122 MLX4_NET_TRANS_RULE_ID_IPV4, 1123 MLX4_NET_TRANS_RULE_ID_TCP, 1124 MLX4_NET_TRANS_RULE_ID_UDP, 1125 MLX4_NET_TRANS_RULE_ID_VXLAN, 1126 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1127 }; 1128 1129 extern const u16 __sw_id_hw[]; 1130 1131 static inline int map_hw_to_sw_id(u16 header_id) 1132 { 1133 1134 int i; 1135 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1136 if (header_id == __sw_id_hw[i]) 1137 return i; 1138 } 1139 return -EINVAL; 1140 } 1141 1142 enum mlx4_net_trans_promisc_mode { 1143 MLX4_FS_REGULAR = 1, 1144 MLX4_FS_ALL_DEFAULT, 1145 MLX4_FS_MC_DEFAULT, 1146 MLX4_FS_UC_SNIFFER, 1147 MLX4_FS_MC_SNIFFER, 1148 MLX4_FS_MODE_NUM, /* should be last */ 1149 }; 1150 1151 struct mlx4_spec_eth { 1152 u8 dst_mac[ETH_ALEN]; 1153 u8 dst_mac_msk[ETH_ALEN]; 1154 u8 src_mac[ETH_ALEN]; 1155 u8 src_mac_msk[ETH_ALEN]; 1156 u8 ether_type_enable; 1157 __be16 ether_type; 1158 __be16 vlan_id_msk; 1159 __be16 vlan_id; 1160 }; 1161 1162 struct mlx4_spec_tcp_udp { 1163 __be16 dst_port; 1164 __be16 dst_port_msk; 1165 __be16 src_port; 1166 __be16 src_port_msk; 1167 }; 1168 1169 struct mlx4_spec_ipv4 { 1170 __be32 dst_ip; 1171 __be32 dst_ip_msk; 1172 __be32 src_ip; 1173 __be32 src_ip_msk; 1174 }; 1175 1176 struct mlx4_spec_ib { 1177 __be32 l3_qpn; 1178 __be32 qpn_msk; 1179 u8 dst_gid[16]; 1180 u8 dst_gid_msk[16]; 1181 }; 1182 1183 struct mlx4_spec_vxlan { 1184 __be32 vni; 1185 __be32 vni_mask; 1186 1187 }; 1188 1189 struct mlx4_spec_list { 1190 struct list_head list; 1191 enum mlx4_net_trans_rule_id id; 1192 union { 1193 struct mlx4_spec_eth eth; 1194 struct mlx4_spec_ib ib; 1195 struct mlx4_spec_ipv4 ipv4; 1196 struct mlx4_spec_tcp_udp tcp_udp; 1197 struct mlx4_spec_vxlan vxlan; 1198 }; 1199 }; 1200 1201 enum mlx4_net_trans_hw_rule_queue { 1202 MLX4_NET_TRANS_Q_FIFO, 1203 MLX4_NET_TRANS_Q_LIFO, 1204 }; 1205 1206 struct mlx4_net_trans_rule { 1207 struct list_head list; 1208 enum mlx4_net_trans_hw_rule_queue queue_mode; 1209 bool exclusive; 1210 bool allow_loopback; 1211 enum mlx4_net_trans_promisc_mode promisc_mode; 1212 u8 port; 1213 u16 priority; 1214 u32 qpn; 1215 }; 1216 1217 struct mlx4_net_trans_rule_hw_ctrl { 1218 __be16 prio; 1219 u8 type; 1220 u8 flags; 1221 u8 rsvd1; 1222 u8 funcid; 1223 u8 vep; 1224 u8 port; 1225 __be32 qpn; 1226 __be32 rsvd2; 1227 }; 1228 1229 struct mlx4_net_trans_rule_hw_ib { 1230 u8 size; 1231 u8 rsvd1; 1232 __be16 id; 1233 u32 rsvd2; 1234 __be32 l3_qpn; 1235 __be32 qpn_mask; 1236 u8 dst_gid[16]; 1237 u8 dst_gid_msk[16]; 1238 } __packed; 1239 1240 struct mlx4_net_trans_rule_hw_eth { 1241 u8 size; 1242 u8 rsvd; 1243 __be16 id; 1244 u8 rsvd1[6]; 1245 u8 dst_mac[6]; 1246 u16 rsvd2; 1247 u8 dst_mac_msk[6]; 1248 u16 rsvd3; 1249 u8 src_mac[6]; 1250 u16 rsvd4; 1251 u8 src_mac_msk[6]; 1252 u8 rsvd5; 1253 u8 ether_type_enable; 1254 __be16 ether_type; 1255 __be16 vlan_tag_msk; 1256 __be16 vlan_tag; 1257 } __packed; 1258 1259 struct mlx4_net_trans_rule_hw_tcp_udp { 1260 u8 size; 1261 u8 rsvd; 1262 __be16 id; 1263 __be16 rsvd1[3]; 1264 __be16 dst_port; 1265 __be16 rsvd2; 1266 __be16 dst_port_msk; 1267 __be16 rsvd3; 1268 __be16 src_port; 1269 __be16 rsvd4; 1270 __be16 src_port_msk; 1271 } __packed; 1272 1273 struct mlx4_net_trans_rule_hw_ipv4 { 1274 u8 size; 1275 u8 rsvd; 1276 __be16 id; 1277 __be32 rsvd1; 1278 __be32 dst_ip; 1279 __be32 dst_ip_msk; 1280 __be32 src_ip; 1281 __be32 src_ip_msk; 1282 } __packed; 1283 1284 struct mlx4_net_trans_rule_hw_vxlan { 1285 u8 size; 1286 u8 rsvd; 1287 __be16 id; 1288 __be32 rsvd1; 1289 __be32 vni; 1290 __be32 vni_mask; 1291 } __packed; 1292 1293 struct _rule_hw { 1294 union { 1295 struct { 1296 u8 size; 1297 u8 rsvd; 1298 __be16 id; 1299 }; 1300 struct mlx4_net_trans_rule_hw_eth eth; 1301 struct mlx4_net_trans_rule_hw_ib ib; 1302 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1303 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1304 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1305 }; 1306 }; 1307 1308 enum { 1309 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1310 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1311 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1312 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1313 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1314 }; 1315 1316 1317 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1318 enum mlx4_net_trans_promisc_mode mode); 1319 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1320 enum mlx4_net_trans_promisc_mode mode); 1321 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1322 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1323 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1324 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1325 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1326 1327 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1328 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1329 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1330 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1331 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1332 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1333 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1334 u8 promisc); 1335 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); 1336 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, 1337 u8 ignore_fcs_value); 1338 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1339 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val); 1340 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv); 1341 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1342 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1343 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1344 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1345 1346 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1347 int npages, u64 iova, u32 *lkey, u32 *rkey); 1348 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1349 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1350 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1351 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1352 u32 *lkey, u32 *rkey); 1353 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1354 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1355 int mlx4_test_interrupts(struct mlx4_dev *dev); 1356 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port); 1357 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector); 1358 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port); 1359 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector); 1360 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1361 1362 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector); 1363 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); 1364 1365 int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1366 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1367 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1368 1369 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1370 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1371 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port); 1372 1373 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, 1374 int port); 1375 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); 1376 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); 1377 int mlx4_flow_attach(struct mlx4_dev *dev, 1378 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1379 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1380 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1381 enum mlx4_net_trans_promisc_mode flow_type); 1382 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1383 enum mlx4_net_trans_rule_id id); 1384 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1385 1386 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, 1387 int port, int qpn, u16 prio, u64 *reg_id); 1388 1389 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1390 int i, int val); 1391 1392 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1393 1394 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1395 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1396 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1397 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1398 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1399 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1400 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1401 1402 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1403 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1404 1405 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1406 int *slave_id); 1407 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1408 u8 *gid); 1409 1410 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1411 u32 max_range_qpn); 1412 1413 cycle_t mlx4_read_clock(struct mlx4_dev *dev); 1414 1415 struct mlx4_active_ports { 1416 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1417 }; 1418 /* Returns a bitmap of the physical ports which are assigned to slave */ 1419 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1420 1421 /* Returns the physical port that represents the virtual port of the slave, */ 1422 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1423 /* mapping is returned. */ 1424 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1425 1426 struct mlx4_slaves_pport { 1427 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1428 }; 1429 /* Returns a bitmap of all slaves that are assigned to port. */ 1430 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1431 int port); 1432 1433 /* Returns a bitmap of all slaves that are assigned exactly to all the */ 1434 /* the ports that are set in crit_ports. */ 1435 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1436 struct mlx4_dev *dev, 1437 const struct mlx4_active_ports *crit_ports); 1438 1439 /* Returns the slave's virtual port that represents the physical port. */ 1440 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1441 1442 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1443 1444 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1445 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); 1446 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); 1447 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1448 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1449 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1450 int enable); 1451 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1452 struct mlx4_mpt_entry ***mpt_entry); 1453 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1454 struct mlx4_mpt_entry **mpt_entry); 1455 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, 1456 u32 pdn); 1457 int mlx4_mr_hw_change_access(struct mlx4_dev *dev, 1458 struct mlx4_mpt_entry *mpt_entry, 1459 u32 access); 1460 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, 1461 struct mlx4_mpt_entry **mpt_entry); 1462 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); 1463 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, 1464 u64 iova, u64 size, int npages, 1465 int page_shift, struct mlx4_mpt_entry *mpt_entry); 1466 1467 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1468 u16 offset, u16 size, u8 *data); 1469 1470 /* Returns true if running in low memory profile (kdump kernel) */ 1471 static inline bool mlx4_low_memory_profile(void) 1472 { 1473 return is_kdump_kernel(); 1474 } 1475 1476 /* ACCESS REG commands */ 1477 enum mlx4_access_reg_method { 1478 MLX4_ACCESS_REG_QUERY = 0x1, 1479 MLX4_ACCESS_REG_WRITE = 0x2, 1480 }; 1481 1482 /* ACCESS PTYS Reg command */ 1483 enum mlx4_ptys_proto { 1484 MLX4_PTYS_IB = 1<<0, 1485 MLX4_PTYS_EN = 1<<2, 1486 }; 1487 1488 struct mlx4_ptys_reg { 1489 u8 resrvd1; 1490 u8 local_port; 1491 u8 resrvd2; 1492 u8 proto_mask; 1493 __be32 resrvd3[2]; 1494 __be32 eth_proto_cap; 1495 __be16 ib_width_cap; 1496 __be16 ib_speed_cap; 1497 __be32 resrvd4; 1498 __be32 eth_proto_admin; 1499 __be16 ib_width_admin; 1500 __be16 ib_speed_admin; 1501 __be32 resrvd5; 1502 __be32 eth_proto_oper; 1503 __be16 ib_width_oper; 1504 __be16 ib_speed_oper; 1505 __be32 resrvd6; 1506 __be32 eth_proto_lp_adv; 1507 } __packed; 1508 1509 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 1510 enum mlx4_access_reg_method method, 1511 struct mlx4_ptys_reg *ptys_reg); 1512 1513 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1514 struct mlx4_clock_params *params); 1515 1516 #endif /* MLX4_DEVICE_H */ 1517