1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/pci.h> 37 #include <linux/completion.h> 38 #include <linux/radix-tree.h> 39 40 #include <asm/atomic.h> 41 42 enum { 43 MLX4_FLAG_MSI_X = 1 << 0, 44 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 45 }; 46 47 enum { 48 MLX4_MAX_PORTS = 2 49 }; 50 51 enum { 52 MLX4_BOARD_ID_LEN = 64 53 }; 54 55 enum { 56 MLX4_DEV_CAP_FLAG_RC = 1 << 0, 57 MLX4_DEV_CAP_FLAG_UC = 1 << 1, 58 MLX4_DEV_CAP_FLAG_UD = 1 << 2, 59 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6, 60 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7, 61 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8, 62 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9, 63 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16, 64 MLX4_DEV_CAP_FLAG_APM = 1 << 17, 65 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18, 66 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19, 67 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20, 68 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21 69 }; 70 71 enum mlx4_event { 72 MLX4_EVENT_TYPE_COMP = 0x00, 73 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 74 MLX4_EVENT_TYPE_COMM_EST = 0x02, 75 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 76 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 77 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 78 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 79 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 80 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 81 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 82 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 83 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 84 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 85 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 86 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 87 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 88 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 89 MLX4_EVENT_TYPE_CMD = 0x0a 90 }; 91 92 enum { 93 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 94 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 95 }; 96 97 enum { 98 MLX4_PERM_LOCAL_READ = 1 << 10, 99 MLX4_PERM_LOCAL_WRITE = 1 << 11, 100 MLX4_PERM_REMOTE_READ = 1 << 12, 101 MLX4_PERM_REMOTE_WRITE = 1 << 13, 102 MLX4_PERM_ATOMIC = 1 << 14 103 }; 104 105 enum { 106 MLX4_OPCODE_NOP = 0x00, 107 MLX4_OPCODE_SEND_INVAL = 0x01, 108 MLX4_OPCODE_RDMA_WRITE = 0x08, 109 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 110 MLX4_OPCODE_SEND = 0x0a, 111 MLX4_OPCODE_SEND_IMM = 0x0b, 112 MLX4_OPCODE_LSO = 0x0e, 113 MLX4_OPCODE_RDMA_READ = 0x10, 114 MLX4_OPCODE_ATOMIC_CS = 0x11, 115 MLX4_OPCODE_ATOMIC_FA = 0x12, 116 MLX4_OPCODE_ATOMIC_MASK_CS = 0x14, 117 MLX4_OPCODE_ATOMIC_MASK_FA = 0x15, 118 MLX4_OPCODE_BIND_MW = 0x18, 119 MLX4_OPCODE_FMR = 0x19, 120 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 121 MLX4_OPCODE_CONFIG_CMD = 0x1f, 122 123 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 124 MLX4_RECV_OPCODE_SEND = 0x01, 125 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 126 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 127 128 MLX4_CQE_OPCODE_ERROR = 0x1e, 129 MLX4_CQE_OPCODE_RESIZE = 0x16, 130 }; 131 132 enum { 133 MLX4_STAT_RATE_OFFSET = 5 134 }; 135 136 struct mlx4_caps { 137 u64 fw_ver; 138 int num_ports; 139 int vl_cap[MLX4_MAX_PORTS + 1]; 140 int mtu_cap[MLX4_MAX_PORTS + 1]; 141 int gid_table_len[MLX4_MAX_PORTS + 1]; 142 int pkey_table_len[MLX4_MAX_PORTS + 1]; 143 int local_ca_ack_delay; 144 int num_uars; 145 int bf_reg_size; 146 int bf_regs_per_page; 147 int max_sq_sg; 148 int max_rq_sg; 149 int num_qps; 150 int max_wqes; 151 int max_sq_desc_sz; 152 int max_rq_desc_sz; 153 int max_qp_init_rdma; 154 int max_qp_dest_rdma; 155 int reserved_qps; 156 int sqp_start; 157 int num_srqs; 158 int max_srq_wqes; 159 int max_srq_sge; 160 int reserved_srqs; 161 int num_cqs; 162 int max_cqes; 163 int reserved_cqs; 164 int num_eqs; 165 int reserved_eqs; 166 int num_mpts; 167 int num_mtt_segs; 168 int fmr_reserved_mtts; 169 int reserved_mtts; 170 int reserved_mrws; 171 int reserved_uars; 172 int num_mgms; 173 int num_amgms; 174 int reserved_mcgs; 175 int num_qp_per_mgm; 176 int num_pds; 177 int reserved_pds; 178 int mtt_entry_sz; 179 u32 max_msg_sz; 180 u32 page_size_cap; 181 u32 flags; 182 u16 stat_rate_support; 183 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 184 }; 185 186 struct mlx4_buf_list { 187 void *buf; 188 dma_addr_t map; 189 }; 190 191 struct mlx4_buf { 192 union { 193 struct mlx4_buf_list direct; 194 struct mlx4_buf_list *page_list; 195 } u; 196 int nbufs; 197 int npages; 198 int page_shift; 199 }; 200 201 struct mlx4_mtt { 202 u32 first_seg; 203 int order; 204 int page_shift; 205 }; 206 207 struct mlx4_mr { 208 struct mlx4_mtt mtt; 209 u64 iova; 210 u64 size; 211 u32 key; 212 u32 pd; 213 u32 access; 214 int enabled; 215 }; 216 217 struct mlx4_fmr { 218 struct mlx4_mr mr; 219 struct mlx4_mpt_entry *mpt; 220 __be64 *mtts; 221 dma_addr_t dma_handle; 222 int max_pages; 223 int max_maps; 224 int maps; 225 u8 page_shift; 226 }; 227 228 struct mlx4_uar { 229 unsigned long pfn; 230 int index; 231 }; 232 233 struct mlx4_cq { 234 void (*comp) (struct mlx4_cq *); 235 void (*event) (struct mlx4_cq *, enum mlx4_event); 236 237 struct mlx4_uar *uar; 238 239 u32 cons_index; 240 241 __be32 *set_ci_db; 242 __be32 *arm_db; 243 int arm_sn; 244 245 int cqn; 246 247 atomic_t refcount; 248 struct completion free; 249 }; 250 251 struct mlx4_qp { 252 void (*event) (struct mlx4_qp *, enum mlx4_event); 253 254 int qpn; 255 256 atomic_t refcount; 257 struct completion free; 258 }; 259 260 struct mlx4_srq { 261 void (*event) (struct mlx4_srq *, enum mlx4_event); 262 263 int srqn; 264 int max; 265 int max_gs; 266 int wqe_shift; 267 268 atomic_t refcount; 269 struct completion free; 270 }; 271 272 struct mlx4_av { 273 __be32 port_pd; 274 u8 reserved1; 275 u8 g_slid; 276 __be16 dlid; 277 u8 reserved2; 278 u8 gid_index; 279 u8 stat_rate; 280 u8 hop_limit; 281 __be32 sl_tclass_flowlabel; 282 u8 dgid[16]; 283 }; 284 285 struct mlx4_dev { 286 struct pci_dev *pdev; 287 unsigned long flags; 288 struct mlx4_caps caps; 289 struct radix_tree_root qp_table_tree; 290 u32 rev_id; 291 char board_id[MLX4_BOARD_ID_LEN]; 292 }; 293 294 struct mlx4_init_port_param { 295 int set_guid0; 296 int set_node_guid; 297 int set_si_guid; 298 u16 mtu; 299 int port_width_cap; 300 u16 vl_cap; 301 u16 max_gid; 302 u16 max_pkey; 303 u64 guid0; 304 u64 node_guid; 305 u64 si_guid; 306 }; 307 308 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 309 struct mlx4_buf *buf); 310 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 311 312 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 313 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 314 315 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 316 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 317 318 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 319 struct mlx4_mtt *mtt); 320 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 321 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 322 323 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 324 int npages, int page_shift, struct mlx4_mr *mr); 325 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 326 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 327 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 328 int start_index, int npages, u64 *page_list); 329 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 330 struct mlx4_buf *buf); 331 332 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 333 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq); 334 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 335 336 int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp); 337 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 338 339 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt, 340 u64 db_rec, struct mlx4_srq *srq); 341 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 342 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 343 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 344 345 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 346 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 347 348 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]); 349 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]); 350 351 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 352 int npages, u64 iova, u32 *lkey, u32 *rkey); 353 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 354 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 355 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 356 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 357 u32 *lkey, u32 *rkey); 358 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 359 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 360 361 #endif /* MLX4_DEVICE_H */ 362