1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/if_ether.h> 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 #include <linux/radix-tree.h> 40 #include <linux/cpu_rmap.h> 41 #include <linux/crash_dump.h> 42 43 #include <linux/atomic.h> 44 45 #include <linux/clocksource.h> 46 47 #define MAX_MSIX_P_PORT 17 48 #define MAX_MSIX 64 49 #define MSIX_LEGACY_SZ 4 50 #define MIN_MSIX_P_PORT 5 51 52 #define MLX4_NUM_UP 8 53 #define MLX4_NUM_TC 8 54 #define MLX4_MAX_100M_UNITS_VAL 255 /* 55 * work around: can't set values 56 * greater then this value when 57 * using 100 Mbps units. 58 */ 59 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 60 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 61 #define MLX4_RATELIMIT_DEFAULT 0x00ff 62 63 #define MLX4_ROCE_MAX_GIDS 128 64 #define MLX4_ROCE_PF_GIDS 16 65 66 enum { 67 MLX4_FLAG_MSI_X = 1 << 0, 68 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 69 MLX4_FLAG_MASTER = 1 << 2, 70 MLX4_FLAG_SLAVE = 1 << 3, 71 MLX4_FLAG_SRIOV = 1 << 4, 72 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 73 }; 74 75 enum { 76 MLX4_PORT_CAP_IS_SM = 1 << 1, 77 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 78 }; 79 80 enum { 81 MLX4_MAX_PORTS = 2, 82 MLX4_MAX_PORT_PKEYS = 128 83 }; 84 85 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 86 * These qkeys must not be allowed for general use. This is a 64k range, 87 * and to test for violation, we use the mask (protect against future chg). 88 */ 89 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 90 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 91 92 enum { 93 MLX4_BOARD_ID_LEN = 64 94 }; 95 96 enum { 97 MLX4_MAX_NUM_PF = 16, 98 MLX4_MAX_NUM_VF = 64, 99 MLX4_MAX_NUM_VF_P_PORT = 64, 100 MLX4_MFUNC_MAX = 80, 101 MLX4_MAX_EQ_NUM = 1024, 102 MLX4_MFUNC_EQ_NUM = 4, 103 MLX4_MFUNC_MAX_EQES = 8, 104 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 105 }; 106 107 /* Driver supports 3 diffrent device methods to manage traffic steering: 108 * -device managed - High level API for ib and eth flow steering. FW is 109 * managing flow steering tables. 110 * - B0 steering mode - Common low level API for ib and (if supported) eth. 111 * - A0 steering mode - Limited low level API for eth. In case of IB, 112 * B0 mode is in use. 113 */ 114 enum { 115 MLX4_STEERING_MODE_A0, 116 MLX4_STEERING_MODE_B0, 117 MLX4_STEERING_MODE_DEVICE_MANAGED 118 }; 119 120 static inline const char *mlx4_steering_mode_str(int steering_mode) 121 { 122 switch (steering_mode) { 123 case MLX4_STEERING_MODE_A0: 124 return "A0 steering"; 125 126 case MLX4_STEERING_MODE_B0: 127 return "B0 steering"; 128 129 case MLX4_STEERING_MODE_DEVICE_MANAGED: 130 return "Device managed flow steering"; 131 132 default: 133 return "Unrecognize steering mode"; 134 } 135 } 136 137 enum { 138 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 139 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 140 }; 141 142 enum { 143 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 144 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 145 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 146 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 147 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 148 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 149 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 150 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 151 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 152 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 153 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 154 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 155 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 156 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 157 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 158 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 159 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 160 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 161 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 162 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 163 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 164 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 165 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 166 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 167 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 168 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 169 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 170 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 171 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 172 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 173 }; 174 175 enum { 176 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 177 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 178 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 179 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 180 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 181 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 182 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 183 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 184 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 185 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 186 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 187 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, 188 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, 189 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13 190 }; 191 192 enum { 193 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 194 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, 195 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, 196 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 197 }; 198 199 enum { 200 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 201 }; 202 203 enum { 204 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 205 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1 206 }; 207 208 209 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 210 211 enum { 212 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 213 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 214 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 215 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 216 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 217 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 218 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 219 }; 220 221 enum mlx4_event { 222 MLX4_EVENT_TYPE_COMP = 0x00, 223 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 224 MLX4_EVENT_TYPE_COMM_EST = 0x02, 225 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 226 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 227 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 228 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 229 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 230 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 231 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 232 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 233 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 234 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 235 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 236 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 237 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 238 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 239 MLX4_EVENT_TYPE_CMD = 0x0a, 240 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 241 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 242 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 243 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 244 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 245 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 246 MLX4_EVENT_TYPE_NONE = 0xff, 247 }; 248 249 enum { 250 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 251 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 252 }; 253 254 enum { 255 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 256 }; 257 258 enum slave_port_state { 259 SLAVE_PORT_DOWN = 0, 260 SLAVE_PENDING_UP, 261 SLAVE_PORT_UP, 262 }; 263 264 enum slave_port_gen_event { 265 SLAVE_PORT_GEN_EVENT_DOWN = 0, 266 SLAVE_PORT_GEN_EVENT_UP, 267 SLAVE_PORT_GEN_EVENT_NONE, 268 }; 269 270 enum slave_port_state_event { 271 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 272 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 273 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 274 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 275 }; 276 277 enum { 278 MLX4_PERM_LOCAL_READ = 1 << 10, 279 MLX4_PERM_LOCAL_WRITE = 1 << 11, 280 MLX4_PERM_REMOTE_READ = 1 << 12, 281 MLX4_PERM_REMOTE_WRITE = 1 << 13, 282 MLX4_PERM_ATOMIC = 1 << 14, 283 MLX4_PERM_BIND_MW = 1 << 15, 284 MLX4_PERM_MASK = 0xFC00 285 }; 286 287 enum { 288 MLX4_OPCODE_NOP = 0x00, 289 MLX4_OPCODE_SEND_INVAL = 0x01, 290 MLX4_OPCODE_RDMA_WRITE = 0x08, 291 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 292 MLX4_OPCODE_SEND = 0x0a, 293 MLX4_OPCODE_SEND_IMM = 0x0b, 294 MLX4_OPCODE_LSO = 0x0e, 295 MLX4_OPCODE_RDMA_READ = 0x10, 296 MLX4_OPCODE_ATOMIC_CS = 0x11, 297 MLX4_OPCODE_ATOMIC_FA = 0x12, 298 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 299 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 300 MLX4_OPCODE_BIND_MW = 0x18, 301 MLX4_OPCODE_FMR = 0x19, 302 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 303 MLX4_OPCODE_CONFIG_CMD = 0x1f, 304 305 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 306 MLX4_RECV_OPCODE_SEND = 0x01, 307 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 308 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 309 310 MLX4_CQE_OPCODE_ERROR = 0x1e, 311 MLX4_CQE_OPCODE_RESIZE = 0x16, 312 }; 313 314 enum { 315 MLX4_STAT_RATE_OFFSET = 5 316 }; 317 318 enum mlx4_protocol { 319 MLX4_PROT_IB_IPV6 = 0, 320 MLX4_PROT_ETH, 321 MLX4_PROT_IB_IPV4, 322 MLX4_PROT_FCOE 323 }; 324 325 enum { 326 MLX4_MTT_FLAG_PRESENT = 1 327 }; 328 329 enum mlx4_qp_region { 330 MLX4_QP_REGION_FW = 0, 331 MLX4_QP_REGION_ETH_ADDR, 332 MLX4_QP_REGION_FC_ADDR, 333 MLX4_QP_REGION_FC_EXCH, 334 MLX4_NUM_QP_REGION 335 }; 336 337 enum mlx4_port_type { 338 MLX4_PORT_TYPE_NONE = 0, 339 MLX4_PORT_TYPE_IB = 1, 340 MLX4_PORT_TYPE_ETH = 2, 341 MLX4_PORT_TYPE_AUTO = 3 342 }; 343 344 enum mlx4_special_vlan_idx { 345 MLX4_NO_VLAN_IDX = 0, 346 MLX4_VLAN_MISS_IDX, 347 MLX4_VLAN_REGULAR 348 }; 349 350 enum mlx4_steer_type { 351 MLX4_MC_STEER = 0, 352 MLX4_UC_STEER, 353 MLX4_NUM_STEERS 354 }; 355 356 enum { 357 MLX4_NUM_FEXCH = 64 * 1024, 358 }; 359 360 enum { 361 MLX4_MAX_FAST_REG_PAGES = 511, 362 }; 363 364 enum { 365 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 366 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 367 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 368 }; 369 370 /* Port mgmt change event handling */ 371 enum { 372 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 373 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 374 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 375 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 376 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 377 }; 378 379 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 380 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 381 382 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 383 { 384 return (major << 32) | (minor << 16) | subminor; 385 } 386 387 struct mlx4_phys_caps { 388 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 389 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 390 u32 num_phys_eqs; 391 u32 base_sqpn; 392 u32 base_proxy_sqpn; 393 u32 base_tunnel_sqpn; 394 }; 395 396 struct mlx4_caps { 397 u64 fw_ver; 398 u32 function; 399 int num_ports; 400 int vl_cap[MLX4_MAX_PORTS + 1]; 401 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 402 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 403 u64 def_mac[MLX4_MAX_PORTS + 1]; 404 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 405 int gid_table_len[MLX4_MAX_PORTS + 1]; 406 int pkey_table_len[MLX4_MAX_PORTS + 1]; 407 int trans_type[MLX4_MAX_PORTS + 1]; 408 int vendor_oui[MLX4_MAX_PORTS + 1]; 409 int wavelength[MLX4_MAX_PORTS + 1]; 410 u64 trans_code[MLX4_MAX_PORTS + 1]; 411 int local_ca_ack_delay; 412 int num_uars; 413 u32 uar_page_size; 414 int bf_reg_size; 415 int bf_regs_per_page; 416 int max_sq_sg; 417 int max_rq_sg; 418 int num_qps; 419 int max_wqes; 420 int max_sq_desc_sz; 421 int max_rq_desc_sz; 422 int max_qp_init_rdma; 423 int max_qp_dest_rdma; 424 u32 *qp0_qkey; 425 u32 *qp0_proxy; 426 u32 *qp1_proxy; 427 u32 *qp0_tunnel; 428 u32 *qp1_tunnel; 429 int num_srqs; 430 int max_srq_wqes; 431 int max_srq_sge; 432 int reserved_srqs; 433 int num_cqs; 434 int max_cqes; 435 int reserved_cqs; 436 int num_eqs; 437 int reserved_eqs; 438 int num_comp_vectors; 439 int comp_pool; 440 int num_mpts; 441 int max_fmr_maps; 442 int num_mtts; 443 int fmr_reserved_mtts; 444 int reserved_mtts; 445 int reserved_mrws; 446 int reserved_uars; 447 int num_mgms; 448 int num_amgms; 449 int reserved_mcgs; 450 int num_qp_per_mgm; 451 int steering_mode; 452 int fs_log_max_ucast_qp_range_size; 453 int num_pds; 454 int reserved_pds; 455 int max_xrcds; 456 int reserved_xrcds; 457 int mtt_entry_sz; 458 u32 max_msg_sz; 459 u32 page_size_cap; 460 u64 flags; 461 u64 flags2; 462 u32 bmme_flags; 463 u32 reserved_lkey; 464 u16 stat_rate_support; 465 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 466 int max_gso_sz; 467 int max_rss_tbl_sz; 468 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 469 int reserved_qps; 470 int reserved_qps_base[MLX4_NUM_QP_REGION]; 471 int log_num_macs; 472 int log_num_vlans; 473 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 474 u8 supported_type[MLX4_MAX_PORTS + 1]; 475 u8 suggested_type[MLX4_MAX_PORTS + 1]; 476 u8 default_sense[MLX4_MAX_PORTS + 1]; 477 u32 port_mask[MLX4_MAX_PORTS + 1]; 478 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 479 u32 max_counters; 480 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 481 u16 sqp_demux; 482 u32 eqe_size; 483 u32 cqe_size; 484 u8 eqe_factor; 485 u32 userspace_caps; /* userspace must be aware of these */ 486 u32 function_caps; /* VFs must be aware of these */ 487 u16 hca_core_clock; 488 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 489 int tunnel_offload_mode; 490 }; 491 492 struct mlx4_buf_list { 493 void *buf; 494 dma_addr_t map; 495 }; 496 497 struct mlx4_buf { 498 struct mlx4_buf_list direct; 499 struct mlx4_buf_list *page_list; 500 int nbufs; 501 int npages; 502 int page_shift; 503 }; 504 505 struct mlx4_mtt { 506 u32 offset; 507 int order; 508 int page_shift; 509 }; 510 511 enum { 512 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 513 }; 514 515 struct mlx4_db_pgdir { 516 struct list_head list; 517 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 518 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 519 unsigned long *bits[2]; 520 __be32 *db_page; 521 dma_addr_t db_dma; 522 }; 523 524 struct mlx4_ib_user_db_page; 525 526 struct mlx4_db { 527 __be32 *db; 528 union { 529 struct mlx4_db_pgdir *pgdir; 530 struct mlx4_ib_user_db_page *user_page; 531 } u; 532 dma_addr_t dma; 533 int index; 534 int order; 535 }; 536 537 struct mlx4_hwq_resources { 538 struct mlx4_db db; 539 struct mlx4_mtt mtt; 540 struct mlx4_buf buf; 541 }; 542 543 struct mlx4_mr { 544 struct mlx4_mtt mtt; 545 u64 iova; 546 u64 size; 547 u32 key; 548 u32 pd; 549 u32 access; 550 int enabled; 551 }; 552 553 enum mlx4_mw_type { 554 MLX4_MW_TYPE_1 = 1, 555 MLX4_MW_TYPE_2 = 2, 556 }; 557 558 struct mlx4_mw { 559 u32 key; 560 u32 pd; 561 enum mlx4_mw_type type; 562 int enabled; 563 }; 564 565 struct mlx4_fmr { 566 struct mlx4_mr mr; 567 struct mlx4_mpt_entry *mpt; 568 __be64 *mtts; 569 dma_addr_t dma_handle; 570 int max_pages; 571 int max_maps; 572 int maps; 573 u8 page_shift; 574 }; 575 576 struct mlx4_uar { 577 unsigned long pfn; 578 int index; 579 struct list_head bf_list; 580 unsigned free_bf_bmap; 581 void __iomem *map; 582 void __iomem *bf_map; 583 }; 584 585 struct mlx4_bf { 586 unsigned int offset; 587 int buf_size; 588 struct mlx4_uar *uar; 589 void __iomem *reg; 590 }; 591 592 struct mlx4_cq { 593 void (*comp) (struct mlx4_cq *); 594 void (*event) (struct mlx4_cq *, enum mlx4_event); 595 596 struct mlx4_uar *uar; 597 598 u32 cons_index; 599 600 u16 irq; 601 __be32 *set_ci_db; 602 __be32 *arm_db; 603 int arm_sn; 604 605 int cqn; 606 unsigned vector; 607 608 atomic_t refcount; 609 struct completion free; 610 }; 611 612 struct mlx4_qp { 613 void (*event) (struct mlx4_qp *, enum mlx4_event); 614 615 int qpn; 616 617 atomic_t refcount; 618 struct completion free; 619 }; 620 621 struct mlx4_srq { 622 void (*event) (struct mlx4_srq *, enum mlx4_event); 623 624 int srqn; 625 int max; 626 int max_gs; 627 int wqe_shift; 628 629 atomic_t refcount; 630 struct completion free; 631 }; 632 633 struct mlx4_av { 634 __be32 port_pd; 635 u8 reserved1; 636 u8 g_slid; 637 __be16 dlid; 638 u8 reserved2; 639 u8 gid_index; 640 u8 stat_rate; 641 u8 hop_limit; 642 __be32 sl_tclass_flowlabel; 643 u8 dgid[16]; 644 }; 645 646 struct mlx4_eth_av { 647 __be32 port_pd; 648 u8 reserved1; 649 u8 smac_idx; 650 u16 reserved2; 651 u8 reserved3; 652 u8 gid_index; 653 u8 stat_rate; 654 u8 hop_limit; 655 __be32 sl_tclass_flowlabel; 656 u8 dgid[16]; 657 u8 s_mac[6]; 658 u8 reserved4[2]; 659 __be16 vlan; 660 u8 mac[ETH_ALEN]; 661 }; 662 663 union mlx4_ext_av { 664 struct mlx4_av ib; 665 struct mlx4_eth_av eth; 666 }; 667 668 struct mlx4_counter { 669 u8 reserved1[3]; 670 u8 counter_mode; 671 __be32 num_ifc; 672 u32 reserved2[2]; 673 __be64 rx_frames; 674 __be64 rx_bytes; 675 __be64 tx_frames; 676 __be64 tx_bytes; 677 }; 678 679 struct mlx4_quotas { 680 int qp; 681 int cq; 682 int srq; 683 int mpt; 684 int mtt; 685 int counter; 686 int xrcd; 687 }; 688 689 struct mlx4_vf_dev { 690 u8 min_port; 691 u8 n_ports; 692 }; 693 694 struct mlx4_dev { 695 struct pci_dev *pdev; 696 unsigned long flags; 697 unsigned long num_slaves; 698 struct mlx4_caps caps; 699 struct mlx4_phys_caps phys_caps; 700 struct mlx4_quotas quotas; 701 struct radix_tree_root qp_table_tree; 702 u8 rev_id; 703 char board_id[MLX4_BOARD_ID_LEN]; 704 int num_vfs; 705 int numa_node; 706 int oper_log_mgm_entry_size; 707 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 708 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 709 struct mlx4_vf_dev *dev_vfs; 710 int nvfs[MLX4_MAX_PORTS + 1]; 711 }; 712 713 struct mlx4_eqe { 714 u8 reserved1; 715 u8 type; 716 u8 reserved2; 717 u8 subtype; 718 union { 719 u32 raw[6]; 720 struct { 721 __be32 cqn; 722 } __packed comp; 723 struct { 724 u16 reserved1; 725 __be16 token; 726 u32 reserved2; 727 u8 reserved3[3]; 728 u8 status; 729 __be64 out_param; 730 } __packed cmd; 731 struct { 732 __be32 qpn; 733 } __packed qp; 734 struct { 735 __be32 srqn; 736 } __packed srq; 737 struct { 738 __be32 cqn; 739 u32 reserved1; 740 u8 reserved2[3]; 741 u8 syndrome; 742 } __packed cq_err; 743 struct { 744 u32 reserved1[2]; 745 __be32 port; 746 } __packed port_change; 747 struct { 748 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 749 u32 reserved; 750 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 751 } __packed comm_channel_arm; 752 struct { 753 u8 port; 754 u8 reserved[3]; 755 __be64 mac; 756 } __packed mac_update; 757 struct { 758 __be32 slave_id; 759 } __packed flr_event; 760 struct { 761 __be16 current_temperature; 762 __be16 warning_threshold; 763 } __packed warming; 764 struct { 765 u8 reserved[3]; 766 u8 port; 767 union { 768 struct { 769 __be16 mstr_sm_lid; 770 __be16 port_lid; 771 __be32 changed_attr; 772 u8 reserved[3]; 773 u8 mstr_sm_sl; 774 __be64 gid_prefix; 775 } __packed port_info; 776 struct { 777 __be32 block_ptr; 778 __be32 tbl_entries_mask; 779 } __packed tbl_change_info; 780 } params; 781 } __packed port_mgmt_change; 782 } event; 783 u8 slave_id; 784 u8 reserved3[2]; 785 u8 owner; 786 } __packed; 787 788 struct mlx4_init_port_param { 789 int set_guid0; 790 int set_node_guid; 791 int set_si_guid; 792 u16 mtu; 793 int port_width_cap; 794 u16 vl_cap; 795 u16 max_gid; 796 u16 max_pkey; 797 u64 guid0; 798 u64 node_guid; 799 u64 si_guid; 800 }; 801 802 #define mlx4_foreach_port(port, dev, type) \ 803 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 804 if ((type) == (dev)->caps.port_mask[(port)]) 805 806 #define mlx4_foreach_non_ib_transport_port(port, dev) \ 807 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 808 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) 809 810 #define mlx4_foreach_ib_transport_port(port, dev) \ 811 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 812 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 813 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 814 815 #define MLX4_INVALID_SLAVE_ID 0xFF 816 817 void handle_port_mgmt_change_event(struct work_struct *work); 818 819 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 820 { 821 return dev->caps.function; 822 } 823 824 static inline int mlx4_is_master(struct mlx4_dev *dev) 825 { 826 return dev->flags & MLX4_FLAG_MASTER; 827 } 828 829 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 830 { 831 return dev->phys_caps.base_sqpn + 8 + 832 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 833 } 834 835 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 836 { 837 return (qpn < dev->phys_caps.base_sqpn + 8 + 838 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); 839 } 840 841 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 842 { 843 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 844 845 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 846 return 1; 847 848 return 0; 849 } 850 851 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 852 { 853 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 854 } 855 856 static inline int mlx4_is_slave(struct mlx4_dev *dev) 857 { 858 return dev->flags & MLX4_FLAG_SLAVE; 859 } 860 861 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 862 struct mlx4_buf *buf, gfp_t gfp); 863 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 864 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 865 { 866 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 867 return buf->direct.buf + offset; 868 else 869 return buf->page_list[offset >> PAGE_SHIFT].buf + 870 (offset & (PAGE_SIZE - 1)); 871 } 872 873 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 874 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 875 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 876 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 877 878 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 879 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 880 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 881 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 882 883 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 884 struct mlx4_mtt *mtt); 885 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 886 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 887 888 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 889 int npages, int page_shift, struct mlx4_mr *mr); 890 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 891 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 892 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 893 struct mlx4_mw *mw); 894 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 895 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 896 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 897 int start_index, int npages, u64 *page_list); 898 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 899 struct mlx4_buf *buf, gfp_t gfp); 900 901 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, 902 gfp_t gfp); 903 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 904 905 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 906 int size, int max_direct); 907 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 908 int size); 909 910 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 911 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 912 unsigned vector, int collapsed, int timestamp_en); 913 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 914 915 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); 916 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 917 918 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, 919 gfp_t gfp); 920 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 921 922 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 923 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 924 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 925 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 926 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 927 928 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 929 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 930 931 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 932 int block_mcast_loopback, enum mlx4_protocol prot); 933 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 934 enum mlx4_protocol prot); 935 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 936 u8 port, int block_mcast_loopback, 937 enum mlx4_protocol protocol, u64 *reg_id); 938 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 939 enum mlx4_protocol protocol, u64 reg_id); 940 941 enum { 942 MLX4_DOMAIN_UVERBS = 0x1000, 943 MLX4_DOMAIN_ETHTOOL = 0x2000, 944 MLX4_DOMAIN_RFS = 0x3000, 945 MLX4_DOMAIN_NIC = 0x5000, 946 }; 947 948 enum mlx4_net_trans_rule_id { 949 MLX4_NET_TRANS_RULE_ID_ETH = 0, 950 MLX4_NET_TRANS_RULE_ID_IB, 951 MLX4_NET_TRANS_RULE_ID_IPV6, 952 MLX4_NET_TRANS_RULE_ID_IPV4, 953 MLX4_NET_TRANS_RULE_ID_TCP, 954 MLX4_NET_TRANS_RULE_ID_UDP, 955 MLX4_NET_TRANS_RULE_ID_VXLAN, 956 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 957 }; 958 959 extern const u16 __sw_id_hw[]; 960 961 static inline int map_hw_to_sw_id(u16 header_id) 962 { 963 964 int i; 965 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 966 if (header_id == __sw_id_hw[i]) 967 return i; 968 } 969 return -EINVAL; 970 } 971 972 enum mlx4_net_trans_promisc_mode { 973 MLX4_FS_REGULAR = 1, 974 MLX4_FS_ALL_DEFAULT, 975 MLX4_FS_MC_DEFAULT, 976 MLX4_FS_UC_SNIFFER, 977 MLX4_FS_MC_SNIFFER, 978 MLX4_FS_MODE_NUM, /* should be last */ 979 }; 980 981 struct mlx4_spec_eth { 982 u8 dst_mac[ETH_ALEN]; 983 u8 dst_mac_msk[ETH_ALEN]; 984 u8 src_mac[ETH_ALEN]; 985 u8 src_mac_msk[ETH_ALEN]; 986 u8 ether_type_enable; 987 __be16 ether_type; 988 __be16 vlan_id_msk; 989 __be16 vlan_id; 990 }; 991 992 struct mlx4_spec_tcp_udp { 993 __be16 dst_port; 994 __be16 dst_port_msk; 995 __be16 src_port; 996 __be16 src_port_msk; 997 }; 998 999 struct mlx4_spec_ipv4 { 1000 __be32 dst_ip; 1001 __be32 dst_ip_msk; 1002 __be32 src_ip; 1003 __be32 src_ip_msk; 1004 }; 1005 1006 struct mlx4_spec_ib { 1007 __be32 l3_qpn; 1008 __be32 qpn_msk; 1009 u8 dst_gid[16]; 1010 u8 dst_gid_msk[16]; 1011 }; 1012 1013 struct mlx4_spec_vxlan { 1014 __be32 vni; 1015 __be32 vni_mask; 1016 1017 }; 1018 1019 struct mlx4_spec_list { 1020 struct list_head list; 1021 enum mlx4_net_trans_rule_id id; 1022 union { 1023 struct mlx4_spec_eth eth; 1024 struct mlx4_spec_ib ib; 1025 struct mlx4_spec_ipv4 ipv4; 1026 struct mlx4_spec_tcp_udp tcp_udp; 1027 struct mlx4_spec_vxlan vxlan; 1028 }; 1029 }; 1030 1031 enum mlx4_net_trans_hw_rule_queue { 1032 MLX4_NET_TRANS_Q_FIFO, 1033 MLX4_NET_TRANS_Q_LIFO, 1034 }; 1035 1036 struct mlx4_net_trans_rule { 1037 struct list_head list; 1038 enum mlx4_net_trans_hw_rule_queue queue_mode; 1039 bool exclusive; 1040 bool allow_loopback; 1041 enum mlx4_net_trans_promisc_mode promisc_mode; 1042 u8 port; 1043 u16 priority; 1044 u32 qpn; 1045 }; 1046 1047 struct mlx4_net_trans_rule_hw_ctrl { 1048 __be16 prio; 1049 u8 type; 1050 u8 flags; 1051 u8 rsvd1; 1052 u8 funcid; 1053 u8 vep; 1054 u8 port; 1055 __be32 qpn; 1056 __be32 rsvd2; 1057 }; 1058 1059 struct mlx4_net_trans_rule_hw_ib { 1060 u8 size; 1061 u8 rsvd1; 1062 __be16 id; 1063 u32 rsvd2; 1064 __be32 l3_qpn; 1065 __be32 qpn_mask; 1066 u8 dst_gid[16]; 1067 u8 dst_gid_msk[16]; 1068 } __packed; 1069 1070 struct mlx4_net_trans_rule_hw_eth { 1071 u8 size; 1072 u8 rsvd; 1073 __be16 id; 1074 u8 rsvd1[6]; 1075 u8 dst_mac[6]; 1076 u16 rsvd2; 1077 u8 dst_mac_msk[6]; 1078 u16 rsvd3; 1079 u8 src_mac[6]; 1080 u16 rsvd4; 1081 u8 src_mac_msk[6]; 1082 u8 rsvd5; 1083 u8 ether_type_enable; 1084 __be16 ether_type; 1085 __be16 vlan_tag_msk; 1086 __be16 vlan_tag; 1087 } __packed; 1088 1089 struct mlx4_net_trans_rule_hw_tcp_udp { 1090 u8 size; 1091 u8 rsvd; 1092 __be16 id; 1093 __be16 rsvd1[3]; 1094 __be16 dst_port; 1095 __be16 rsvd2; 1096 __be16 dst_port_msk; 1097 __be16 rsvd3; 1098 __be16 src_port; 1099 __be16 rsvd4; 1100 __be16 src_port_msk; 1101 } __packed; 1102 1103 struct mlx4_net_trans_rule_hw_ipv4 { 1104 u8 size; 1105 u8 rsvd; 1106 __be16 id; 1107 __be32 rsvd1; 1108 __be32 dst_ip; 1109 __be32 dst_ip_msk; 1110 __be32 src_ip; 1111 __be32 src_ip_msk; 1112 } __packed; 1113 1114 struct mlx4_net_trans_rule_hw_vxlan { 1115 u8 size; 1116 u8 rsvd; 1117 __be16 id; 1118 __be32 rsvd1; 1119 __be32 vni; 1120 __be32 vni_mask; 1121 } __packed; 1122 1123 struct _rule_hw { 1124 union { 1125 struct { 1126 u8 size; 1127 u8 rsvd; 1128 __be16 id; 1129 }; 1130 struct mlx4_net_trans_rule_hw_eth eth; 1131 struct mlx4_net_trans_rule_hw_ib ib; 1132 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1133 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1134 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1135 }; 1136 }; 1137 1138 enum { 1139 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1140 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1141 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1142 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1143 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1144 }; 1145 1146 1147 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1148 enum mlx4_net_trans_promisc_mode mode); 1149 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1150 enum mlx4_net_trans_promisc_mode mode); 1151 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1152 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1153 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1154 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1155 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1156 1157 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1158 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1159 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1160 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1161 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); 1162 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1163 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1164 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1165 u8 promisc); 1166 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); 1167 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, 1168 u8 *pg, u16 *ratelimit); 1169 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1170 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1171 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1172 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1173 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1174 1175 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1176 int npages, u64 iova, u32 *lkey, u32 *rkey); 1177 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1178 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1179 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1180 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1181 u32 *lkey, u32 *rkey); 1182 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1183 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1184 int mlx4_test_interrupts(struct mlx4_dev *dev); 1185 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, 1186 int *vector); 1187 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1188 1189 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); 1190 1191 int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1192 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1193 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1194 1195 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1196 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1197 1198 int mlx4_flow_attach(struct mlx4_dev *dev, 1199 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1200 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1201 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1202 enum mlx4_net_trans_promisc_mode flow_type); 1203 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1204 enum mlx4_net_trans_rule_id id); 1205 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1206 1207 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, 1208 int port, int qpn, u16 prio, u64 *reg_id); 1209 1210 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1211 int i, int val); 1212 1213 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1214 1215 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1216 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1217 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1218 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1219 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1220 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1221 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1222 1223 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1224 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1225 1226 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1227 int *slave_id); 1228 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1229 u8 *gid); 1230 1231 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1232 u32 max_range_qpn); 1233 1234 cycle_t mlx4_read_clock(struct mlx4_dev *dev); 1235 1236 struct mlx4_active_ports { 1237 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1238 }; 1239 /* Returns a bitmap of the physical ports which are assigned to slave */ 1240 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1241 1242 /* Returns the physical port that represents the virtual port of the slave, */ 1243 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1244 /* mapping is returned. */ 1245 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1246 1247 struct mlx4_slaves_pport { 1248 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1249 }; 1250 /* Returns a bitmap of all slaves that are assigned to port. */ 1251 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1252 int port); 1253 1254 /* Returns a bitmap of all slaves that are assigned exactly to all the */ 1255 /* the ports that are set in crit_ports. */ 1256 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1257 struct mlx4_dev *dev, 1258 const struct mlx4_active_ports *crit_ports); 1259 1260 /* Returns the slave's virtual port that represents the physical port. */ 1261 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1262 1263 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1264 1265 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1266 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1267 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1268 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1269 int enable); 1270 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1271 struct mlx4_mpt_entry ***mpt_entry); 1272 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1273 struct mlx4_mpt_entry **mpt_entry); 1274 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, 1275 u32 pdn); 1276 int mlx4_mr_hw_change_access(struct mlx4_dev *dev, 1277 struct mlx4_mpt_entry *mpt_entry, 1278 u32 access); 1279 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, 1280 struct mlx4_mpt_entry **mpt_entry); 1281 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); 1282 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, 1283 u64 iova, u64 size, int npages, 1284 int page_shift, struct mlx4_mpt_entry *mpt_entry); 1285 1286 /* Returns true if running in low memory profile (kdump kernel) */ 1287 static inline bool mlx4_low_memory_profile(void) 1288 { 1289 return is_kdump_kernel(); 1290 } 1291 1292 #endif /* MLX4_DEVICE_H */ 1293