1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 20d40c612SSylwester Nawrocki #ifndef _DT_BINDINGS_SAMSUNG_I2S_H 30d40c612SSylwester Nawrocki #define _DT_BINDINGS_SAMSUNG_I2S_H 40d40c612SSylwester Nawrocki 5*6cc23ed2SMaciej Falkowski #define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */ 6*6cc23ed2SMaciej Falkowski 7*6cc23ed2SMaciej Falkowski #define CLK_I2S_RCLK_SRC 1 /* the RCLKSRC mux clock (corresponding to 8*6cc23ed2SMaciej Falkowski * RCLKSRC bit in IISMOD register) 9*6cc23ed2SMaciej Falkowski */ 10*6cc23ed2SMaciej Falkowski 11*6cc23ed2SMaciej Falkowski #define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock 12*6cc23ed2SMaciej Falkowski * (corresponding to the IISPSR register) 13*6cc23ed2SMaciej Falkowski */ 140d40c612SSylwester Nawrocki 150d40c612SSylwester Nawrocki #endif /* _DT_BINDINGS_SAMSUNG_I2S_H */ 16