1*55bfc376SQin Jian /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*55bfc376SQin Jian /* 3*55bfc376SQin Jian * Copyright (C) Sunplus Technology Co., Ltd. 4*55bfc376SQin Jian * All rights reserved. 5*55bfc376SQin Jian */ 6*55bfc376SQin Jian #ifndef _DT_BINDINGS_RST_SUNPLUS_SP7021_H 7*55bfc376SQin Jian #define _DT_BINDINGS_RST_SUNPLUS_SP7021_H 8*55bfc376SQin Jian 9*55bfc376SQin Jian #define RST_SYSTEM 0 10*55bfc376SQin Jian #define RST_RTC 1 11*55bfc376SQin Jian #define RST_IOCTL 2 12*55bfc376SQin Jian #define RST_IOP 3 13*55bfc376SQin Jian #define RST_OTPRX 4 14*55bfc376SQin Jian #define RST_NOC 5 15*55bfc376SQin Jian #define RST_BR 6 16*55bfc376SQin Jian #define RST_RBUS_L00 7 17*55bfc376SQin Jian #define RST_SPIFL 8 18*55bfc376SQin Jian #define RST_SDCTRL0 9 19*55bfc376SQin Jian #define RST_PERI0 10 20*55bfc376SQin Jian #define RST_A926 11 21*55bfc376SQin Jian #define RST_UMCTL2 12 22*55bfc376SQin Jian #define RST_PERI1 13 23*55bfc376SQin Jian #define RST_DDR_PHY0 14 24*55bfc376SQin Jian #define RST_ACHIP 15 25*55bfc376SQin Jian #define RST_STC0 16 26*55bfc376SQin Jian #define RST_STC_AV0 17 27*55bfc376SQin Jian #define RST_STC_AV1 18 28*55bfc376SQin Jian #define RST_STC_AV2 19 29*55bfc376SQin Jian #define RST_UA0 20 30*55bfc376SQin Jian #define RST_UA1 21 31*55bfc376SQin Jian #define RST_UA2 22 32*55bfc376SQin Jian #define RST_UA3 23 33*55bfc376SQin Jian #define RST_UA4 24 34*55bfc376SQin Jian #define RST_HWUA 25 35*55bfc376SQin Jian #define RST_DDC0 26 36*55bfc376SQin Jian #define RST_UADMA 27 37*55bfc376SQin Jian #define RST_CBDMA0 28 38*55bfc376SQin Jian #define RST_CBDMA1 29 39*55bfc376SQin Jian #define RST_SPI_COMBO_0 30 40*55bfc376SQin Jian #define RST_SPI_COMBO_1 31 41*55bfc376SQin Jian #define RST_SPI_COMBO_2 32 42*55bfc376SQin Jian #define RST_SPI_COMBO_3 33 43*55bfc376SQin Jian #define RST_AUD 34 44*55bfc376SQin Jian #define RST_USBC0 35 45*55bfc376SQin Jian #define RST_USBC1 36 46*55bfc376SQin Jian #define RST_UPHY0 37 47*55bfc376SQin Jian #define RST_UPHY1 38 48*55bfc376SQin Jian #define RST_I2CM0 39 49*55bfc376SQin Jian #define RST_I2CM1 40 50*55bfc376SQin Jian #define RST_I2CM2 41 51*55bfc376SQin Jian #define RST_I2CM3 42 52*55bfc376SQin Jian #define RST_PMC 43 53*55bfc376SQin Jian #define RST_CARD_CTL0 44 54*55bfc376SQin Jian #define RST_CARD_CTL1 45 55*55bfc376SQin Jian #define RST_CARD_CTL4 46 56*55bfc376SQin Jian #define RST_BCH 47 57*55bfc376SQin Jian #define RST_DDFCH 48 58*55bfc376SQin Jian #define RST_CSIIW0 49 59*55bfc376SQin Jian #define RST_CSIIW1 50 60*55bfc376SQin Jian #define RST_MIPICSI0 51 61*55bfc376SQin Jian #define RST_MIPICSI1 52 62*55bfc376SQin Jian #define RST_HDMI_TX 53 63*55bfc376SQin Jian #define RST_VPOST 54 64*55bfc376SQin Jian #define RST_TGEN 55 65*55bfc376SQin Jian #define RST_DMIX 56 66*55bfc376SQin Jian #define RST_TCON 57 67*55bfc376SQin Jian #define RST_INTERRUPT 58 68*55bfc376SQin Jian #define RST_RGST 59 69*55bfc376SQin Jian #define RST_GPIO 60 70*55bfc376SQin Jian #define RST_RBUS_TOP 61 71*55bfc376SQin Jian #define RST_MAILBOX 62 72*55bfc376SQin Jian #define RST_SPIND 63 73*55bfc376SQin Jian #define RST_I2C2CBUS 64 74*55bfc376SQin Jian #define RST_SEC 65 75*55bfc376SQin Jian #define RST_DVE 66 76*55bfc376SQin Jian #define RST_GPOST0 67 77*55bfc376SQin Jian #define RST_OSD0 68 78*55bfc376SQin Jian #define RST_DISP_PWM 69 79*55bfc376SQin Jian #define RST_UADBG 70 80*55bfc376SQin Jian #define RST_DUMMY_MASTER 71 81*55bfc376SQin Jian #define RST_FIO_CTL 72 82*55bfc376SQin Jian #define RST_FPGA 73 83*55bfc376SQin Jian #define RST_L2SW 74 84*55bfc376SQin Jian #define RST_ICM 75 85*55bfc376SQin Jian #define RST_AXI_GLOBAL 76 86*55bfc376SQin Jian 87*55bfc376SQin Jian #endif 88