xref: /openbmc/linux/include/dt-bindings/reset/qcom,ipq9574-gcc.h (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)
1*b065b23dSDevi Priya /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*b065b23dSDevi Priya /*
3*b065b23dSDevi Priya  * Copyright (c) 2018-2023, The Linux Foundation. All rights reserved.
4*b065b23dSDevi Priya  */
5*b065b23dSDevi Priya 
6*b065b23dSDevi Priya #ifndef _DT_BINDINGS_RESET_IPQ_GCC_9574_H
7*b065b23dSDevi Priya #define _DT_BINDINGS_RESET_IPQ_GCC_9574_H
8*b065b23dSDevi Priya 
9*b065b23dSDevi Priya #define GCC_ADSS_BCR						0
10*b065b23dSDevi Priya #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR			1
11*b065b23dSDevi Priya #define GCC_BLSP1_BCR						2
12*b065b23dSDevi Priya #define GCC_BLSP1_QUP1_BCR					3
13*b065b23dSDevi Priya #define GCC_BLSP1_QUP2_BCR					4
14*b065b23dSDevi Priya #define GCC_BLSP1_QUP3_BCR					5
15*b065b23dSDevi Priya #define GCC_BLSP1_QUP4_BCR					6
16*b065b23dSDevi Priya #define GCC_BLSP1_QUP5_BCR					7
17*b065b23dSDevi Priya #define GCC_BLSP1_QUP6_BCR					8
18*b065b23dSDevi Priya #define GCC_BLSP1_UART1_BCR					9
19*b065b23dSDevi Priya #define GCC_BLSP1_UART2_BCR					10
20*b065b23dSDevi Priya #define GCC_BLSP1_UART3_BCR					11
21*b065b23dSDevi Priya #define GCC_BLSP1_UART4_BCR					12
22*b065b23dSDevi Priya #define GCC_BLSP1_UART5_BCR					13
23*b065b23dSDevi Priya #define GCC_BLSP1_UART6_BCR					14
24*b065b23dSDevi Priya #define GCC_BOOT_ROM_BCR					15
25*b065b23dSDevi Priya #define GCC_MDIO_BCR						16
26*b065b23dSDevi Priya #define GCC_NSS_BCR						17
27*b065b23dSDevi Priya #define GCC_NSS_TBU_BCR						18
28*b065b23dSDevi Priya #define GCC_PCIE0_BCR						19
29*b065b23dSDevi Priya #define GCC_PCIE0_LINK_DOWN_BCR					20
30*b065b23dSDevi Priya #define GCC_PCIE0_PHY_BCR					21
31*b065b23dSDevi Priya #define GCC_PCIE0PHY_PHY_BCR					22
32*b065b23dSDevi Priya #define GCC_PCIE1_BCR						23
33*b065b23dSDevi Priya #define GCC_PCIE1_LINK_DOWN_BCR					24
34*b065b23dSDevi Priya #define GCC_PCIE1_PHY_BCR					25
35*b065b23dSDevi Priya #define GCC_PCIE1PHY_PHY_BCR					26
36*b065b23dSDevi Priya #define GCC_PCIE2_BCR						27
37*b065b23dSDevi Priya #define GCC_PCIE2_LINK_DOWN_BCR					28
38*b065b23dSDevi Priya #define GCC_PCIE2_PHY_BCR					29
39*b065b23dSDevi Priya #define GCC_PCIE2PHY_PHY_BCR					30
40*b065b23dSDevi Priya #define GCC_PCIE3_BCR						31
41*b065b23dSDevi Priya #define GCC_PCIE3_LINK_DOWN_BCR					32
42*b065b23dSDevi Priya #define GCC_PCIE3_PHY_BCR					33
43*b065b23dSDevi Priya #define GCC_PCIE3PHY_PHY_BCR					34
44*b065b23dSDevi Priya #define GCC_PRNG_BCR						35
45*b065b23dSDevi Priya #define GCC_QUSB2_0_PHY_BCR					36
46*b065b23dSDevi Priya #define GCC_SDCC_BCR						37
47*b065b23dSDevi Priya #define GCC_TLMM_BCR						38
48*b065b23dSDevi Priya #define GCC_UNIPHY0_BCR						39
49*b065b23dSDevi Priya #define GCC_UNIPHY1_BCR						40
50*b065b23dSDevi Priya #define GCC_UNIPHY2_BCR						41
51*b065b23dSDevi Priya #define GCC_USB0_PHY_BCR					42
52*b065b23dSDevi Priya #define GCC_USB3PHY_0_PHY_BCR					43
53*b065b23dSDevi Priya #define GCC_USB_BCR						44
54*b065b23dSDevi Priya #define GCC_ANOC0_TBU_BCR					45
55*b065b23dSDevi Priya #define GCC_ANOC1_TBU_BCR					46
56*b065b23dSDevi Priya #define GCC_ANOC_BCR						47
57*b065b23dSDevi Priya #define GCC_APSS_TCU_BCR					48
58*b065b23dSDevi Priya #define GCC_CMN_BLK_BCR						49
59*b065b23dSDevi Priya #define GCC_CMN_BLK_AHB_ARES					50
60*b065b23dSDevi Priya #define GCC_CMN_BLK_SYS_ARES					51
61*b065b23dSDevi Priya #define GCC_CMN_BLK_APU_ARES					52
62*b065b23dSDevi Priya #define GCC_DCC_BCR						53
63*b065b23dSDevi Priya #define GCC_DDRSS_BCR						54
64*b065b23dSDevi Priya #define GCC_IMEM_BCR						55
65*b065b23dSDevi Priya #define GCC_LPASS_BCR						56
66*b065b23dSDevi Priya #define GCC_MPM_BCR						57
67*b065b23dSDevi Priya #define GCC_MSG_RAM_BCR						58
68*b065b23dSDevi Priya #define GCC_NSSNOC_MEMNOC_1_ARES				59
69*b065b23dSDevi Priya #define GCC_NSSNOC_PCNOC_1_ARES					60
70*b065b23dSDevi Priya #define GCC_NSSNOC_SNOC_1_ARES					61
71*b065b23dSDevi Priya #define GCC_NSSNOC_XO_DCD_ARES					62
72*b065b23dSDevi Priya #define GCC_NSSNOC_TS_ARES					63
73*b065b23dSDevi Priya #define GCC_NSSCC_ARES						64
74*b065b23dSDevi Priya #define GCC_NSSNOC_NSSCC_ARES					65
75*b065b23dSDevi Priya #define GCC_NSSNOC_ATB_ARES					66
76*b065b23dSDevi Priya #define GCC_NSSNOC_MEMNOC_ARES					67
77*b065b23dSDevi Priya #define GCC_NSSNOC_QOSGEN_REF_ARES				68
78*b065b23dSDevi Priya #define GCC_NSSNOC_SNOC_ARES					69
79*b065b23dSDevi Priya #define GCC_NSSNOC_TIMEOUT_REF_ARES				70
80*b065b23dSDevi Priya #define GCC_NSS_CFG_ARES					71
81*b065b23dSDevi Priya #define GCC_UBI0_DBG_ARES					72
82*b065b23dSDevi Priya #define GCC_PCIE0_AHB_ARES					73
83*b065b23dSDevi Priya #define GCC_PCIE0_AUX_ARES					74
84*b065b23dSDevi Priya #define GCC_PCIE0_AXI_M_ARES					75
85*b065b23dSDevi Priya #define GCC_PCIE0_AXI_M_STICKY_ARES				76
86*b065b23dSDevi Priya #define GCC_PCIE0_AXI_S_ARES					77
87*b065b23dSDevi Priya #define GCC_PCIE0_AXI_S_STICKY_ARES				78
88*b065b23dSDevi Priya #define GCC_PCIE0_CORE_STICKY_ARES				79
89*b065b23dSDevi Priya #define GCC_PCIE0_PIPE_ARES					80
90*b065b23dSDevi Priya #define GCC_PCIE1_AHB_ARES					81
91*b065b23dSDevi Priya #define GCC_PCIE1_AUX_ARES					82
92*b065b23dSDevi Priya #define GCC_PCIE1_AXI_M_ARES					83
93*b065b23dSDevi Priya #define GCC_PCIE1_AXI_M_STICKY_ARES				84
94*b065b23dSDevi Priya #define GCC_PCIE1_AXI_S_ARES					85
95*b065b23dSDevi Priya #define GCC_PCIE1_AXI_S_STICKY_ARES				86
96*b065b23dSDevi Priya #define GCC_PCIE1_CORE_STICKY_ARES				87
97*b065b23dSDevi Priya #define GCC_PCIE1_PIPE_ARES					88
98*b065b23dSDevi Priya #define GCC_PCIE2_AHB_ARES					89
99*b065b23dSDevi Priya #define GCC_PCIE2_AUX_ARES					90
100*b065b23dSDevi Priya #define GCC_PCIE2_AXI_M_ARES					91
101*b065b23dSDevi Priya #define GCC_PCIE2_AXI_M_STICKY_ARES				92
102*b065b23dSDevi Priya #define GCC_PCIE2_AXI_S_ARES					93
103*b065b23dSDevi Priya #define GCC_PCIE2_AXI_S_STICKY_ARES				94
104*b065b23dSDevi Priya #define GCC_PCIE2_CORE_STICKY_ARES				95
105*b065b23dSDevi Priya #define GCC_PCIE2_PIPE_ARES					96
106*b065b23dSDevi Priya #define GCC_PCIE3_AHB_ARES					97
107*b065b23dSDevi Priya #define GCC_PCIE3_AUX_ARES					98
108*b065b23dSDevi Priya #define GCC_PCIE3_AXI_M_ARES					99
109*b065b23dSDevi Priya #define GCC_PCIE3_AXI_M_STICKY_ARES				100
110*b065b23dSDevi Priya #define GCC_PCIE3_AXI_S_ARES					101
111*b065b23dSDevi Priya #define GCC_PCIE3_AXI_S_STICKY_ARES				102
112*b065b23dSDevi Priya #define GCC_PCIE3_CORE_STICKY_ARES				103
113*b065b23dSDevi Priya #define GCC_PCIE3_PIPE_ARES					104
114*b065b23dSDevi Priya #define GCC_PCNOC_BCR						105
115*b065b23dSDevi Priya #define GCC_PCNOC_BUS_TIMEOUT0_BCR				106
116*b065b23dSDevi Priya #define GCC_PCNOC_BUS_TIMEOUT1_BCR				107
117*b065b23dSDevi Priya #define GCC_PCNOC_BUS_TIMEOUT2_BCR				108
118*b065b23dSDevi Priya #define GCC_PCNOC_BUS_TIMEOUT3_BCR				109
119*b065b23dSDevi Priya #define GCC_PCNOC_BUS_TIMEOUT4_BCR				110
120*b065b23dSDevi Priya #define GCC_PCNOC_BUS_TIMEOUT5_BCR				111
121*b065b23dSDevi Priya #define GCC_PCNOC_BUS_TIMEOUT6_BCR				112
122*b065b23dSDevi Priya #define GCC_PCNOC_BUS_TIMEOUT7_BCR				113
123*b065b23dSDevi Priya #define GCC_PCNOC_BUS_TIMEOUT8_BCR				114
124*b065b23dSDevi Priya #define GCC_PCNOC_BUS_TIMEOUT9_BCR				115
125*b065b23dSDevi Priya #define GCC_PCNOC_TBU_BCR					116
126*b065b23dSDevi Priya #define GCC_Q6SS_DBG_ARES					117
127*b065b23dSDevi Priya #define GCC_Q6_AHB_ARES						118
128*b065b23dSDevi Priya #define GCC_Q6_AHB_S_ARES					119
129*b065b23dSDevi Priya #define GCC_Q6_AXIM2_ARES					120
130*b065b23dSDevi Priya #define GCC_Q6_AXIM_ARES					121
131*b065b23dSDevi Priya #define GCC_QDSS_BCR						122
132*b065b23dSDevi Priya #define GCC_QPIC_BCR						123
133*b065b23dSDevi Priya #define GCC_QPIC_AHB_ARES					124
134*b065b23dSDevi Priya #define GCC_QPIC_ARES						125
135*b065b23dSDevi Priya #define GCC_RBCPR_BCR						126
136*b065b23dSDevi Priya #define GCC_RBCPR_MX_BCR					127
137*b065b23dSDevi Priya #define GCC_SEC_CTRL_BCR					128
138*b065b23dSDevi Priya #define GCC_SMMU_CFG_BCR					129
139*b065b23dSDevi Priya #define GCC_SNOC_BCR						130
140*b065b23dSDevi Priya #define GCC_SPDM_BCR						131
141*b065b23dSDevi Priya #define GCC_TME_BCR						132
142*b065b23dSDevi Priya #define GCC_UNIPHY0_SYS_RESET					133
143*b065b23dSDevi Priya #define GCC_UNIPHY0_AHB_RESET					134
144*b065b23dSDevi Priya #define GCC_UNIPHY0_XPCS_RESET					135
145*b065b23dSDevi Priya #define GCC_UNIPHY1_SYS_RESET					136
146*b065b23dSDevi Priya #define GCC_UNIPHY1_AHB_RESET					137
147*b065b23dSDevi Priya #define GCC_UNIPHY1_XPCS_RESET					138
148*b065b23dSDevi Priya #define GCC_UNIPHY2_SYS_RESET					139
149*b065b23dSDevi Priya #define GCC_UNIPHY2_AHB_RESET					140
150*b065b23dSDevi Priya #define GCC_UNIPHY2_XPCS_RESET					141
151*b065b23dSDevi Priya #define GCC_USB_MISC_RESET					142
152*b065b23dSDevi Priya #define GCC_WCSSAON_RESET					143
153*b065b23dSDevi Priya #define GCC_WCSS_ACMT_ARES					144
154*b065b23dSDevi Priya #define GCC_WCSS_AHB_S_ARES					145
155*b065b23dSDevi Priya #define GCC_WCSS_AXI_M_ARES					146
156*b065b23dSDevi Priya #define GCC_WCSS_BCR						147
157*b065b23dSDevi Priya #define GCC_WCSS_DBG_ARES					148
158*b065b23dSDevi Priya #define GCC_WCSS_DBG_BDG_ARES					149
159*b065b23dSDevi Priya #define GCC_WCSS_ECAHB_ARES					150
160*b065b23dSDevi Priya #define GCC_WCSS_Q6_BCR						151
161*b065b23dSDevi Priya #define GCC_WCSS_Q6_TBU_BCR					152
162*b065b23dSDevi Priya #define GCC_TCSR_BCR						153
163*b065b23dSDevi Priya #define GCC_CRYPTO_BCR						154
164*b065b23dSDevi Priya 
165 #endif
166