xref: /openbmc/linux/include/dt-bindings/reset/qcom,gcc-ipq6018.h (revision 8dd06ef34b6e2f41b29fbf5fc1663780f2524285)
1*d15b1ff1SSricharan R /* SPDX-License-Identifier: GPL-2.0 */
2*d15b1ff1SSricharan R /*
3*d15b1ff1SSricharan R  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4*d15b1ff1SSricharan R  */
5*d15b1ff1SSricharan R 
6*d15b1ff1SSricharan R #ifndef _DT_BINDINGS_RESET_IPQ_GCC_6018_H
7*d15b1ff1SSricharan R #define _DT_BINDINGS_RESET_IPQ_GCC_6018_H
8*d15b1ff1SSricharan R 
9*d15b1ff1SSricharan R #define GCC_BLSP1_BCR				0
10*d15b1ff1SSricharan R #define GCC_BLSP1_QUP1_BCR			1
11*d15b1ff1SSricharan R #define GCC_BLSP1_UART1_BCR			2
12*d15b1ff1SSricharan R #define GCC_BLSP1_QUP2_BCR			3
13*d15b1ff1SSricharan R #define GCC_BLSP1_UART2_BCR			4
14*d15b1ff1SSricharan R #define GCC_BLSP1_QUP3_BCR			5
15*d15b1ff1SSricharan R #define GCC_BLSP1_UART3_BCR			6
16*d15b1ff1SSricharan R #define GCC_BLSP1_QUP4_BCR			7
17*d15b1ff1SSricharan R #define GCC_BLSP1_UART4_BCR			8
18*d15b1ff1SSricharan R #define GCC_BLSP1_QUP5_BCR			9
19*d15b1ff1SSricharan R #define GCC_BLSP1_UART5_BCR			10
20*d15b1ff1SSricharan R #define GCC_BLSP1_QUP6_BCR			11
21*d15b1ff1SSricharan R #define GCC_BLSP1_UART6_BCR			12
22*d15b1ff1SSricharan R #define GCC_IMEM_BCR				13
23*d15b1ff1SSricharan R #define GCC_SMMU_BCR				14
24*d15b1ff1SSricharan R #define GCC_APSS_TCU_BCR			15
25*d15b1ff1SSricharan R #define GCC_SMMU_XPU_BCR			16
26*d15b1ff1SSricharan R #define GCC_PCNOC_TBU_BCR			17
27*d15b1ff1SSricharan R #define GCC_SMMU_CFG_BCR			18
28*d15b1ff1SSricharan R #define GCC_PRNG_BCR				19
29*d15b1ff1SSricharan R #define GCC_BOOT_ROM_BCR			20
30*d15b1ff1SSricharan R #define GCC_CRYPTO_BCR				21
31*d15b1ff1SSricharan R #define GCC_WCSS_BCR				22
32*d15b1ff1SSricharan R #define GCC_WCSS_Q6_BCR				23
33*d15b1ff1SSricharan R #define GCC_NSS_BCR				24
34*d15b1ff1SSricharan R #define GCC_SEC_CTRL_BCR			25
35*d15b1ff1SSricharan R #define GCC_DDRSS_BCR				26
36*d15b1ff1SSricharan R #define GCC_SYSTEM_NOC_BCR			27
37*d15b1ff1SSricharan R #define GCC_PCNOC_BCR				28
38*d15b1ff1SSricharan R #define GCC_TCSR_BCR				29
39*d15b1ff1SSricharan R #define GCC_QDSS_BCR				30
40*d15b1ff1SSricharan R #define GCC_DCD_BCR				31
41*d15b1ff1SSricharan R #define GCC_MSG_RAM_BCR				32
42*d15b1ff1SSricharan R #define GCC_MPM_BCR				33
43*d15b1ff1SSricharan R #define GCC_SPDM_BCR				34
44*d15b1ff1SSricharan R #define GCC_RBCPR_BCR				35
45*d15b1ff1SSricharan R #define GCC_RBCPR_MX_BCR			36
46*d15b1ff1SSricharan R #define GCC_TLMM_BCR				37
47*d15b1ff1SSricharan R #define GCC_RBCPR_WCSS_BCR			38
48*d15b1ff1SSricharan R #define GCC_USB0_PHY_BCR			39
49*d15b1ff1SSricharan R #define GCC_USB3PHY_0_PHY_BCR			40
50*d15b1ff1SSricharan R #define GCC_USB0_BCR				41
51*d15b1ff1SSricharan R #define GCC_USB1_BCR				42
52*d15b1ff1SSricharan R #define GCC_QUSB2_0_PHY_BCR			43
53*d15b1ff1SSricharan R #define GCC_QUSB2_1_PHY_BCR			44
54*d15b1ff1SSricharan R #define GCC_SDCC1_BCR				45
55*d15b1ff1SSricharan R #define GCC_SNOC_BUS_TIMEOUT0_BCR		46
56*d15b1ff1SSricharan R #define GCC_SNOC_BUS_TIMEOUT1_BCR		47
57*d15b1ff1SSricharan R #define GCC_SNOC_BUS_TIMEOUT2_BCR		48
58*d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT0_BCR		49
59*d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT1_BCR		50
60*d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT2_BCR		51
61*d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT3_BCR		52
62*d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT4_BCR		53
63*d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT5_BCR		54
64*d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT6_BCR		55
65*d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT7_BCR		56
66*d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT8_BCR		57
67*d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT9_BCR		58
68*d15b1ff1SSricharan R #define GCC_UNIPHY0_BCR				59
69*d15b1ff1SSricharan R #define GCC_UNIPHY1_BCR				60
70*d15b1ff1SSricharan R #define GCC_CMN_12GPLL_BCR			61
71*d15b1ff1SSricharan R #define GCC_QPIC_BCR				62
72*d15b1ff1SSricharan R #define GCC_MDIO_BCR				63
73*d15b1ff1SSricharan R #define GCC_WCSS_CORE_TBU_BCR			64
74*d15b1ff1SSricharan R #define GCC_WCSS_Q6_TBU_BCR			65
75*d15b1ff1SSricharan R #define GCC_USB0_TBU_BCR			66
76*d15b1ff1SSricharan R #define GCC_PCIE0_TBU_BCR			67
77*d15b1ff1SSricharan R #define GCC_PCIE0_BCR				68
78*d15b1ff1SSricharan R #define GCC_PCIE0_PHY_BCR			69
79*d15b1ff1SSricharan R #define GCC_PCIE0PHY_PHY_BCR			70
80*d15b1ff1SSricharan R #define GCC_PCIE0_LINK_DOWN_BCR			71
81*d15b1ff1SSricharan R #define GCC_DCC_BCR				72
82*d15b1ff1SSricharan R #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR	73
83*d15b1ff1SSricharan R #define GCC_SMMU_CATS_BCR			74
84*d15b1ff1SSricharan R #define GCC_UBI0_AXI_ARES			75
85*d15b1ff1SSricharan R #define GCC_UBI0_AHB_ARES			76
86*d15b1ff1SSricharan R #define GCC_UBI0_NC_AXI_ARES			77
87*d15b1ff1SSricharan R #define GCC_UBI0_DBG_ARES			78
88*d15b1ff1SSricharan R #define GCC_UBI0_CORE_CLAMP_ENABLE		79
89*d15b1ff1SSricharan R #define GCC_UBI0_CLKRST_CLAMP_ENABLE		80
90*d15b1ff1SSricharan R #define GCC_UBI0_UTCM_ARES			81
91*d15b1ff1SSricharan R #define GCC_NSS_CFG_ARES			82
92*d15b1ff1SSricharan R #define GCC_NSS_NOC_ARES			83
93*d15b1ff1SSricharan R #define GCC_NSS_CRYPTO_ARES			84
94*d15b1ff1SSricharan R #define GCC_NSS_CSR_ARES			85
95*d15b1ff1SSricharan R #define GCC_NSS_CE_APB_ARES			86
96*d15b1ff1SSricharan R #define GCC_NSS_CE_AXI_ARES			87
97*d15b1ff1SSricharan R #define GCC_NSSNOC_CE_APB_ARES			88
98*d15b1ff1SSricharan R #define GCC_NSSNOC_CE_AXI_ARES			89
99*d15b1ff1SSricharan R #define GCC_NSSNOC_UBI0_AHB_ARES		90
100*d15b1ff1SSricharan R #define GCC_NSSNOC_SNOC_ARES			91
101*d15b1ff1SSricharan R #define GCC_NSSNOC_CRYPTO_ARES			92
102*d15b1ff1SSricharan R #define GCC_NSSNOC_ATB_ARES			93
103*d15b1ff1SSricharan R #define GCC_NSSNOC_QOSGEN_REF_ARES		94
104*d15b1ff1SSricharan R #define GCC_NSSNOC_TIMEOUT_REF_ARES		95
105*d15b1ff1SSricharan R #define GCC_PCIE0_PIPE_ARES			96
106*d15b1ff1SSricharan R #define GCC_PCIE0_SLEEP_ARES			97
107*d15b1ff1SSricharan R #define GCC_PCIE0_CORE_STICKY_ARES		98
108*d15b1ff1SSricharan R #define GCC_PCIE0_AXI_MASTER_ARES		99
109*d15b1ff1SSricharan R #define GCC_PCIE0_AXI_SLAVE_ARES		100
110*d15b1ff1SSricharan R #define GCC_PCIE0_AHB_ARES			101
111*d15b1ff1SSricharan R #define GCC_PCIE0_AXI_MASTER_STICKY_ARES	102
112*d15b1ff1SSricharan R #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES		103
113*d15b1ff1SSricharan R #define GCC_PPE_FULL_RESET			104
114*d15b1ff1SSricharan R #define GCC_UNIPHY0_SOFT_RESET			105
115*d15b1ff1SSricharan R #define GCC_UNIPHY0_XPCS_RESET			106
116*d15b1ff1SSricharan R #define GCC_UNIPHY1_SOFT_RESET			107
117*d15b1ff1SSricharan R #define GCC_UNIPHY1_XPCS_RESET			108
118*d15b1ff1SSricharan R #define GCC_EDMA_HW_RESET			109
119*d15b1ff1SSricharan R #define GCC_ADSS_BCR				110
120*d15b1ff1SSricharan R #define GCC_NSS_NOC_TBU_BCR			111
121*d15b1ff1SSricharan R #define GCC_NSSPORT1_RESET			112
122*d15b1ff1SSricharan R #define GCC_NSSPORT2_RESET			113
123*d15b1ff1SSricharan R #define GCC_NSSPORT3_RESET			114
124*d15b1ff1SSricharan R #define GCC_NSSPORT4_RESET			115
125*d15b1ff1SSricharan R #define GCC_NSSPORT5_RESET			116
126*d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT1_ARES			117
127*d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT2_ARES			118
128*d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT3_ARES			119
129*d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT4_ARES			120
130*d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT5_ARES			121
131*d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT_4_5_RESET		122
132*d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT_4_RESET		123
133*d15b1ff1SSricharan R #define GCC_LPASS_BCR				124
134*d15b1ff1SSricharan R #define GCC_UBI32_TBU_BCR			125
135*d15b1ff1SSricharan R #define GCC_LPASS_TBU_BCR			126
136*d15b1ff1SSricharan R #define GCC_WCSSAON_RESET			127
137*d15b1ff1SSricharan R #define GCC_LPASS_Q6_AXIM_ARES			128
138*d15b1ff1SSricharan R #define GCC_LPASS_Q6SS_TSCTR_1TO2_ARES		129
139*d15b1ff1SSricharan R #define GCC_LPASS_Q6SS_TRIG_ARES		130
140*d15b1ff1SSricharan R #define GCC_LPASS_Q6_ATBM_AT_ARES		131
141*d15b1ff1SSricharan R #define GCC_LPASS_Q6_PCLKDBG_ARES		132
142*d15b1ff1SSricharan R #define GCC_LPASS_CORE_AXIM_ARES		133
143*d15b1ff1SSricharan R #define GCC_LPASS_SNOC_CFG_ARES			134
144*d15b1ff1SSricharan R #define GCC_WCSS_DBG_ARES			135
145*d15b1ff1SSricharan R #define GCC_WCSS_ECAHB_ARES			136
146*d15b1ff1SSricharan R #define GCC_WCSS_ACMT_ARES			137
147*d15b1ff1SSricharan R #define GCC_WCSS_DBG_BDG_ARES			138
148*d15b1ff1SSricharan R #define GCC_WCSS_AHB_S_ARES			139
149*d15b1ff1SSricharan R #define GCC_WCSS_AXI_M_ARES			140
150*d15b1ff1SSricharan R #define GCC_Q6SS_DBG_ARES			141
151*d15b1ff1SSricharan R #define GCC_Q6_AHB_S_ARES			142
152*d15b1ff1SSricharan R #define GCC_Q6_AHB_ARES				143
153*d15b1ff1SSricharan R #define GCC_Q6_AXIM2_ARES			144
154*d15b1ff1SSricharan R #define GCC_Q6_AXIM_ARES			145
155*d15b1ff1SSricharan R #define GCC_UBI0_CORE_ARES			146
156*d15b1ff1SSricharan R 
157*d15b1ff1SSricharan R #endif
158