11d6866e8SRunyang Chen /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 21d6866e8SRunyang Chen /* 31d6866e8SRunyang Chen * Copyright (c) 2022 MediaTek Inc. 41d6866e8SRunyang Chen * Author: Runyang Chen <runyang.chen@mediatek.com> 51d6866e8SRunyang Chen */ 61d6866e8SRunyang Chen 71d6866e8SRunyang Chen #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186 81d6866e8SRunyang Chen #define _DT_BINDINGS_RESET_CONTROLLER_MT8186 91d6866e8SRunyang Chen 10*5ea61b47SRex-BC Chen /* TOPRGU resets */ 111d6866e8SRunyang Chen #define MT8186_TOPRGU_INFRA_SW_RST 0 121d6866e8SRunyang Chen #define MT8186_TOPRGU_MM_SW_RST 1 131d6866e8SRunyang Chen #define MT8186_TOPRGU_MFG_SW_RST 2 141d6866e8SRunyang Chen #define MT8186_TOPRGU_VENC_SW_RST 3 151d6866e8SRunyang Chen #define MT8186_TOPRGU_VDEC_SW_RST 4 161d6866e8SRunyang Chen #define MT8186_TOPRGU_IMG_SW_RST 5 171d6866e8SRunyang Chen #define MT8186_TOPRGU_DDR_SW_RST 6 181d6866e8SRunyang Chen #define MT8186_TOPRGU_INFRA_AO_SW_RST 8 191d6866e8SRunyang Chen #define MT8186_TOPRGU_CONNSYS_SW_RST 9 201d6866e8SRunyang Chen #define MT8186_TOPRGU_APMIXED_SW_RST 10 211d6866e8SRunyang Chen #define MT8186_TOPRGU_PWRAP_SW_RST 11 221d6866e8SRunyang Chen #define MT8186_TOPRGU_CONN_MCU_SW_RST 12 231d6866e8SRunyang Chen #define MT8186_TOPRGU_IPNNA_SW_RST 13 241d6866e8SRunyang Chen #define MT8186_TOPRGU_WPE_SW_RST 14 251d6866e8SRunyang Chen #define MT8186_TOPRGU_ADSP_SW_RST 15 261d6866e8SRunyang Chen #define MT8186_TOPRGU_AUDIO_SW_RST 17 271d6866e8SRunyang Chen #define MT8186_TOPRGU_CAM_MAIN_SW_RST 18 281d6866e8SRunyang Chen #define MT8186_TOPRGU_CAM_RAWA_SW_RST 19 291d6866e8SRunyang Chen #define MT8186_TOPRGU_CAM_RAWB_SW_RST 20 301d6866e8SRunyang Chen #define MT8186_TOPRGU_IPE_SW_RST 21 311d6866e8SRunyang Chen #define MT8186_TOPRGU_IMG2_SW_RST 22 321d6866e8SRunyang Chen #define MT8186_TOPRGU_SW_RST_NUM 23 331d6866e8SRunyang Chen 341d6866e8SRunyang Chen /* MMSYS resets */ 351d6866e8SRunyang Chen #define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19 361d6866e8SRunyang Chen 37*5ea61b47SRex-BC Chen /* INFRA resets */ 38*5ea61b47SRex-BC Chen #define MT8186_INFRA_THERMAL_CTRL_RST 0 39*5ea61b47SRex-BC Chen #define MT8186_INFRA_PTP_CTRL_RST 1 40*5ea61b47SRex-BC Chen 411d6866e8SRunyang Chen #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */ 42