14cab5bf6SAndrey Smirnov /* SPDX-License-Identifier: GPL-2.0 */ 24cab5bf6SAndrey Smirnov /* 34cab5bf6SAndrey Smirnov * Copyright (C) 2018 Zodiac Inflight Innovations 44cab5bf6SAndrey Smirnov * 54cab5bf6SAndrey Smirnov * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 64cab5bf6SAndrey Smirnov */ 74cab5bf6SAndrey Smirnov 84cab5bf6SAndrey Smirnov #ifndef DT_BINDING_RESET_IMX8MQ_H 94cab5bf6SAndrey Smirnov #define DT_BINDING_RESET_IMX8MQ_H 104cab5bf6SAndrey Smirnov 114cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_CORE_POR_RESET0 0 124cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_CORE_POR_RESET1 1 134cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_CORE_POR_RESET2 2 144cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_CORE_POR_RESET3 3 154cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_CORE_RESET0 4 164cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_CORE_RESET1 5 174cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_CORE_RESET2 6 184cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_CORE_RESET3 7 194cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_DBG_RESET0 8 204cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_DBG_RESET1 9 214cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_DBG_RESET2 10 224cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_DBG_RESET3 11 234cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_ETM_RESET0 12 244cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_ETM_RESET1 13 254cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_ETM_RESET2 14 264cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_ETM_RESET3 15 274cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_SOC_DBG_RESET 16 284cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_A53_L2RESET 17 294cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 304cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_OTG1_PHY_RESET 19 31ecd910f4SAnson Huang #define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */ 32ecd910f4SAnson Huang #define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */ 33ecd910f4SAnson Huang #define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */ 34ecd910f4SAnson Huang #define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */ 35ecd910f4SAnson Huang #define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */ 36ecd910f4SAnson Huang #define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */ 37ecd910f4SAnson Huang #define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */ 38ecd910f4SAnson Huang #define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */ 39ecd910f4SAnson Huang #define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */ 40ecd910f4SAnson Huang #define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */ 41ecd910f4SAnson Huang #define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */ 424cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_DISP_RESET 31 434cab5bf6SAndrey Smirnov #define IMX8MQ_RESET_GPU_RESET 32 44ecd910f4SAnson Huang #define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */ 45ecd910f4SAnson Huang #define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */ 46ecd910f4SAnson Huang #define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */ 47ecd910f4SAnson Huang #define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */ 48ecd910f4SAnson Huang #define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */ 49ecd910f4SAnson Huang #define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */ 50ecd910f4SAnson Huang #define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */ 51ecd910f4SAnson Huang #define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */ 52ecd910f4SAnson Huang #define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */ 53ecd910f4SAnson Huang #define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */ 54ecd910f4SAnson Huang #define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */ 55ecd910f4SAnson Huang #define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */ 56ecd910f4SAnson Huang #define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */ 57ecd910f4SAnson Huang #define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */ 58ecd910f4SAnson Huang #define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */ 59ecd910f4SAnson Huang #define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */ 60ecd910f4SAnson Huang #define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */ 61*cbc111d1SPeng Fan #define IMX8MQ_RESET_SW_M4C_RST 50 62*cbc111d1SPeng Fan #define IMX8MQ_RESET_SW_M4P_RST 51 63*cbc111d1SPeng Fan #define IMX8MQ_RESET_M4_ENABLE 52 644cab5bf6SAndrey Smirnov 65*cbc111d1SPeng Fan #define IMX8MQ_RESET_NUM 53 664cab5bf6SAndrey Smirnov 674cab5bf6SAndrey Smirnov #endif 68