1*a35bcf7cSManivannan Sadhasivam // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2*a35bcf7cSManivannan Sadhasivam // 3*a35bcf7cSManivannan Sadhasivam // Device Tree binding constants for Actions Semi S900 Reset Management Unit 4*a35bcf7cSManivannan Sadhasivam // 5*a35bcf7cSManivannan Sadhasivam // Copyright (c) 2018 Linaro Ltd. 6*a35bcf7cSManivannan Sadhasivam 7*a35bcf7cSManivannan Sadhasivam #ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H 8*a35bcf7cSManivannan Sadhasivam #define __DT_BINDINGS_ACTIONS_S900_RESET_H 9*a35bcf7cSManivannan Sadhasivam 10*a35bcf7cSManivannan Sadhasivam #define RESET_CHIPID 0 11*a35bcf7cSManivannan Sadhasivam #define RESET_CPU_SCNT 1 12*a35bcf7cSManivannan Sadhasivam #define RESET_SRAMI 2 13*a35bcf7cSManivannan Sadhasivam #define RESET_DDR_CTL_PHY 3 14*a35bcf7cSManivannan Sadhasivam #define RESET_DMAC 4 15*a35bcf7cSManivannan Sadhasivam #define RESET_GPIO 5 16*a35bcf7cSManivannan Sadhasivam #define RESET_BISP_AXI 6 17*a35bcf7cSManivannan Sadhasivam #define RESET_CSI0 7 18*a35bcf7cSManivannan Sadhasivam #define RESET_CSI1 8 19*a35bcf7cSManivannan Sadhasivam #define RESET_DE 9 20*a35bcf7cSManivannan Sadhasivam #define RESET_DSI 10 21*a35bcf7cSManivannan Sadhasivam #define RESET_GPU3D_PA 11 22*a35bcf7cSManivannan Sadhasivam #define RESET_GPU3D_PB 12 23*a35bcf7cSManivannan Sadhasivam #define RESET_HDE 13 24*a35bcf7cSManivannan Sadhasivam #define RESET_I2C0 14 25*a35bcf7cSManivannan Sadhasivam #define RESET_I2C1 15 26*a35bcf7cSManivannan Sadhasivam #define RESET_I2C2 16 27*a35bcf7cSManivannan Sadhasivam #define RESET_I2C3 17 28*a35bcf7cSManivannan Sadhasivam #define RESET_I2C4 18 29*a35bcf7cSManivannan Sadhasivam #define RESET_I2C5 19 30*a35bcf7cSManivannan Sadhasivam #define RESET_IMX 20 31*a35bcf7cSManivannan Sadhasivam #define RESET_NANDC0 21 32*a35bcf7cSManivannan Sadhasivam #define RESET_NANDC1 22 33*a35bcf7cSManivannan Sadhasivam #define RESET_SD0 23 34*a35bcf7cSManivannan Sadhasivam #define RESET_SD1 24 35*a35bcf7cSManivannan Sadhasivam #define RESET_SD2 25 36*a35bcf7cSManivannan Sadhasivam #define RESET_SD3 26 37*a35bcf7cSManivannan Sadhasivam #define RESET_SPI0 27 38*a35bcf7cSManivannan Sadhasivam #define RESET_SPI1 28 39*a35bcf7cSManivannan Sadhasivam #define RESET_SPI2 29 40*a35bcf7cSManivannan Sadhasivam #define RESET_SPI3 30 41*a35bcf7cSManivannan Sadhasivam #define RESET_UART0 31 42*a35bcf7cSManivannan Sadhasivam #define RESET_UART1 32 43*a35bcf7cSManivannan Sadhasivam #define RESET_UART2 33 44*a35bcf7cSManivannan Sadhasivam #define RESET_UART3 34 45*a35bcf7cSManivannan Sadhasivam #define RESET_UART4 35 46*a35bcf7cSManivannan Sadhasivam #define RESET_UART5 36 47*a35bcf7cSManivannan Sadhasivam #define RESET_UART6 37 48*a35bcf7cSManivannan Sadhasivam #define RESET_HDMI 38 49*a35bcf7cSManivannan Sadhasivam #define RESET_LVDS 39 50*a35bcf7cSManivannan Sadhasivam #define RESET_EDP 40 51*a35bcf7cSManivannan Sadhasivam #define RESET_USB2HUB 41 52*a35bcf7cSManivannan Sadhasivam #define RESET_USB2HSIC 42 53*a35bcf7cSManivannan Sadhasivam #define RESET_USB3 43 54*a35bcf7cSManivannan Sadhasivam #define RESET_PCM1 44 55*a35bcf7cSManivannan Sadhasivam #define RESET_AUDIO 45 56*a35bcf7cSManivannan Sadhasivam #define RESET_PCM0 46 57*a35bcf7cSManivannan Sadhasivam #define RESET_SE 47 58*a35bcf7cSManivannan Sadhasivam #define RESET_GIC 48 59*a35bcf7cSManivannan Sadhasivam #define RESET_DDR_CTL_PHY_AXI 49 60*a35bcf7cSManivannan Sadhasivam #define RESET_CMU_DDR 50 61*a35bcf7cSManivannan Sadhasivam #define RESET_DMM 51 62*a35bcf7cSManivannan Sadhasivam #define RESET_HDCP2TX 52 63*a35bcf7cSManivannan Sadhasivam #define RESET_ETHERNET 53 64*a35bcf7cSManivannan Sadhasivam 65*a35bcf7cSManivannan Sadhasivam #endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */ 66