1*8fd27fb4SRajan Vaja /* SPDX-License-Identifier: GPL-2.0 */ 2*8fd27fb4SRajan Vaja /* 3*8fd27fb4SRajan Vaja * Copyright (C) 2018 Xilinx, Inc. 4*8fd27fb4SRajan Vaja */ 5*8fd27fb4SRajan Vaja 6*8fd27fb4SRajan Vaja #ifndef _DT_BINDINGS_ZYNQMP_POWER_H 7*8fd27fb4SRajan Vaja #define _DT_BINDINGS_ZYNQMP_POWER_H 8*8fd27fb4SRajan Vaja 9*8fd27fb4SRajan Vaja #define PD_USB_0 22 10*8fd27fb4SRajan Vaja #define PD_USB_1 23 11*8fd27fb4SRajan Vaja #define PD_TTC_0 24 12*8fd27fb4SRajan Vaja #define PD_TTC_1 25 13*8fd27fb4SRajan Vaja #define PD_TTC_2 26 14*8fd27fb4SRajan Vaja #define PD_TTC_3 27 15*8fd27fb4SRajan Vaja #define PD_SATA 28 16*8fd27fb4SRajan Vaja #define PD_ETH_0 29 17*8fd27fb4SRajan Vaja #define PD_ETH_1 30 18*8fd27fb4SRajan Vaja #define PD_ETH_2 31 19*8fd27fb4SRajan Vaja #define PD_ETH_3 32 20*8fd27fb4SRajan Vaja #define PD_UART_0 33 21*8fd27fb4SRajan Vaja #define PD_UART_1 34 22*8fd27fb4SRajan Vaja #define PD_SPI_0 35 23*8fd27fb4SRajan Vaja #define PD_SPI_1 36 24*8fd27fb4SRajan Vaja #define PD_I2C_0 37 25*8fd27fb4SRajan Vaja #define PD_I2C_1 38 26*8fd27fb4SRajan Vaja #define PD_SD_0 39 27*8fd27fb4SRajan Vaja #define PD_SD_1 40 28*8fd27fb4SRajan Vaja #define PD_DP 41 29*8fd27fb4SRajan Vaja #define PD_GDMA 42 30*8fd27fb4SRajan Vaja #define PD_ADMA 43 31*8fd27fb4SRajan Vaja #define PD_NAND 44 32*8fd27fb4SRajan Vaja #define PD_QSPI 45 33*8fd27fb4SRajan Vaja #define PD_GPIO 46 34*8fd27fb4SRajan Vaja #define PD_CAN_0 47 35*8fd27fb4SRajan Vaja #define PD_CAN_1 48 36*8fd27fb4SRajan Vaja #define PD_GPU 58 37*8fd27fb4SRajan Vaja #define PD_PCIE 59 38*8fd27fb4SRajan Vaja 39*8fd27fb4SRajan Vaja #endif 40