1*67944950SFinley Xiao /* SPDX-License-Identifier: (GPL-2.0 or MIT) */ 2*67944950SFinley Xiao #ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__ 3*67944950SFinley Xiao #define __DT_BINDINGS_POWER_RK3588_POWER_H__ 4*67944950SFinley Xiao 5*67944950SFinley Xiao /* VD_LITDSU */ 6*67944950SFinley Xiao #define RK3588_PD_CPU_0 0 7*67944950SFinley Xiao #define RK3588_PD_CPU_1 1 8*67944950SFinley Xiao #define RK3588_PD_CPU_2 2 9*67944950SFinley Xiao #define RK3588_PD_CPU_3 3 10*67944950SFinley Xiao 11*67944950SFinley Xiao /* VD_BIGCORE0 */ 12*67944950SFinley Xiao #define RK3588_PD_CPU_4 4 13*67944950SFinley Xiao #define RK3588_PD_CPU_5 5 14*67944950SFinley Xiao 15*67944950SFinley Xiao /* VD_BIGCORE1 */ 16*67944950SFinley Xiao #define RK3588_PD_CPU_6 6 17*67944950SFinley Xiao #define RK3588_PD_CPU_7 7 18*67944950SFinley Xiao 19*67944950SFinley Xiao /* VD_NPU */ 20*67944950SFinley Xiao #define RK3588_PD_NPU 8 21*67944950SFinley Xiao #define RK3588_PD_NPUTOP 9 22*67944950SFinley Xiao #define RK3588_PD_NPU1 10 23*67944950SFinley Xiao #define RK3588_PD_NPU2 11 24*67944950SFinley Xiao 25*67944950SFinley Xiao /* VD_GPU */ 26*67944950SFinley Xiao #define RK3588_PD_GPU 12 27*67944950SFinley Xiao 28*67944950SFinley Xiao /* VD_VCODEC */ 29*67944950SFinley Xiao #define RK3588_PD_VCODEC 13 30*67944950SFinley Xiao #define RK3588_PD_RKVDEC0 14 31*67944950SFinley Xiao #define RK3588_PD_RKVDEC1 15 32*67944950SFinley Xiao #define RK3588_PD_VENC0 16 33*67944950SFinley Xiao #define RK3588_PD_VENC1 17 34*67944950SFinley Xiao 35*67944950SFinley Xiao /* VD_DD01 */ 36*67944950SFinley Xiao #define RK3588_PD_DDR01 18 37*67944950SFinley Xiao 38*67944950SFinley Xiao /* VD_DD23 */ 39*67944950SFinley Xiao #define RK3588_PD_DDR23 19 40*67944950SFinley Xiao 41*67944950SFinley Xiao /* VD_LOGIC */ 42*67944950SFinley Xiao #define RK3588_PD_CENTER 20 43*67944950SFinley Xiao #define RK3588_PD_VDPU 21 44*67944950SFinley Xiao #define RK3588_PD_RGA30 22 45*67944950SFinley Xiao #define RK3588_PD_AV1 23 46*67944950SFinley Xiao #define RK3588_PD_VOP 24 47*67944950SFinley Xiao #define RK3588_PD_VO0 25 48*67944950SFinley Xiao #define RK3588_PD_VO1 26 49*67944950SFinley Xiao #define RK3588_PD_VI 27 50*67944950SFinley Xiao #define RK3588_PD_ISP1 28 51*67944950SFinley Xiao #define RK3588_PD_FEC 29 52*67944950SFinley Xiao #define RK3588_PD_RGA31 30 53*67944950SFinley Xiao #define RK3588_PD_USB 31 54*67944950SFinley Xiao #define RK3588_PD_PHP 32 55*67944950SFinley Xiao #define RK3588_PD_GMAC 33 56*67944950SFinley Xiao #define RK3588_PD_PCIE 34 57*67944950SFinley Xiao #define RK3588_PD_NVM 35 58*67944950SFinley Xiao #define RK3588_PD_NVM0 36 59*67944950SFinley Xiao #define RK3588_PD_SDIO 37 60*67944950SFinley Xiao #define RK3588_PD_AUDIO 38 61*67944950SFinley Xiao #define RK3588_PD_SECURE 39 62*67944950SFinley Xiao #define RK3588_PD_SDMMC 40 63*67944950SFinley Xiao #define RK3588_PD_CRYPTO 41 64*67944950SFinley Xiao #define RK3588_PD_BUS 42 65*67944950SFinley Xiao 66*67944950SFinley Xiao /* VD_PMU */ 67*67944950SFinley Xiao #define RK3588_PD_PMU1 43 68*67944950SFinley Xiao 69*67944950SFinley Xiao #endif 70