xref: /openbmc/linux/include/dt-bindings/power/r8a779a0-sysc.h (revision cbecf716ca618fd44feda6bd9a64a8179d031fc5)
1*c2ff0810SYoshihiro Shimoda /* SPDX-License-Identifier: GPL-2.0-only */
2*c2ff0810SYoshihiro Shimoda /*
3*c2ff0810SYoshihiro Shimoda  * Copyright (C) 2020 Renesas Electronics Corp.
4*c2ff0810SYoshihiro Shimoda  */
5*c2ff0810SYoshihiro Shimoda #ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
6*c2ff0810SYoshihiro Shimoda #define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
7*c2ff0810SYoshihiro Shimoda 
8*c2ff0810SYoshihiro Shimoda /*
9*c2ff0810SYoshihiro Shimoda  * These power domain indices match the Power Domain Register Numbers (PDR)
10*c2ff0810SYoshihiro Shimoda  */
11*c2ff0810SYoshihiro Shimoda 
12*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1E0D0C0		0
13*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1E0D0C1		1
14*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1E0D1C0		2
15*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1E0D1C1		3
16*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1E1D0C0		4
17*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1E1D0C1		5
18*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1E1D1C0		6
19*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1E1D1C1		7
20*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2E0D0		16
21*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2E0D1		17
22*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2E1D0		18
23*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2E1D1		19
24*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A3E0		20
25*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A3E1		21
26*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_3DG_A		24
27*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_3DG_B		25
28*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1CNN2		32
29*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1DSP0		33
30*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2IMP01		34
31*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2DP0		35
32*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2CV0		36
33*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2CV1		37
34*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2CV4		38
35*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2CV6		39
36*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2CN2		40
37*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1CNN0		41
38*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2CN0		42
39*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A3IR		43
40*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1CNN1		44
41*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A1DSP1		45
42*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2IMP23		46
43*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2DP1		47
44*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2CV2		48
45*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2CV3		49
46*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2CV5		50
47*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2CV7		51
48*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A2CN1		52
49*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A3VIP0		56
50*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A3VIP1		57
51*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A3VIP2		58
52*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A3VIP3		59
53*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A3ISP01		60
54*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_A3ISP23		61
55*c2ff0810SYoshihiro Shimoda 
56*c2ff0810SYoshihiro Shimoda /* Always-on power area */
57*c2ff0810SYoshihiro Shimoda #define R8A779A0_PD_ALWAYS_ON		64
58*c2ff0810SYoshihiro Shimoda 
59*c2ff0810SYoshihiro Shimoda #endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */
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