xref: /openbmc/linux/include/dt-bindings/power/r8a77961-sysc.h (revision c95baf12f5077419db01313ab61c2aac007d40cd)
1*640f9606SGeert Uytterhoeven /* SPDX-License-Identifier: GPL-2.0-only */
2*640f9606SGeert Uytterhoeven /*
3*640f9606SGeert Uytterhoeven  * Copyright (C) 2019 Glider bvba
4*640f9606SGeert Uytterhoeven  */
5*640f9606SGeert Uytterhoeven #ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__
6*640f9606SGeert Uytterhoeven #define __DT_BINDINGS_POWER_R8A77961_SYSC_H__
7*640f9606SGeert Uytterhoeven 
8*640f9606SGeert Uytterhoeven /*
9*640f9606SGeert Uytterhoeven  * These power domain indices match the numbers of the interrupt bits
10*640f9606SGeert Uytterhoeven  * representing the power areas in the various Interrupt Registers
11*640f9606SGeert Uytterhoeven  * (e.g. SYSCISR, Interrupt Status Register)
12*640f9606SGeert Uytterhoeven  */
13*640f9606SGeert Uytterhoeven 
14*640f9606SGeert Uytterhoeven #define R8A77961_PD_CA57_CPU0		 0
15*640f9606SGeert Uytterhoeven #define R8A77961_PD_CA57_CPU1		 1
16*640f9606SGeert Uytterhoeven #define R8A77961_PD_CA53_CPU0		 5
17*640f9606SGeert Uytterhoeven #define R8A77961_PD_CA53_CPU1		 6
18*640f9606SGeert Uytterhoeven #define R8A77961_PD_CA53_CPU2		 7
19*640f9606SGeert Uytterhoeven #define R8A77961_PD_CA53_CPU3		 8
20*640f9606SGeert Uytterhoeven #define R8A77961_PD_CA57_SCU		12
21*640f9606SGeert Uytterhoeven #define R8A77961_PD_CR7			13
22*640f9606SGeert Uytterhoeven #define R8A77961_PD_A3VC		14
23*640f9606SGeert Uytterhoeven #define R8A77961_PD_3DG_A		17
24*640f9606SGeert Uytterhoeven #define R8A77961_PD_3DG_B		18
25*640f9606SGeert Uytterhoeven #define R8A77961_PD_CA53_SCU		21
26*640f9606SGeert Uytterhoeven #define R8A77961_PD_A3IR		24
27*640f9606SGeert Uytterhoeven #define R8A77961_PD_A2VC1		26
28*640f9606SGeert Uytterhoeven 
29*640f9606SGeert Uytterhoeven /* Always-on power area */
30*640f9606SGeert Uytterhoeven #define R8A77961_PD_ALWAYS_ON		32
31*640f9606SGeert Uytterhoeven 
32*640f9606SGeert Uytterhoeven #endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */
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