1*c8a00689SChun-Jie Chen /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2*c8a00689SChun-Jie Chen /* 3*c8a00689SChun-Jie Chen * Copyright (c) 2022 MediaTek Inc. 4*c8a00689SChun-Jie Chen * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5*c8a00689SChun-Jie Chen */ 6*c8a00689SChun-Jie Chen 7*c8a00689SChun-Jie Chen #ifndef _DT_BINDINGS_POWER_MT8186_POWER_H 8*c8a00689SChun-Jie Chen #define _DT_BINDINGS_POWER_MT8186_POWER_H 9*c8a00689SChun-Jie Chen 10*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_MFG0 0 11*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_MFG1 1 12*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_MFG2 2 13*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_MFG3 3 14*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_SSUSB 4 15*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_SSUSB_P1 5 16*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_DIS 6 17*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_IMG 7 18*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_IMG2 8 19*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_IPE 9 20*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_CAM 10 21*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_CAM_RAWA 11 22*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_CAM_RAWB 12 23*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_VENC 13 24*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_VDEC 14 25*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_WPE 15 26*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_CONN_ON 16 27*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_CSIRX_TOP 17 28*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_ADSP_AO 18 29*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_ADSP_INFRA 19 30*c8a00689SChun-Jie Chen #define MT8186_POWER_DOMAIN_ADSP_TOP 20 31*c8a00689SChun-Jie Chen 32*c8a00689SChun-Jie Chen #endif /* _DT_BINDINGS_POWER_MT8186_POWER_H */ 33