1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2588c43a7SThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H 3588c43a7SThierry Reding #define DT_BINDINGS_MEMORY_TEGRA210_MC_H 4588c43a7SThierry Reding 5588c43a7SThierry Reding #define TEGRA_SWGROUP_PTC 0 6588c43a7SThierry Reding #define TEGRA_SWGROUP_DC 1 7588c43a7SThierry Reding #define TEGRA_SWGROUP_DCB 2 8588c43a7SThierry Reding #define TEGRA_SWGROUP_AFI 3 9588c43a7SThierry Reding #define TEGRA_SWGROUP_AVPC 4 10588c43a7SThierry Reding #define TEGRA_SWGROUP_HDA 5 11588c43a7SThierry Reding #define TEGRA_SWGROUP_HC 6 12588c43a7SThierry Reding #define TEGRA_SWGROUP_NVENC 7 13588c43a7SThierry Reding #define TEGRA_SWGROUP_PPCS 8 14588c43a7SThierry Reding #define TEGRA_SWGROUP_SATA 9 15588c43a7SThierry Reding #define TEGRA_SWGROUP_MPCORE 10 16588c43a7SThierry Reding #define TEGRA_SWGROUP_ISP2 11 17588c43a7SThierry Reding #define TEGRA_SWGROUP_XUSB_HOST 12 18588c43a7SThierry Reding #define TEGRA_SWGROUP_XUSB_DEV 13 19588c43a7SThierry Reding #define TEGRA_SWGROUP_ISP2B 14 20588c43a7SThierry Reding #define TEGRA_SWGROUP_TSEC 15 21588c43a7SThierry Reding #define TEGRA_SWGROUP_A9AVP 16 22588c43a7SThierry Reding #define TEGRA_SWGROUP_GPU 17 23588c43a7SThierry Reding #define TEGRA_SWGROUP_SDMMC1A 18 24588c43a7SThierry Reding #define TEGRA_SWGROUP_SDMMC2A 19 25588c43a7SThierry Reding #define TEGRA_SWGROUP_SDMMC3A 20 26588c43a7SThierry Reding #define TEGRA_SWGROUP_SDMMC4A 21 27588c43a7SThierry Reding #define TEGRA_SWGROUP_VIC 22 28588c43a7SThierry Reding #define TEGRA_SWGROUP_VI 23 29588c43a7SThierry Reding #define TEGRA_SWGROUP_NVDEC 24 30588c43a7SThierry Reding #define TEGRA_SWGROUP_APE 25 31588c43a7SThierry Reding #define TEGRA_SWGROUP_NVJPG 26 32588c43a7SThierry Reding #define TEGRA_SWGROUP_SE 27 33588c43a7SThierry Reding #define TEGRA_SWGROUP_AXIAP 28 34588c43a7SThierry Reding #define TEGRA_SWGROUP_ETR 29 35588c43a7SThierry Reding #define TEGRA_SWGROUP_TSECB 30 36*65abc8efSNicolin Chen #define TEGRA_SWGROUP_NV 31 37*65abc8efSNicolin Chen #define TEGRA_SWGROUP_NV2 32 38*65abc8efSNicolin Chen #define TEGRA_SWGROUP_PPCS1 33 39*65abc8efSNicolin Chen #define TEGRA_SWGROUP_DC1 34 40*65abc8efSNicolin Chen #define TEGRA_SWGROUP_PPCS2 35 41*65abc8efSNicolin Chen #define TEGRA_SWGROUP_HC1 36 42*65abc8efSNicolin Chen #define TEGRA_SWGROUP_SE1 37 43*65abc8efSNicolin Chen #define TEGRA_SWGROUP_TSEC1 38 44*65abc8efSNicolin Chen #define TEGRA_SWGROUP_TSECB1 39 45*65abc8efSNicolin Chen #define TEGRA_SWGROUP_NVDEC1 40 46588c43a7SThierry Reding 475c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_AFI 0 485c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_AVPC 1 495c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_DC 2 505c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_DCB 3 515c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_HC 4 525c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_HDA 5 535c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_ISP2 6 545c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_MPCORE 7 555c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_NVENC 8 565c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_PPCS 9 575c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_SATA 10 585c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_VI 11 595c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_VIC 12 605c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_XUSB_HOST 13 615c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_XUSB_DEV 14 625c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_A9AVP 15 635c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_TSEC 16 645c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_SDMMC1 17 655c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_SDMMC2 18 665c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_SDMMC3 19 675c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_SDMMC4 20 685c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_ISP2B 21 695c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_GPU 22 705c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_NVDEC 23 715c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_APE 24 725c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_SE 25 735c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_NVJPG 26 745c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_AXIAP 27 755c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_ETR 28 765c8d08f3SDmitry Osipenko #define TEGRA210_MC_RESET_TSECB 29 775c8d08f3SDmitry Osipenko 78588c43a7SThierry Reding #endif 79