1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 289184651SThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H 389184651SThierry Reding #define DT_BINDINGS_MEMORY_TEGRA114_MC_H 489184651SThierry Reding 589184651SThierry Reding #define TEGRA_SWGROUP_PTC 0 689184651SThierry Reding #define TEGRA_SWGROUP_DC 1 789184651SThierry Reding #define TEGRA_SWGROUP_DCB 2 889184651SThierry Reding #define TEGRA_SWGROUP_EPP 3 989184651SThierry Reding #define TEGRA_SWGROUP_G2 4 1089184651SThierry Reding #define TEGRA_SWGROUP_AVPC 5 1189184651SThierry Reding #define TEGRA_SWGROUP_NV 6 1289184651SThierry Reding #define TEGRA_SWGROUP_HDA 7 1389184651SThierry Reding #define TEGRA_SWGROUP_HC 8 1489184651SThierry Reding #define TEGRA_SWGROUP_MSENC 9 1589184651SThierry Reding #define TEGRA_SWGROUP_PPCS 10 1689184651SThierry Reding #define TEGRA_SWGROUP_VDE 11 1789184651SThierry Reding #define TEGRA_SWGROUP_MPCORELP 12 1889184651SThierry Reding #define TEGRA_SWGROUP_MPCORE 13 1989184651SThierry Reding #define TEGRA_SWGROUP_VI 14 2089184651SThierry Reding #define TEGRA_SWGROUP_ISP 15 2189184651SThierry Reding #define TEGRA_SWGROUP_XUSB_HOST 16 2289184651SThierry Reding #define TEGRA_SWGROUP_XUSB_DEV 17 2389184651SThierry Reding #define TEGRA_SWGROUP_EMUCIF 18 2489184651SThierry Reding #define TEGRA_SWGROUP_TSEC 19 2589184651SThierry Reding 26*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_AVPC 0 27*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_DC 1 28*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_DCB 2 29*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_EPP 3 30*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_2D 4 31*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_HC 5 32*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_HDA 6 33*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_ISP 7 34*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_MPCORE 8 35*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_MPCORELP 9 36*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_MPE 10 37*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_3D 11 38*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_3D2 12 39*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_PPCS 13 40*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_VDE 14 41*a1be3cfdSDmitry Osipenko #define TEGRA114_MC_RESET_VI 15 425c8d08f3SDmitry Osipenko 4389184651SThierry Reding #endif 44