129746d01SYong Wu /* SPDX-License-Identifier: GPL-2.0 */ 229746d01SYong Wu /* 329746d01SYong Wu * Copyright (c) 2018 MediaTek Inc. 429746d01SYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 529746d01SYong Wu */ 6*ddd3e349SYong Wu #ifndef _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ 7*ddd3e349SYong Wu #define _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ 829746d01SYong Wu 95cf482f2SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 1029746d01SYong Wu 1129746d01SYong Wu #define M4U_LARB0_ID 0 1229746d01SYong Wu #define M4U_LARB1_ID 1 1329746d01SYong Wu #define M4U_LARB2_ID 2 1429746d01SYong Wu #define M4U_LARB3_ID 3 1529746d01SYong Wu #define M4U_LARB4_ID 4 1629746d01SYong Wu #define M4U_LARB5_ID 5 1729746d01SYong Wu #define M4U_LARB6_ID 6 1829746d01SYong Wu #define M4U_LARB7_ID 7 1929746d01SYong Wu 2029746d01SYong Wu /* larb0 */ 2129746d01SYong Wu #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 2229746d01SYong Wu #define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1) 2329746d01SYong Wu #define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2) 2429746d01SYong Wu #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) 2529746d01SYong Wu #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4) 2629746d01SYong Wu #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) 2729746d01SYong Wu #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) 2829746d01SYong Wu #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) 2929746d01SYong Wu #define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8) 3029746d01SYong Wu #define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9) 3129746d01SYong Wu 3229746d01SYong Wu /* larb1 */ 3329746d01SYong Wu #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) 3429746d01SYong Wu #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) 3529746d01SYong Wu #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) 3629746d01SYong Wu #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) 3729746d01SYong Wu #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) 3829746d01SYong Wu #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) 3929746d01SYong Wu #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) 4029746d01SYong Wu 4129746d01SYong Wu /* larb2 VPU0 */ 4229746d01SYong Wu #define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB2_ID, 0) 4329746d01SYong Wu #define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB2_ID, 1) 4429746d01SYong Wu #define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB2_ID, 2) 4529746d01SYong Wu 4629746d01SYong Wu /* larb3 VPU1 */ 4729746d01SYong Wu #define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB3_ID, 0) 4829746d01SYong Wu #define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB3_ID, 1) 4929746d01SYong Wu #define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB3_ID, 2) 5029746d01SYong Wu #define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB3_ID, 3) 5129746d01SYong Wu #define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB3_ID, 4) 5229746d01SYong Wu 5329746d01SYong Wu /* larb4 */ 5429746d01SYong Wu #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB4_ID, 0) 5529746d01SYong Wu #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB4_ID, 1) 5629746d01SYong Wu #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 2) 5729746d01SYong Wu #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB4_ID, 3) 5829746d01SYong Wu #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB4_ID, 4) 5929746d01SYong Wu #define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB4_ID, 5) 6029746d01SYong Wu #define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 6) 6129746d01SYong Wu #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB4_ID, 7) 6229746d01SYong Wu #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 8) 6329746d01SYong Wu #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB4_ID, 9) 6429746d01SYong Wu #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 10) 6529746d01SYong Wu 6629746d01SYong Wu /* larb5 */ 6729746d01SYong Wu #define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB5_ID, 0) 6829746d01SYong Wu #define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB5_ID, 1) 6929746d01SYong Wu #define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB5_ID, 2) 7029746d01SYong Wu #define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB5_ID, 3) 7129746d01SYong Wu #define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB5_ID, 4) 7229746d01SYong Wu #define M4U_PORT_CAM_SMXI MTK_M4U_ID(M4U_LARB5_ID, 5) 7329746d01SYong Wu #define M4U_PORT_CAM_SMXO MTK_M4U_ID(M4U_LARB5_ID, 6) 7429746d01SYong Wu #define M4U_PORT_CAM_WPE0_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 7) 7529746d01SYong Wu #define M4U_PORT_CAM_WPE0_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 8) 7629746d01SYong Wu #define M4U_PORT_CAM_WPE0_WDMA MTK_M4U_ID(M4U_LARB5_ID, 9) 7729746d01SYong Wu #define M4U_PORT_CAM_FDVT_RP MTK_M4U_ID(M4U_LARB5_ID, 10) 7829746d01SYong Wu #define M4U_PORT_CAM_FDVT_WR MTK_M4U_ID(M4U_LARB5_ID, 11) 7929746d01SYong Wu #define M4U_PORT_CAM_FDVT_RB MTK_M4U_ID(M4U_LARB5_ID, 12) 8029746d01SYong Wu #define M4U_PORT_CAM_WPE1_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 13) 8129746d01SYong Wu #define M4U_PORT_CAM_WPE1_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 14) 8229746d01SYong Wu #define M4U_PORT_CAM_WPE1_WDMA MTK_M4U_ID(M4U_LARB5_ID, 15) 8329746d01SYong Wu #define M4U_PORT_CAM_DPE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 16) 8429746d01SYong Wu #define M4U_PORT_CAM_DPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 17) 8529746d01SYong Wu #define M4U_PORT_CAM_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 18) 8629746d01SYong Wu #define M4U_PORT_CAM_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 19) 8729746d01SYong Wu #define M4U_PORT_CAM_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 20) 8829746d01SYong Wu #define M4U_PORT_CAM_RSC_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 21) 8929746d01SYong Wu #define M4U_PORT_CAM_RSC_WDMA MTK_M4U_ID(M4U_LARB5_ID, 22) 9029746d01SYong Wu #define M4U_PORT_CAM_OWE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 23) 9129746d01SYong Wu #define M4U_PORT_CAM_OWE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 24) 9229746d01SYong Wu 9329746d01SYong Wu /* larb6 */ 9429746d01SYong Wu #define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB6_ID, 0) 9529746d01SYong Wu #define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB6_ID, 1) 9629746d01SYong Wu #define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB6_ID, 2) 9729746d01SYong Wu #define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB6_ID, 3) 9829746d01SYong Wu #define M4U_PORT_CAM_LSCI0 MTK_M4U_ID(M4U_LARB6_ID, 4) 9929746d01SYong Wu #define M4U_PORT_CAM_LSCI1 MTK_M4U_ID(M4U_LARB6_ID, 5) 10029746d01SYong Wu #define M4U_PORT_CAM_PDO MTK_M4U_ID(M4U_LARB6_ID, 6) 10129746d01SYong Wu #define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB6_ID, 7) 10229746d01SYong Wu #define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB6_ID, 8) 10329746d01SYong Wu #define M4U_PORT_CAM_CAM_RSSO_A MTK_M4U_ID(M4U_LARB6_ID, 9) 10429746d01SYong Wu #define M4U_PORT_CAM_UFEO MTK_M4U_ID(M4U_LARB6_ID, 10) 10529746d01SYong Wu #define M4U_PORT_CAM_SOCO MTK_M4U_ID(M4U_LARB6_ID, 11) 10629746d01SYong Wu #define M4U_PORT_CAM_SOC1 MTK_M4U_ID(M4U_LARB6_ID, 12) 10729746d01SYong Wu #define M4U_PORT_CAM_SOC2 MTK_M4U_ID(M4U_LARB6_ID, 13) 10829746d01SYong Wu #define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB6_ID, 14) 10929746d01SYong Wu #define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB6_ID, 15) 11029746d01SYong Wu #define M4U_PORT_CAM_RAWI_A MTK_M4U_ID(M4U_LARB6_ID, 16) 11129746d01SYong Wu #define M4U_PORT_CAM_CCUG MTK_M4U_ID(M4U_LARB6_ID, 17) 11229746d01SYong Wu #define M4U_PORT_CAM_PSO MTK_M4U_ID(M4U_LARB6_ID, 18) 11329746d01SYong Wu #define M4U_PORT_CAM_AFO_1 MTK_M4U_ID(M4U_LARB6_ID, 19) 11429746d01SYong Wu #define M4U_PORT_CAM_LSCI_2 MTK_M4U_ID(M4U_LARB6_ID, 20) 11529746d01SYong Wu #define M4U_PORT_CAM_PDI MTK_M4U_ID(M4U_LARB6_ID, 21) 11629746d01SYong Wu #define M4U_PORT_CAM_FLKO MTK_M4U_ID(M4U_LARB6_ID, 22) 11729746d01SYong Wu #define M4U_PORT_CAM_LMVO MTK_M4U_ID(M4U_LARB6_ID, 23) 11829746d01SYong Wu #define M4U_PORT_CAM_UFGO MTK_M4U_ID(M4U_LARB6_ID, 24) 11929746d01SYong Wu #define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB6_ID, 25) 12029746d01SYong Wu #define M4U_PORT_CAM_SPARE_2 MTK_M4U_ID(M4U_LARB6_ID, 26) 12129746d01SYong Wu #define M4U_PORT_CAM_SPARE_3 MTK_M4U_ID(M4U_LARB6_ID, 27) 12229746d01SYong Wu #define M4U_PORT_CAM_SPARE_4 MTK_M4U_ID(M4U_LARB6_ID, 28) 12329746d01SYong Wu #define M4U_PORT_CAM_SPARE_5 MTK_M4U_ID(M4U_LARB6_ID, 29) 12429746d01SYong Wu #define M4U_PORT_CAM_SPARE_6 MTK_M4U_ID(M4U_LARB6_ID, 30) 12529746d01SYong Wu 12629746d01SYong Wu /* CCU */ 12729746d01SYong Wu #define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB7_ID, 0) 12829746d01SYong Wu #define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB7_ID, 1) 12929746d01SYong Wu 13029746d01SYong Wu #endif 131