1*061dbde2SShawn Guo /* SPDX-License-Identifier: GPL-2.0 */ 2*061dbde2SShawn Guo /* QCM2290 interconnect IDs */ 3*061dbde2SShawn Guo 4*061dbde2SShawn Guo #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCM2290_H 5*061dbde2SShawn Guo #define __DT_BINDINGS_INTERCONNECT_QCOM_QCM2290_H 6*061dbde2SShawn Guo 7*061dbde2SShawn Guo /* BIMC */ 8*061dbde2SShawn Guo #define MASTER_APPSS_PROC 0 9*061dbde2SShawn Guo #define MASTER_SNOC_BIMC_RT 1 10*061dbde2SShawn Guo #define MASTER_SNOC_BIMC_NRT 2 11*061dbde2SShawn Guo #define MASTER_SNOC_BIMC 3 12*061dbde2SShawn Guo #define MASTER_TCU_0 4 13*061dbde2SShawn Guo #define MASTER_GFX3D 5 14*061dbde2SShawn Guo #define SLAVE_EBI1 6 15*061dbde2SShawn Guo #define SLAVE_BIMC_SNOC 7 16*061dbde2SShawn Guo 17*061dbde2SShawn Guo /* CNOC */ 18*061dbde2SShawn Guo #define MASTER_SNOC_CNOC 0 19*061dbde2SShawn Guo #define MASTER_QDSS_DAP 1 20*061dbde2SShawn Guo #define SLAVE_BIMC_CFG 2 21*061dbde2SShawn Guo #define SLAVE_CAMERA_NRT_THROTTLE_CFG 3 22*061dbde2SShawn Guo #define SLAVE_CAMERA_RT_THROTTLE_CFG 4 23*061dbde2SShawn Guo #define SLAVE_CAMERA_CFG 5 24*061dbde2SShawn Guo #define SLAVE_CLK_CTL 6 25*061dbde2SShawn Guo #define SLAVE_CRYPTO_0_CFG 7 26*061dbde2SShawn Guo #define SLAVE_DISPLAY_CFG 8 27*061dbde2SShawn Guo #define SLAVE_DISPLAY_THROTTLE_CFG 9 28*061dbde2SShawn Guo #define SLAVE_GPU_CFG 10 29*061dbde2SShawn Guo #define SLAVE_HWKM 11 30*061dbde2SShawn Guo #define SLAVE_IMEM_CFG 12 31*061dbde2SShawn Guo #define SLAVE_IPA_CFG 13 32*061dbde2SShawn Guo #define SLAVE_LPASS 14 33*061dbde2SShawn Guo #define SLAVE_MESSAGE_RAM 15 34*061dbde2SShawn Guo #define SLAVE_PDM 16 35*061dbde2SShawn Guo #define SLAVE_PIMEM_CFG 17 36*061dbde2SShawn Guo #define SLAVE_PKA_WRAPPER 18 37*061dbde2SShawn Guo #define SLAVE_PMIC_ARB 19 38*061dbde2SShawn Guo #define SLAVE_PRNG 20 39*061dbde2SShawn Guo #define SLAVE_QDSS_CFG 21 40*061dbde2SShawn Guo #define SLAVE_QM_CFG 22 41*061dbde2SShawn Guo #define SLAVE_QM_MPU_CFG 23 42*061dbde2SShawn Guo #define SLAVE_QPIC 24 43*061dbde2SShawn Guo #define SLAVE_QUP_0 25 44*061dbde2SShawn Guo #define SLAVE_SDCC_1 26 45*061dbde2SShawn Guo #define SLAVE_SDCC_2 27 46*061dbde2SShawn Guo #define SLAVE_SNOC_CFG 28 47*061dbde2SShawn Guo #define SLAVE_TCSR 29 48*061dbde2SShawn Guo #define SLAVE_USB3 30 49*061dbde2SShawn Guo #define SLAVE_VENUS_CFG 31 50*061dbde2SShawn Guo #define SLAVE_VENUS_THROTTLE_CFG 32 51*061dbde2SShawn Guo #define SLAVE_VSENSE_CTRL_CFG 33 52*061dbde2SShawn Guo #define SLAVE_SERVICE_CNOC 34 53*061dbde2SShawn Guo 54*061dbde2SShawn Guo /* SNOC */ 55*061dbde2SShawn Guo #define MASTER_CRYPTO_CORE0 0 56*061dbde2SShawn Guo #define MASTER_SNOC_CFG 1 57*061dbde2SShawn Guo #define MASTER_TIC 2 58*061dbde2SShawn Guo #define MASTER_ANOC_SNOC 3 59*061dbde2SShawn Guo #define MASTER_BIMC_SNOC 4 60*061dbde2SShawn Guo #define MASTER_PIMEM 5 61*061dbde2SShawn Guo #define MASTER_QDSS_BAM 6 62*061dbde2SShawn Guo #define MASTER_QUP_0 7 63*061dbde2SShawn Guo #define MASTER_IPA 8 64*061dbde2SShawn Guo #define MASTER_QDSS_ETR 9 65*061dbde2SShawn Guo #define MASTER_SDCC_1 10 66*061dbde2SShawn Guo #define MASTER_SDCC_2 11 67*061dbde2SShawn Guo #define MASTER_QPIC 12 68*061dbde2SShawn Guo #define MASTER_USB3_0 13 69*061dbde2SShawn Guo #define SLAVE_APPSS 14 70*061dbde2SShawn Guo #define SLAVE_SNOC_CNOC 15 71*061dbde2SShawn Guo #define SLAVE_IMEM 16 72*061dbde2SShawn Guo #define SLAVE_PIMEM 17 73*061dbde2SShawn Guo #define SLAVE_SNOC_BIMC 18 74*061dbde2SShawn Guo #define SLAVE_SERVICE_SNOC 19 75*061dbde2SShawn Guo #define SLAVE_QDSS_STM 20 76*061dbde2SShawn Guo #define SLAVE_TCU 21 77*061dbde2SShawn Guo #define SLAVE_ANOC_SNOC 22 78*061dbde2SShawn Guo 79*061dbde2SShawn Guo /* QUP Virtual */ 80*061dbde2SShawn Guo #define MASTER_QUP_CORE_0 0 81*061dbde2SShawn Guo #define SLAVE_QUP_CORE_0 1 82*061dbde2SShawn Guo 83*061dbde2SShawn Guo /* MMNRT Virtual */ 84*061dbde2SShawn Guo #define MASTER_CAMNOC_SF 0 85*061dbde2SShawn Guo #define MASTER_VIDEO_P0 1 86*061dbde2SShawn Guo #define MASTER_VIDEO_PROC 2 87*061dbde2SShawn Guo #define SLAVE_SNOC_BIMC_NRT 3 88*061dbde2SShawn Guo 89*061dbde2SShawn Guo /* MMRT Virtual */ 90*061dbde2SShawn Guo #define MASTER_CAMNOC_HF 0 91*061dbde2SShawn Guo #define MASTER_MDP0 1 92*061dbde2SShawn Guo #define SLAVE_SNOC_BIMC_RT 2 93*061dbde2SShawn Guo 94*061dbde2SShawn Guo #endif 95