1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2ec6b9255SStephen Warren /* 3ec6b9255SStephen Warren * This header provides constants for binding nvidia,tegra186-gpio*. 4ec6b9255SStephen Warren * 5ec6b9255SStephen Warren * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 6ec6b9255SStephen Warren * provide names for this. 7ec6b9255SStephen Warren * 8ec6b9255SStephen Warren * The second cell contains standard flag values specified in gpio.h. 9ec6b9255SStephen Warren */ 10ec6b9255SStephen Warren 11*64a38367SThierry Reding #ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H 12*64a38367SThierry Reding #define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H 13ec6b9255SStephen Warren 14ec6b9255SStephen Warren #include <dt-bindings/gpio/gpio.h> 15ec6b9255SStephen Warren 16ec6b9255SStephen Warren /* GPIOs implemented by main GPIO controller */ 1725fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_A 0 1825fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_B 1 1925fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_C 2 2025fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_D 3 2125fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_E 4 2225fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_F 5 2325fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_G 6 2425fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_H 7 2525fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_I 8 2625fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_J 9 2725fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_K 10 2825fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_L 11 2925fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_M 12 3025fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_N 13 3125fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_O 14 3225fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_P 15 3325fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_Q 16 3425fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_R 17 3525fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_T 18 3625fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_X 19 3725fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_Y 20 3825fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_BB 21 3925fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO_PORT_CC 22 4025fbc9e8SThierry Reding 4125fbc9e8SThierry Reding #define TEGRA186_MAIN_GPIO(port, offset) \ 4225fbc9e8SThierry Reding ((TEGRA186_MAIN_GPIO_PORT_##port * 8) + offset) 4325fbc9e8SThierry Reding 44ec6b9255SStephen Warren /* GPIOs implemented by AON GPIO controller */ 4525fbc9e8SThierry Reding #define TEGRA186_AON_GPIO_PORT_S 0 4625fbc9e8SThierry Reding #define TEGRA186_AON_GPIO_PORT_U 1 4725fbc9e8SThierry Reding #define TEGRA186_AON_GPIO_PORT_V 2 4825fbc9e8SThierry Reding #define TEGRA186_AON_GPIO_PORT_W 3 4925fbc9e8SThierry Reding #define TEGRA186_AON_GPIO_PORT_Z 4 5025fbc9e8SThierry Reding #define TEGRA186_AON_GPIO_PORT_AA 5 5125fbc9e8SThierry Reding #define TEGRA186_AON_GPIO_PORT_EE 6 5225fbc9e8SThierry Reding #define TEGRA186_AON_GPIO_PORT_FF 7 5325fbc9e8SThierry Reding 5425fbc9e8SThierry Reding #define TEGRA186_AON_GPIO(port, offset) \ 5525fbc9e8SThierry Reding ((TEGRA186_AON_GPIO_PORT_##port * 8) + offset) 5625fbc9e8SThierry Reding 57ec6b9255SStephen Warren #endif 58