xref: /openbmc/linux/include/dt-bindings/clock/stih407-clks.h (revision 77deed2bbd64e88b3c31283a6ecf771d637ff161)
11befe7e4SGabriel FERNANDEZ /*
21befe7e4SGabriel FERNANDEZ  * This header provides constants clk index STMicroelectronics
31befe7e4SGabriel FERNANDEZ  * STiH407 SoC.
41befe7e4SGabriel FERNANDEZ  */
51befe7e4SGabriel FERNANDEZ #ifndef _DT_BINDINGS_CLK_STIH407
61befe7e4SGabriel FERNANDEZ #define _DT_BINDINGS_CLK_STIH407
71befe7e4SGabriel FERNANDEZ 
81befe7e4SGabriel FERNANDEZ /* CLOCKGEN C0 */
9*77deed2bSGabriel FERNANDEZ #define CLK_ICN_GPU		0
10*77deed2bSGabriel FERNANDEZ #define CLK_FDMA		1
11*77deed2bSGabriel FERNANDEZ #define CLK_NAND		2
12*77deed2bSGabriel FERNANDEZ #define CLK_HVA			3
13*77deed2bSGabriel FERNANDEZ #define CLK_PROC_STFE		4
14*77deed2bSGabriel FERNANDEZ #define CLK_PROC_TP		5
15*77deed2bSGabriel FERNANDEZ #define CLK_RX_ICN_DMU		6
16*77deed2bSGabriel FERNANDEZ #define CLK_RX_ICN_DISP_0	6
17*77deed2bSGabriel FERNANDEZ #define CLK_RX_ICN_DISP_1	6
18*77deed2bSGabriel FERNANDEZ #define CLK_RX_ICN_HVA		7
19*77deed2bSGabriel FERNANDEZ #define CLK_RX_ICN_TS		7
20*77deed2bSGabriel FERNANDEZ #define CLK_ICN_CPU		8
21*77deed2bSGabriel FERNANDEZ #define CLK_TX_ICN_DMU		9
22*77deed2bSGabriel FERNANDEZ #define CLK_TX_ICN_HVA		9
23*77deed2bSGabriel FERNANDEZ #define CLK_TX_ICN_TS		9
24*77deed2bSGabriel FERNANDEZ #define CLK_ICN_COMPO		9
25*77deed2bSGabriel FERNANDEZ #define CLK_MMC_0		10
26*77deed2bSGabriel FERNANDEZ #define CLK_MMC_1		11
27*77deed2bSGabriel FERNANDEZ #define CLK_JPEGDEC		12
28*77deed2bSGabriel FERNANDEZ #define CLK_ICN_REG		13
29*77deed2bSGabriel FERNANDEZ #define CLK_TRACE_A9		13
30*77deed2bSGabriel FERNANDEZ #define CLK_PTI_STM		13
311befe7e4SGabriel FERNANDEZ #define CLK_EXT2F_A9		13
32*77deed2bSGabriel FERNANDEZ #define CLK_IC_BDISP_0		14
33*77deed2bSGabriel FERNANDEZ #define CLK_IC_BDISP_1		15
34*77deed2bSGabriel FERNANDEZ #define CLK_PP_DMU		16
35*77deed2bSGabriel FERNANDEZ #define CLK_VID_DMU		17
36*77deed2bSGabriel FERNANDEZ #define CLK_DSS_LPC		18
37*77deed2bSGabriel FERNANDEZ #define CLK_ST231_AUD_0		19
38*77deed2bSGabriel FERNANDEZ #define CLK_ST231_GP_0		19
39*77deed2bSGabriel FERNANDEZ #define CLK_ST231_GP_1		20
40*77deed2bSGabriel FERNANDEZ #define CLK_ST231_DMU		21
41*77deed2bSGabriel FERNANDEZ #define CLK_ICN_LMI		22
42*77deed2bSGabriel FERNANDEZ #define CLK_TX_ICN_DISP_0	23
43*77deed2bSGabriel FERNANDEZ #define CLK_TX_ICN_DISP_1	23
44*77deed2bSGabriel FERNANDEZ #define CLK_ICN_SBC		24
45*77deed2bSGabriel FERNANDEZ #define CLK_STFE_FRC2		25
46*77deed2bSGabriel FERNANDEZ #define CLK_ETH_PHY		26
47*77deed2bSGabriel FERNANDEZ #define CLK_ETH_REF_PHYCLK	27
48*77deed2bSGabriel FERNANDEZ #define CLK_FLASH_PROMIP	28
49*77deed2bSGabriel FERNANDEZ #define CLK_MAIN_DISP		29
50*77deed2bSGabriel FERNANDEZ #define CLK_AUX_DISP		30
51*77deed2bSGabriel FERNANDEZ #define CLK_COMPO_DVP		31
521befe7e4SGabriel FERNANDEZ 
53*77deed2bSGabriel FERNANDEZ /* CLOCKGEN D0 */
54*77deed2bSGabriel FERNANDEZ #define CLK_PCM_0		0
55*77deed2bSGabriel FERNANDEZ #define CLK_PCM_1		1
56*77deed2bSGabriel FERNANDEZ #define CLK_PCM_2		2
57*77deed2bSGabriel FERNANDEZ #define CLK_SPDIFF		3
58*77deed2bSGabriel FERNANDEZ 
59*77deed2bSGabriel FERNANDEZ /* CLOCKGEN D2 */
60*77deed2bSGabriel FERNANDEZ #define CLK_PIX_MAIN_DISP	0
61*77deed2bSGabriel FERNANDEZ #define CLK_PIX_PIP		1
62*77deed2bSGabriel FERNANDEZ #define CLK_PIX_GDP1		2
63*77deed2bSGabriel FERNANDEZ #define CLK_PIX_GDP2		3
64*77deed2bSGabriel FERNANDEZ #define CLK_PIX_GDP3		4
65*77deed2bSGabriel FERNANDEZ #define CLK_PIX_GDP4		5
66*77deed2bSGabriel FERNANDEZ #define CLK_PIX_AUX_DISP	6
67*77deed2bSGabriel FERNANDEZ #define CLK_DENC		7
68*77deed2bSGabriel FERNANDEZ #define CLK_PIX_HDDAC		8
69*77deed2bSGabriel FERNANDEZ #define CLK_HDDAC		9
70*77deed2bSGabriel FERNANDEZ #define CLK_SDDAC		10
71*77deed2bSGabriel FERNANDEZ #define CLK_PIX_DVO		11
72*77deed2bSGabriel FERNANDEZ #define CLK_DVO			12
73*77deed2bSGabriel FERNANDEZ #define CLK_PIX_HDMI		13
74*77deed2bSGabriel FERNANDEZ #define CLK_TMDS_HDMI		14
75*77deed2bSGabriel FERNANDEZ #define CLK_REF_HDMIPHY		15
76*77deed2bSGabriel FERNANDEZ 
77*77deed2bSGabriel FERNANDEZ /* CLOCKGEN D3 */
78*77deed2bSGabriel FERNANDEZ #define CLK_STFE_FRC1		0
79*77deed2bSGabriel FERNANDEZ #define CLK_TSOUT_0		1
80*77deed2bSGabriel FERNANDEZ #define CLK_TSOUT_1		2
81*77deed2bSGabriel FERNANDEZ #define CLK_MCHI		3
82*77deed2bSGabriel FERNANDEZ #define CLK_VSENS_COMPO		4
83*77deed2bSGabriel FERNANDEZ #define CLK_FRC1_REMOTE		5
84*77deed2bSGabriel FERNANDEZ #define CLK_LPC_0		6
85*77deed2bSGabriel FERNANDEZ #define CLK_LPC_1		7
861befe7e4SGabriel FERNANDEZ #endif
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