1*8f8ef386SVamsi krishna Lanka /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*8f8ef386SVamsi krishna Lanka /* 3*8f8ef386SVamsi krishna Lanka * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 4*8f8ef386SVamsi krishna Lanka */ 5*8f8ef386SVamsi krishna Lanka 6*8f8ef386SVamsi krishna Lanka #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H 7*8f8ef386SVamsi krishna Lanka #define _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H 8*8f8ef386SVamsi krishna Lanka 9*8f8ef386SVamsi krishna Lanka /* GCC clocks */ 10*8f8ef386SVamsi krishna Lanka #define GPLL0 0 11*8f8ef386SVamsi krishna Lanka #define GPLL0_OUT_EVEN 1 12*8f8ef386SVamsi krishna Lanka #define GCC_AHB_PCIE_LINK_CLK 2 13*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_AHB_CLK 3 14*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP1_I2C_APPS_CLK 4 15*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 5 16*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP1_SPI_APPS_CLK 6 17*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 7 18*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP2_I2C_APPS_CLK 8 19*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 9 20*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP2_SPI_APPS_CLK 10 21*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 11 22*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP3_I2C_APPS_CLK 12 23*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 13 24*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP3_SPI_APPS_CLK 14 25*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 15 26*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP4_I2C_APPS_CLK 16 27*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 17 28*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP4_SPI_APPS_CLK 18 29*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 19 30*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_SLEEP_CLK 20 31*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_UART1_APPS_CLK 21 32*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_UART1_APPS_CLK_SRC 22 33*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_UART2_APPS_CLK 23 34*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_UART2_APPS_CLK_SRC 24 35*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_UART3_APPS_CLK 25 36*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_UART3_APPS_CLK_SRC 26 37*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_UART4_APPS_CLK 27 38*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_UART4_APPS_CLK_SRC 28 39*8f8ef386SVamsi krishna Lanka #define GCC_BOOT_ROM_AHB_CLK 29 40*8f8ef386SVamsi krishna Lanka #define GCC_CPUSS_AHB_CLK 30 41*8f8ef386SVamsi krishna Lanka #define GCC_CPUSS_AHB_CLK_SRC 31 42*8f8ef386SVamsi krishna Lanka #define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 32 43*8f8ef386SVamsi krishna Lanka #define GCC_CPUSS_GNOC_CLK 33 44*8f8ef386SVamsi krishna Lanka #define GCC_GP1_CLK 34 45*8f8ef386SVamsi krishna Lanka #define GCC_GP1_CLK_SRC 35 46*8f8ef386SVamsi krishna Lanka #define GCC_GP2_CLK 36 47*8f8ef386SVamsi krishna Lanka #define GCC_GP2_CLK_SRC 37 48*8f8ef386SVamsi krishna Lanka #define GCC_GP3_CLK 38 49*8f8ef386SVamsi krishna Lanka #define GCC_GP3_CLK_SRC 39 50*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_0_CLKREF_EN 40 51*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_AUX_CLK 41 52*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_AUX_CLK_SRC 42 53*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_AUX_PHY_CLK_SRC 43 54*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_CFG_AHB_CLK 44 55*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_MSTR_AXI_CLK 45 56*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_PIPE_CLK 46 57*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_PIPE_CLK_SRC 47 58*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_RCHNG_PHY_CLK 48 59*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_RCHNG_PHY_CLK_SRC 49 60*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_SLEEP_CLK 50 61*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_SLV_AXI_CLK 51 62*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_SLV_Q2A_AXI_CLK 52 63*8f8ef386SVamsi krishna Lanka #define GCC_PDM2_CLK 53 64*8f8ef386SVamsi krishna Lanka #define GCC_PDM2_CLK_SRC 54 65*8f8ef386SVamsi krishna Lanka #define GCC_PDM_AHB_CLK 55 66*8f8ef386SVamsi krishna Lanka #define GCC_PDM_XO4_CLK 56 67*8f8ef386SVamsi krishna Lanka #define GCC_RX1_USB2_CLKREF_EN 57 68*8f8ef386SVamsi krishna Lanka #define GCC_SDCC1_AHB_CLK 58 69*8f8ef386SVamsi krishna Lanka #define GCC_SDCC1_APPS_CLK 59 70*8f8ef386SVamsi krishna Lanka #define GCC_SDCC1_APPS_CLK_SRC 60 71*8f8ef386SVamsi krishna Lanka #define GCC_SPMI_FETCHER_AHB_CLK 61 72*8f8ef386SVamsi krishna Lanka #define GCC_SPMI_FETCHER_CLK 62 73*8f8ef386SVamsi krishna Lanka #define GCC_SPMI_FETCHER_CLK_SRC 63 74*8f8ef386SVamsi krishna Lanka #define GCC_SYS_NOC_CPUSS_AHB_CLK 64 75*8f8ef386SVamsi krishna Lanka #define GCC_USB30_MASTER_CLK 65 76*8f8ef386SVamsi krishna Lanka #define GCC_USB30_MASTER_CLK_SRC 66 77*8f8ef386SVamsi krishna Lanka #define GCC_USB30_MOCK_UTMI_CLK 67 78*8f8ef386SVamsi krishna Lanka #define GCC_USB30_MOCK_UTMI_CLK_SRC 68 79*8f8ef386SVamsi krishna Lanka #define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 69 80*8f8ef386SVamsi krishna Lanka #define GCC_USB30_MSTR_AXI_CLK 70 81*8f8ef386SVamsi krishna Lanka #define GCC_USB30_SLEEP_CLK 71 82*8f8ef386SVamsi krishna Lanka #define GCC_USB30_SLV_AHB_CLK 72 83*8f8ef386SVamsi krishna Lanka #define GCC_USB3_PHY_AUX_CLK 73 84*8f8ef386SVamsi krishna Lanka #define GCC_USB3_PHY_AUX_CLK_SRC 74 85*8f8ef386SVamsi krishna Lanka #define GCC_USB3_PHY_PIPE_CLK 75 86*8f8ef386SVamsi krishna Lanka #define GCC_USB3_PHY_PIPE_CLK_SRC 76 87*8f8ef386SVamsi krishna Lanka #define GCC_USB3_PRIM_CLKREF_EN 77 88*8f8ef386SVamsi krishna Lanka #define GCC_USB_PHY_CFG_AHB2PHY_CLK 78 89*8f8ef386SVamsi krishna Lanka #define GCC_XO_DIV4_CLK 79 90*8f8ef386SVamsi krishna Lanka #define GCC_XO_PCIE_LINK_CLK 80 91*8f8ef386SVamsi krishna Lanka 92*8f8ef386SVamsi krishna Lanka /* GCC resets */ 93*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP1_BCR 0 94*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP2_BCR 1 95*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP3_BCR 2 96*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_QUP4_BCR 3 97*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_UART1_BCR 4 98*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_UART2_BCR 5 99*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_UART3_BCR 6 100*8f8ef386SVamsi krishna Lanka #define GCC_BLSP1_UART4_BCR 7 101*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_BCR 8 102*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_LINK_DOWN_BCR 9 103*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_NOCSR_COM_PHY_BCR 10 104*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_PHY_BCR 11 105*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_PHY_CFG_AHB_BCR 12 106*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_PHY_COM_BCR 13 107*8f8ef386SVamsi krishna Lanka #define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 14 108*8f8ef386SVamsi krishna Lanka #define GCC_PDM_BCR 15 109*8f8ef386SVamsi krishna Lanka #define GCC_QUSB2PHY_BCR 16 110*8f8ef386SVamsi krishna Lanka #define GCC_SDCC1_BCR 17 111*8f8ef386SVamsi krishna Lanka #define GCC_SPMI_FETCHER_BCR 18 112*8f8ef386SVamsi krishna Lanka #define GCC_TCSR_PCIE_BCR 19 113*8f8ef386SVamsi krishna Lanka #define GCC_USB30_BCR 20 114*8f8ef386SVamsi krishna Lanka #define GCC_USB3_PHY_BCR 21 115*8f8ef386SVamsi krishna Lanka #define GCC_USB3PHY_PHY_BCR 22 116*8f8ef386SVamsi krishna Lanka #define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 117*8f8ef386SVamsi krishna Lanka 118*8f8ef386SVamsi krishna Lanka /* GCC power domains */ 119*8f8ef386SVamsi krishna Lanka #define USB30_GDSC 0 120*8f8ef386SVamsi krishna Lanka #define PCIE_GDSC 1 121*8f8ef386SVamsi krishna Lanka 122*8f8ef386SVamsi krishna Lanka #endif 123