19c92ab61SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 249e28282SJeremy McNicoll /* 349e28282SJeremy McNicoll * Copyright (c) 2016, The Linux Foundation. All rights reserved. 449e28282SJeremy McNicoll */ 549e28282SJeremy McNicoll 649e28282SJeremy McNicoll 749e28282SJeremy McNicoll #ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H 849e28282SJeremy McNicoll #define _DT_BINDINGS_CLK_MSM_GCC_8994_H 949e28282SJeremy McNicoll 1049e28282SJeremy McNicoll #define GPLL0_EARLY 0 1149e28282SJeremy McNicoll #define GPLL0 1 1249e28282SJeremy McNicoll #define GPLL4_EARLY 2 1349e28282SJeremy McNicoll #define GPLL4 3 1449e28282SJeremy McNicoll #define UFS_AXI_CLK_SRC 4 1549e28282SJeremy McNicoll #define USB30_MASTER_CLK_SRC 5 1649e28282SJeremy McNicoll #define BLSP1_QUP1_I2C_APPS_CLK_SRC 6 1749e28282SJeremy McNicoll #define BLSP1_QUP1_SPI_APPS_CLK_SRC 7 1849e28282SJeremy McNicoll #define BLSP1_QUP2_I2C_APPS_CLK_SRC 8 1949e28282SJeremy McNicoll #define BLSP1_QUP2_SPI_APPS_CLK_SRC 9 2049e28282SJeremy McNicoll #define BLSP1_QUP3_I2C_APPS_CLK_SRC 10 2149e28282SJeremy McNicoll #define BLSP1_QUP3_SPI_APPS_CLK_SRC 11 2249e28282SJeremy McNicoll #define BLSP1_QUP4_I2C_APPS_CLK_SRC 12 2349e28282SJeremy McNicoll #define BLSP1_QUP4_SPI_APPS_CLK_SRC 13 2449e28282SJeremy McNicoll #define BLSP1_QUP5_I2C_APPS_CLK_SRC 14 2549e28282SJeremy McNicoll #define BLSP1_QUP5_SPI_APPS_CLK_SRC 15 2649e28282SJeremy McNicoll #define BLSP1_QUP6_I2C_APPS_CLK_SRC 16 2749e28282SJeremy McNicoll #define BLSP1_QUP6_SPI_APPS_CLK_SRC 17 2849e28282SJeremy McNicoll #define BLSP1_UART1_APPS_CLK_SRC 18 2949e28282SJeremy McNicoll #define BLSP1_UART2_APPS_CLK_SRC 19 3049e28282SJeremy McNicoll #define BLSP1_UART3_APPS_CLK_SRC 20 3149e28282SJeremy McNicoll #define BLSP1_UART4_APPS_CLK_SRC 21 3249e28282SJeremy McNicoll #define BLSP1_UART5_APPS_CLK_SRC 22 3349e28282SJeremy McNicoll #define BLSP1_UART6_APPS_CLK_SRC 23 3449e28282SJeremy McNicoll #define BLSP2_QUP1_I2C_APPS_CLK_SRC 24 3549e28282SJeremy McNicoll #define BLSP2_QUP1_SPI_APPS_CLK_SRC 25 3649e28282SJeremy McNicoll #define BLSP2_QUP2_I2C_APPS_CLK_SRC 26 3749e28282SJeremy McNicoll #define BLSP2_QUP2_SPI_APPS_CLK_SRC 27 3849e28282SJeremy McNicoll #define BLSP2_QUP3_I2C_APPS_CLK_SRC 28 3949e28282SJeremy McNicoll #define BLSP2_QUP3_SPI_APPS_CLK_SRC 29 4049e28282SJeremy McNicoll #define BLSP2_QUP4_I2C_APPS_CLK_SRC 30 4149e28282SJeremy McNicoll #define BLSP2_QUP4_SPI_APPS_CLK_SRC 31 4249e28282SJeremy McNicoll #define BLSP2_QUP5_I2C_APPS_CLK_SRC 32 4349e28282SJeremy McNicoll #define BLSP2_QUP5_SPI_APPS_CLK_SRC 33 4449e28282SJeremy McNicoll #define BLSP2_QUP6_I2C_APPS_CLK_SRC 34 4549e28282SJeremy McNicoll #define BLSP2_QUP6_SPI_APPS_CLK_SRC 35 4649e28282SJeremy McNicoll #define BLSP2_UART1_APPS_CLK_SRC 36 4749e28282SJeremy McNicoll #define BLSP2_UART2_APPS_CLK_SRC 37 4849e28282SJeremy McNicoll #define BLSP2_UART3_APPS_CLK_SRC 38 4949e28282SJeremy McNicoll #define BLSP2_UART4_APPS_CLK_SRC 39 5049e28282SJeremy McNicoll #define BLSP2_UART5_APPS_CLK_SRC 40 5149e28282SJeremy McNicoll #define BLSP2_UART6_APPS_CLK_SRC 41 5249e28282SJeremy McNicoll #define GP1_CLK_SRC 42 5349e28282SJeremy McNicoll #define GP2_CLK_SRC 43 5449e28282SJeremy McNicoll #define GP3_CLK_SRC 44 5549e28282SJeremy McNicoll #define PCIE_0_AUX_CLK_SRC 45 5649e28282SJeremy McNicoll #define PCIE_0_PIPE_CLK_SRC 46 5749e28282SJeremy McNicoll #define PCIE_1_AUX_CLK_SRC 47 5849e28282SJeremy McNicoll #define PCIE_1_PIPE_CLK_SRC 48 5949e28282SJeremy McNicoll #define PDM2_CLK_SRC 49 6049e28282SJeremy McNicoll #define SDCC1_APPS_CLK_SRC 50 6149e28282SJeremy McNicoll #define SDCC2_APPS_CLK_SRC 51 6249e28282SJeremy McNicoll #define SDCC3_APPS_CLK_SRC 52 6349e28282SJeremy McNicoll #define SDCC4_APPS_CLK_SRC 53 6449e28282SJeremy McNicoll #define TSIF_REF_CLK_SRC 54 6549e28282SJeremy McNicoll #define USB30_MOCK_UTMI_CLK_SRC 55 6649e28282SJeremy McNicoll #define USB3_PHY_AUX_CLK_SRC 56 6749e28282SJeremy McNicoll #define USB_HS_SYSTEM_CLK_SRC 57 6849e28282SJeremy McNicoll #define GCC_BLSP1_AHB_CLK 58 6949e28282SJeremy McNicoll #define GCC_BLSP1_QUP1_I2C_APPS_CLK 59 7049e28282SJeremy McNicoll #define GCC_BLSP1_QUP1_SPI_APPS_CLK 60 7149e28282SJeremy McNicoll #define GCC_BLSP1_QUP2_I2C_APPS_CLK 61 7249e28282SJeremy McNicoll #define GCC_BLSP1_QUP2_SPI_APPS_CLK 62 7349e28282SJeremy McNicoll #define GCC_BLSP1_QUP3_I2C_APPS_CLK 63 7449e28282SJeremy McNicoll #define GCC_BLSP1_QUP3_SPI_APPS_CLK 64 7549e28282SJeremy McNicoll #define GCC_BLSP1_QUP4_I2C_APPS_CLK 65 7649e28282SJeremy McNicoll #define GCC_BLSP1_QUP4_SPI_APPS_CLK 66 7749e28282SJeremy McNicoll #define GCC_BLSP1_QUP5_I2C_APPS_CLK 67 7849e28282SJeremy McNicoll #define GCC_BLSP1_QUP5_SPI_APPS_CLK 68 7949e28282SJeremy McNicoll #define GCC_BLSP1_QUP6_I2C_APPS_CLK 69 8049e28282SJeremy McNicoll #define GCC_BLSP1_QUP6_SPI_APPS_CLK 70 8149e28282SJeremy McNicoll #define GCC_BLSP1_UART1_APPS_CLK 71 8249e28282SJeremy McNicoll #define GCC_BLSP1_UART2_APPS_CLK 72 8349e28282SJeremy McNicoll #define GCC_BLSP1_UART3_APPS_CLK 73 8449e28282SJeremy McNicoll #define GCC_BLSP1_UART4_APPS_CLK 74 8549e28282SJeremy McNicoll #define GCC_BLSP1_UART5_APPS_CLK 75 8649e28282SJeremy McNicoll #define GCC_BLSP1_UART6_APPS_CLK 76 8749e28282SJeremy McNicoll #define GCC_BLSP2_AHB_CLK 77 8849e28282SJeremy McNicoll #define GCC_BLSP2_QUP1_I2C_APPS_CLK 78 8949e28282SJeremy McNicoll #define GCC_BLSP2_QUP1_SPI_APPS_CLK 79 9049e28282SJeremy McNicoll #define GCC_BLSP2_QUP2_I2C_APPS_CLK 80 9149e28282SJeremy McNicoll #define GCC_BLSP2_QUP2_SPI_APPS_CLK 81 9249e28282SJeremy McNicoll #define GCC_BLSP2_QUP3_I2C_APPS_CLK 82 9349e28282SJeremy McNicoll #define GCC_BLSP2_QUP3_SPI_APPS_CLK 83 9449e28282SJeremy McNicoll #define GCC_BLSP2_QUP4_I2C_APPS_CLK 84 9549e28282SJeremy McNicoll #define GCC_BLSP2_QUP4_SPI_APPS_CLK 85 9649e28282SJeremy McNicoll #define GCC_BLSP2_QUP5_I2C_APPS_CLK 86 9749e28282SJeremy McNicoll #define GCC_BLSP2_QUP5_SPI_APPS_CLK 87 9849e28282SJeremy McNicoll #define GCC_BLSP2_QUP6_I2C_APPS_CLK 88 9949e28282SJeremy McNicoll #define GCC_BLSP2_QUP6_SPI_APPS_CLK 89 10049e28282SJeremy McNicoll #define GCC_BLSP2_UART1_APPS_CLK 90 10149e28282SJeremy McNicoll #define GCC_BLSP2_UART2_APPS_CLK 91 10249e28282SJeremy McNicoll #define GCC_BLSP2_UART3_APPS_CLK 92 10349e28282SJeremy McNicoll #define GCC_BLSP2_UART4_APPS_CLK 93 10449e28282SJeremy McNicoll #define GCC_BLSP2_UART5_APPS_CLK 94 10549e28282SJeremy McNicoll #define GCC_BLSP2_UART6_APPS_CLK 95 10649e28282SJeremy McNicoll #define GCC_GP1_CLK 96 10749e28282SJeremy McNicoll #define GCC_GP2_CLK 97 10849e28282SJeremy McNicoll #define GCC_GP3_CLK 98 10949e28282SJeremy McNicoll #define GCC_PCIE_0_AUX_CLK 99 11049e28282SJeremy McNicoll #define GCC_PCIE_0_PIPE_CLK 100 11149e28282SJeremy McNicoll #define GCC_PCIE_1_AUX_CLK 101 11249e28282SJeremy McNicoll #define GCC_PCIE_1_PIPE_CLK 102 11349e28282SJeremy McNicoll #define GCC_PDM2_CLK 103 11449e28282SJeremy McNicoll #define GCC_SDCC1_APPS_CLK 104 11549e28282SJeremy McNicoll #define GCC_SDCC2_APPS_CLK 105 11649e28282SJeremy McNicoll #define GCC_SDCC3_APPS_CLK 106 11749e28282SJeremy McNicoll #define GCC_SDCC4_APPS_CLK 107 11849e28282SJeremy McNicoll #define GCC_SYS_NOC_UFS_AXI_CLK 108 11949e28282SJeremy McNicoll #define GCC_SYS_NOC_USB3_AXI_CLK 109 12049e28282SJeremy McNicoll #define GCC_TSIF_REF_CLK 110 12149e28282SJeremy McNicoll #define GCC_UFS_AXI_CLK 111 12249e28282SJeremy McNicoll #define GCC_UFS_RX_CFG_CLK 112 12349e28282SJeremy McNicoll #define GCC_UFS_TX_CFG_CLK 113 12449e28282SJeremy McNicoll #define GCC_USB30_MASTER_CLK 114 12549e28282SJeremy McNicoll #define GCC_USB30_MOCK_UTMI_CLK 115 12649e28282SJeremy McNicoll #define GCC_USB3_PHY_AUX_CLK 116 12749e28282SJeremy McNicoll #define GCC_USB_HS_SYSTEM_CLK 117 1286eeaf8ffSJeremy McNicoll #define GCC_SDCC1_AHB_CLK 118 1298c18b41bSKonrad Dybcio #define GCC_LPASS_Q6_AXI_CLK 119 1308c18b41bSKonrad Dybcio #define GCC_MSS_Q6_BIMC_AXI_CLK 120 1318c18b41bSKonrad Dybcio #define GCC_PCIE_0_CFG_AHB_CLK 121 1328c18b41bSKonrad Dybcio #define GCC_PCIE_0_MSTR_AXI_CLK 122 1338c18b41bSKonrad Dybcio #define GCC_PCIE_0_SLV_AXI_CLK 123 1348c18b41bSKonrad Dybcio #define GCC_PCIE_1_CFG_AHB_CLK 124 1358c18b41bSKonrad Dybcio #define GCC_PCIE_1_MSTR_AXI_CLK 125 1368c18b41bSKonrad Dybcio #define GCC_PCIE_1_SLV_AXI_CLK 126 1378c18b41bSKonrad Dybcio #define GCC_PDM_AHB_CLK 127 1388c18b41bSKonrad Dybcio #define GCC_SDCC2_AHB_CLK 128 1398c18b41bSKonrad Dybcio #define GCC_SDCC3_AHB_CLK 129 1408c18b41bSKonrad Dybcio #define GCC_SDCC4_AHB_CLK 130 1418c18b41bSKonrad Dybcio #define GCC_TSIF_AHB_CLK 131 1428c18b41bSKonrad Dybcio #define GCC_UFS_AHB_CLK 132 1438c18b41bSKonrad Dybcio #define GCC_UFS_RX_SYMBOL_0_CLK 133 1448c18b41bSKonrad Dybcio #define GCC_UFS_RX_SYMBOL_1_CLK 134 1458c18b41bSKonrad Dybcio #define GCC_UFS_TX_SYMBOL_0_CLK 135 1468c18b41bSKonrad Dybcio #define GCC_UFS_TX_SYMBOL_1_CLK 136 1478c18b41bSKonrad Dybcio #define GCC_USB2_HS_PHY_SLEEP_CLK 137 1488c18b41bSKonrad Dybcio #define GCC_USB30_SLEEP_CLK 138 1498c18b41bSKonrad Dybcio #define GCC_USB_HS_AHB_CLK 139 1508c18b41bSKonrad Dybcio #define GCC_USB_PHY_CFG_AHB2PHY_CLK 140 15174a33facSKonrad Dybcio #define CONFIG_NOC_CLK_SRC 141 15274a33facSKonrad Dybcio #define PERIPH_NOC_CLK_SRC 142 15374a33facSKonrad Dybcio #define SYSTEM_NOC_CLK_SRC 143 154b8f415c6SKonrad Dybcio #define GPLL0_OUT_MMSSCC 144 155b8f415c6SKonrad Dybcio #define GPLL0_OUT_MSSCC 145 156b8f415c6SKonrad Dybcio #define PCIE_0_PHY_LDO 146 157b8f415c6SKonrad Dybcio #define PCIE_1_PHY_LDO 147 158b8f415c6SKonrad Dybcio #define UFS_PHY_LDO 148 159b8f415c6SKonrad Dybcio #define USB_SS_PHY_LDO 149 160b8f415c6SKonrad Dybcio #define GCC_BOOT_ROM_AHB_CLK 150 161b8f415c6SKonrad Dybcio #define GCC_PRNG_AHB_CLK 151 162b8f415c6SKonrad Dybcio #define GCC_USB3_PHY_PIPE_CLK 152 1638c18b41bSKonrad Dybcio 1648c18b41bSKonrad Dybcio /* GDSCs */ 1658c18b41bSKonrad Dybcio #define PCIE_GDSC 0 1668c18b41bSKonrad Dybcio #define PCIE_0_GDSC 1 1678c18b41bSKonrad Dybcio #define PCIE_1_GDSC 2 1688c18b41bSKonrad Dybcio #define USB30_GDSC 3 1698c18b41bSKonrad Dybcio #define UFS_GDSC 4 1708c18b41bSKonrad Dybcio 1718c18b41bSKonrad Dybcio /* Resets */ 1728c18b41bSKonrad Dybcio #define USB3_PHY_RESET 0 1738c18b41bSKonrad Dybcio #define USB3PHY_PHY_RESET 1 1748c18b41bSKonrad Dybcio #define PCIE_PHY_0_RESET 2 1758c18b41bSKonrad Dybcio #define PCIE_PHY_1_RESET 3 1768c18b41bSKonrad Dybcio #define QUSB2_PHY_RESET 4 177*a888dc4cSKonrad Dybcio #define MSS_RESET 5 17849e28282SJeremy McNicoll 17949e28282SJeremy McNicoll #endif 180