1d33faa9eSStephen Boyd /* 2d33faa9eSStephen Boyd * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3d33faa9eSStephen Boyd * 4d33faa9eSStephen Boyd * This software is licensed under the terms of the GNU General Public 5d33faa9eSStephen Boyd * License version 2, as published by the Free Software Foundation, and 6d33faa9eSStephen Boyd * may be copied, distributed, and modified under those terms. 7d33faa9eSStephen Boyd * 8d33faa9eSStephen Boyd * This program is distributed in the hope that it will be useful, 9d33faa9eSStephen Boyd * but WITHOUT ANY WARRANTY; without even the implied warranty of 10d33faa9eSStephen Boyd * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11d33faa9eSStephen Boyd * GNU General Public License for more details. 12d33faa9eSStephen Boyd */ 13d33faa9eSStephen Boyd 14d33faa9eSStephen Boyd #ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H 15d33faa9eSStephen Boyd #define _DT_BINDINGS_CLK_MSM_GCC_8974_H 16d33faa9eSStephen Boyd 17d33faa9eSStephen Boyd #define GPLL0 0 18d33faa9eSStephen Boyd #define GPLL0_VOTE 1 19d33faa9eSStephen Boyd #define CONFIG_NOC_CLK_SRC 2 20d33faa9eSStephen Boyd #define GPLL2 3 21d33faa9eSStephen Boyd #define GPLL2_VOTE 4 22d33faa9eSStephen Boyd #define GPLL3 5 23d33faa9eSStephen Boyd #define GPLL3_VOTE 6 24d33faa9eSStephen Boyd #define PERIPH_NOC_CLK_SRC 7 25d33faa9eSStephen Boyd #define BLSP_UART_SIM_CLK_SRC 8 26d33faa9eSStephen Boyd #define QDSS_TSCTR_CLK_SRC 9 27d33faa9eSStephen Boyd #define BIMC_DDR_CLK_SRC 10 28d33faa9eSStephen Boyd #define SYSTEM_NOC_CLK_SRC 11 29d33faa9eSStephen Boyd #define GPLL1 12 30d33faa9eSStephen Boyd #define GPLL1_VOTE 13 31d33faa9eSStephen Boyd #define RPM_CLK_SRC 14 32d33faa9eSStephen Boyd #define GCC_BIMC_CLK 15 33d33faa9eSStephen Boyd #define BIMC_DDR_CPLL0_ROOT_CLK_SRC 16 34d33faa9eSStephen Boyd #define KPSS_AHB_CLK_SRC 17 35d33faa9eSStephen Boyd #define QDSS_AT_CLK_SRC 18 36d33faa9eSStephen Boyd #define USB30_MASTER_CLK_SRC 19 37d33faa9eSStephen Boyd #define BIMC_DDR_CPLL1_ROOT_CLK_SRC 20 38d33faa9eSStephen Boyd #define QDSS_STM_CLK_SRC 21 39d33faa9eSStephen Boyd #define ACC_CLK_SRC 22 40d33faa9eSStephen Boyd #define SEC_CTRL_CLK_SRC 23 41d33faa9eSStephen Boyd #define BLSP1_QUP1_I2C_APPS_CLK_SRC 24 42d33faa9eSStephen Boyd #define BLSP1_QUP1_SPI_APPS_CLK_SRC 25 43d33faa9eSStephen Boyd #define BLSP1_QUP2_I2C_APPS_CLK_SRC 26 44d33faa9eSStephen Boyd #define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 45d33faa9eSStephen Boyd #define BLSP1_QUP3_I2C_APPS_CLK_SRC 28 46d33faa9eSStephen Boyd #define BLSP1_QUP3_SPI_APPS_CLK_SRC 29 47d33faa9eSStephen Boyd #define BLSP1_QUP4_I2C_APPS_CLK_SRC 30 48d33faa9eSStephen Boyd #define BLSP1_QUP4_SPI_APPS_CLK_SRC 31 49d33faa9eSStephen Boyd #define BLSP1_QUP5_I2C_APPS_CLK_SRC 32 50d33faa9eSStephen Boyd #define BLSP1_QUP5_SPI_APPS_CLK_SRC 33 51d33faa9eSStephen Boyd #define BLSP1_QUP6_I2C_APPS_CLK_SRC 34 52d33faa9eSStephen Boyd #define BLSP1_QUP6_SPI_APPS_CLK_SRC 35 53d33faa9eSStephen Boyd #define BLSP1_UART1_APPS_CLK_SRC 36 54d33faa9eSStephen Boyd #define BLSP1_UART2_APPS_CLK_SRC 37 55d33faa9eSStephen Boyd #define BLSP1_UART3_APPS_CLK_SRC 38 56d33faa9eSStephen Boyd #define BLSP1_UART4_APPS_CLK_SRC 39 57d33faa9eSStephen Boyd #define BLSP1_UART5_APPS_CLK_SRC 40 58d33faa9eSStephen Boyd #define BLSP1_UART6_APPS_CLK_SRC 41 59d33faa9eSStephen Boyd #define BLSP2_QUP1_I2C_APPS_CLK_SRC 42 60d33faa9eSStephen Boyd #define BLSP2_QUP1_SPI_APPS_CLK_SRC 43 61d33faa9eSStephen Boyd #define BLSP2_QUP2_I2C_APPS_CLK_SRC 44 62d33faa9eSStephen Boyd #define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 63d33faa9eSStephen Boyd #define BLSP2_QUP3_I2C_APPS_CLK_SRC 46 64d33faa9eSStephen Boyd #define BLSP2_QUP3_SPI_APPS_CLK_SRC 47 65d33faa9eSStephen Boyd #define BLSP2_QUP4_I2C_APPS_CLK_SRC 48 66d33faa9eSStephen Boyd #define BLSP2_QUP4_SPI_APPS_CLK_SRC 49 67d33faa9eSStephen Boyd #define BLSP2_QUP5_I2C_APPS_CLK_SRC 50 68d33faa9eSStephen Boyd #define BLSP2_QUP5_SPI_APPS_CLK_SRC 51 69d33faa9eSStephen Boyd #define BLSP2_QUP6_I2C_APPS_CLK_SRC 52 70d33faa9eSStephen Boyd #define BLSP2_QUP6_SPI_APPS_CLK_SRC 53 71d33faa9eSStephen Boyd #define BLSP2_UART1_APPS_CLK_SRC 54 72d33faa9eSStephen Boyd #define BLSP2_UART2_APPS_CLK_SRC 55 73d33faa9eSStephen Boyd #define BLSP2_UART3_APPS_CLK_SRC 56 74d33faa9eSStephen Boyd #define BLSP2_UART4_APPS_CLK_SRC 57 75d33faa9eSStephen Boyd #define BLSP2_UART5_APPS_CLK_SRC 58 76d33faa9eSStephen Boyd #define BLSP2_UART6_APPS_CLK_SRC 59 77d33faa9eSStephen Boyd #define CE1_CLK_SRC 60 78d33faa9eSStephen Boyd #define CE2_CLK_SRC 61 79d33faa9eSStephen Boyd #define GP1_CLK_SRC 62 80d33faa9eSStephen Boyd #define GP2_CLK_SRC 63 81d33faa9eSStephen Boyd #define GP3_CLK_SRC 64 82d33faa9eSStephen Boyd #define PDM2_CLK_SRC 65 83d33faa9eSStephen Boyd #define QDSS_TRACECLKIN_CLK_SRC 66 84d33faa9eSStephen Boyd #define RBCPR_CLK_SRC 67 85d33faa9eSStephen Boyd #define SDCC1_APPS_CLK_SRC 68 86d33faa9eSStephen Boyd #define SDCC2_APPS_CLK_SRC 69 87d33faa9eSStephen Boyd #define SDCC3_APPS_CLK_SRC 70 88d33faa9eSStephen Boyd #define SDCC4_APPS_CLK_SRC 71 89d33faa9eSStephen Boyd #define SPMI_AHB_CLK_SRC 72 90d33faa9eSStephen Boyd #define SPMI_SER_CLK_SRC 73 91d33faa9eSStephen Boyd #define TSIF_REF_CLK_SRC 74 92d33faa9eSStephen Boyd #define USB30_MOCK_UTMI_CLK_SRC 75 93d33faa9eSStephen Boyd #define USB_HS_SYSTEM_CLK_SRC 76 94d33faa9eSStephen Boyd #define USB_HSIC_CLK_SRC 77 95d33faa9eSStephen Boyd #define USB_HSIC_IO_CAL_CLK_SRC 78 96d33faa9eSStephen Boyd #define USB_HSIC_SYSTEM_CLK_SRC 79 97d33faa9eSStephen Boyd #define GCC_BAM_DMA_AHB_CLK 80 98d33faa9eSStephen Boyd #define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 81 99d33faa9eSStephen Boyd #define GCC_BIMC_CFG_AHB_CLK 82 100d33faa9eSStephen Boyd #define GCC_BIMC_KPSS_AXI_CLK 83 101d33faa9eSStephen Boyd #define GCC_BIMC_SLEEP_CLK 84 102d33faa9eSStephen Boyd #define GCC_BIMC_SYSNOC_AXI_CLK 85 103d33faa9eSStephen Boyd #define GCC_BIMC_XO_CLK 86 104d33faa9eSStephen Boyd #define GCC_BLSP1_AHB_CLK 87 105d33faa9eSStephen Boyd #define GCC_BLSP1_SLEEP_CLK 88 106d33faa9eSStephen Boyd #define GCC_BLSP1_QUP1_I2C_APPS_CLK 89 107d33faa9eSStephen Boyd #define GCC_BLSP1_QUP1_SPI_APPS_CLK 90 108d33faa9eSStephen Boyd #define GCC_BLSP1_QUP2_I2C_APPS_CLK 91 109d33faa9eSStephen Boyd #define GCC_BLSP1_QUP2_SPI_APPS_CLK 92 110d33faa9eSStephen Boyd #define GCC_BLSP1_QUP3_I2C_APPS_CLK 93 111d33faa9eSStephen Boyd #define GCC_BLSP1_QUP3_SPI_APPS_CLK 94 112d33faa9eSStephen Boyd #define GCC_BLSP1_QUP4_I2C_APPS_CLK 95 113d33faa9eSStephen Boyd #define GCC_BLSP1_QUP4_SPI_APPS_CLK 96 114d33faa9eSStephen Boyd #define GCC_BLSP1_QUP5_I2C_APPS_CLK 97 115d33faa9eSStephen Boyd #define GCC_BLSP1_QUP5_SPI_APPS_CLK 98 116d33faa9eSStephen Boyd #define GCC_BLSP1_QUP6_I2C_APPS_CLK 99 117d33faa9eSStephen Boyd #define GCC_BLSP1_QUP6_SPI_APPS_CLK 100 118d33faa9eSStephen Boyd #define GCC_BLSP1_UART1_APPS_CLK 101 119d33faa9eSStephen Boyd #define GCC_BLSP1_UART1_SIM_CLK 102 120d33faa9eSStephen Boyd #define GCC_BLSP1_UART2_APPS_CLK 103 121d33faa9eSStephen Boyd #define GCC_BLSP1_UART2_SIM_CLK 104 122d33faa9eSStephen Boyd #define GCC_BLSP1_UART3_APPS_CLK 105 123d33faa9eSStephen Boyd #define GCC_BLSP1_UART3_SIM_CLK 106 124d33faa9eSStephen Boyd #define GCC_BLSP1_UART4_APPS_CLK 107 125d33faa9eSStephen Boyd #define GCC_BLSP1_UART4_SIM_CLK 108 126d33faa9eSStephen Boyd #define GCC_BLSP1_UART5_APPS_CLK 109 127d33faa9eSStephen Boyd #define GCC_BLSP1_UART5_SIM_CLK 110 128d33faa9eSStephen Boyd #define GCC_BLSP1_UART6_APPS_CLK 111 129d33faa9eSStephen Boyd #define GCC_BLSP1_UART6_SIM_CLK 112 130d33faa9eSStephen Boyd #define GCC_BLSP2_AHB_CLK 113 131d33faa9eSStephen Boyd #define GCC_BLSP2_SLEEP_CLK 114 132d33faa9eSStephen Boyd #define GCC_BLSP2_QUP1_I2C_APPS_CLK 115 133d33faa9eSStephen Boyd #define GCC_BLSP2_QUP1_SPI_APPS_CLK 116 134d33faa9eSStephen Boyd #define GCC_BLSP2_QUP2_I2C_APPS_CLK 117 135d33faa9eSStephen Boyd #define GCC_BLSP2_QUP2_SPI_APPS_CLK 118 136d33faa9eSStephen Boyd #define GCC_BLSP2_QUP3_I2C_APPS_CLK 119 137d33faa9eSStephen Boyd #define GCC_BLSP2_QUP3_SPI_APPS_CLK 120 138d33faa9eSStephen Boyd #define GCC_BLSP2_QUP4_I2C_APPS_CLK 121 139d33faa9eSStephen Boyd #define GCC_BLSP2_QUP4_SPI_APPS_CLK 122 140d33faa9eSStephen Boyd #define GCC_BLSP2_QUP5_I2C_APPS_CLK 123 141d33faa9eSStephen Boyd #define GCC_BLSP2_QUP5_SPI_APPS_CLK 124 142d33faa9eSStephen Boyd #define GCC_BLSP2_QUP6_I2C_APPS_CLK 125 143d33faa9eSStephen Boyd #define GCC_BLSP2_QUP6_SPI_APPS_CLK 126 144d33faa9eSStephen Boyd #define GCC_BLSP2_UART1_APPS_CLK 127 145d33faa9eSStephen Boyd #define GCC_BLSP2_UART1_SIM_CLK 128 146d33faa9eSStephen Boyd #define GCC_BLSP2_UART2_APPS_CLK 129 147d33faa9eSStephen Boyd #define GCC_BLSP2_UART2_SIM_CLK 130 148d33faa9eSStephen Boyd #define GCC_BLSP2_UART3_APPS_CLK 131 149d33faa9eSStephen Boyd #define GCC_BLSP2_UART3_SIM_CLK 132 150d33faa9eSStephen Boyd #define GCC_BLSP2_UART4_APPS_CLK 133 151d33faa9eSStephen Boyd #define GCC_BLSP2_UART4_SIM_CLK 134 152d33faa9eSStephen Boyd #define GCC_BLSP2_UART5_APPS_CLK 135 153d33faa9eSStephen Boyd #define GCC_BLSP2_UART5_SIM_CLK 136 154d33faa9eSStephen Boyd #define GCC_BLSP2_UART6_APPS_CLK 137 155d33faa9eSStephen Boyd #define GCC_BLSP2_UART6_SIM_CLK 138 156d33faa9eSStephen Boyd #define GCC_BOOT_ROM_AHB_CLK 139 157d33faa9eSStephen Boyd #define GCC_CE1_AHB_CLK 140 158d33faa9eSStephen Boyd #define GCC_CE1_AXI_CLK 141 159d33faa9eSStephen Boyd #define GCC_CE1_CLK 142 160d33faa9eSStephen Boyd #define GCC_CE2_AHB_CLK 143 161d33faa9eSStephen Boyd #define GCC_CE2_AXI_CLK 144 162d33faa9eSStephen Boyd #define GCC_CE2_CLK 145 163d33faa9eSStephen Boyd #define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 146 164d33faa9eSStephen Boyd #define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 147 165d33faa9eSStephen Boyd #define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 148 166d33faa9eSStephen Boyd #define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 149 167d33faa9eSStephen Boyd #define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 150 168d33faa9eSStephen Boyd #define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 151 169d33faa9eSStephen Boyd #define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 152 170d33faa9eSStephen Boyd #define GCC_CFG_NOC_AHB_CLK 153 171d33faa9eSStephen Boyd #define GCC_CFG_NOC_DDR_CFG_CLK 154 172d33faa9eSStephen Boyd #define GCC_CFG_NOC_RPM_AHB_CLK 155 173d33faa9eSStephen Boyd #define GCC_BIMC_DDR_CPLL0_CLK 156 174d33faa9eSStephen Boyd #define GCC_BIMC_DDR_CPLL1_CLK 157 175d33faa9eSStephen Boyd #define GCC_DDR_DIM_CFG_CLK 158 176d33faa9eSStephen Boyd #define GCC_DDR_DIM_SLEEP_CLK 159 177d33faa9eSStephen Boyd #define GCC_DEHR_CLK 160 178d33faa9eSStephen Boyd #define GCC_AHB_CLK 161 179d33faa9eSStephen Boyd #define GCC_IM_SLEEP_CLK 162 180d33faa9eSStephen Boyd #define GCC_XO_CLK 163 181d33faa9eSStephen Boyd #define GCC_XO_DIV4_CLK 164 182d33faa9eSStephen Boyd #define GCC_GP1_CLK 165 183d33faa9eSStephen Boyd #define GCC_GP2_CLK 166 184d33faa9eSStephen Boyd #define GCC_GP3_CLK 167 185d33faa9eSStephen Boyd #define GCC_IMEM_AXI_CLK 168 186d33faa9eSStephen Boyd #define GCC_IMEM_CFG_AHB_CLK 169 187d33faa9eSStephen Boyd #define GCC_KPSS_AHB_CLK 170 188d33faa9eSStephen Boyd #define GCC_KPSS_AXI_CLK 171 189d33faa9eSStephen Boyd #define GCC_LPASS_Q6_AXI_CLK 172 190d33faa9eSStephen Boyd #define GCC_MMSS_NOC_AT_CLK 173 191d33faa9eSStephen Boyd #define GCC_MMSS_NOC_CFG_AHB_CLK 174 192d33faa9eSStephen Boyd #define GCC_OCMEM_NOC_CFG_AHB_CLK 175 193d33faa9eSStephen Boyd #define GCC_OCMEM_SYS_NOC_AXI_CLK 176 194d33faa9eSStephen Boyd #define GCC_MPM_AHB_CLK 177 195d33faa9eSStephen Boyd #define GCC_MSG_RAM_AHB_CLK 178 196d33faa9eSStephen Boyd #define GCC_MSS_CFG_AHB_CLK 179 197d33faa9eSStephen Boyd #define GCC_MSS_Q6_BIMC_AXI_CLK 180 198d33faa9eSStephen Boyd #define GCC_NOC_CONF_XPU_AHB_CLK 181 199d33faa9eSStephen Boyd #define GCC_PDM2_CLK 182 200d33faa9eSStephen Boyd #define GCC_PDM_AHB_CLK 183 201d33faa9eSStephen Boyd #define GCC_PDM_XO4_CLK 184 202d33faa9eSStephen Boyd #define GCC_PERIPH_NOC_AHB_CLK 185 203d33faa9eSStephen Boyd #define GCC_PERIPH_NOC_AT_CLK 186 204d33faa9eSStephen Boyd #define GCC_PERIPH_NOC_CFG_AHB_CLK 187 205d33faa9eSStephen Boyd #define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 188 206d33faa9eSStephen Boyd #define GCC_PERIPH_XPU_AHB_CLK 189 207d33faa9eSStephen Boyd #define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 190 208d33faa9eSStephen Boyd #define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 191 209d33faa9eSStephen Boyd #define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 192 210d33faa9eSStephen Boyd #define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 193 211d33faa9eSStephen Boyd #define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 194 212d33faa9eSStephen Boyd #define GCC_PRNG_AHB_CLK 195 213d33faa9eSStephen Boyd #define GCC_QDSS_AT_CLK 196 214d33faa9eSStephen Boyd #define GCC_QDSS_CFG_AHB_CLK 197 215d33faa9eSStephen Boyd #define GCC_QDSS_DAP_AHB_CLK 198 216d33faa9eSStephen Boyd #define GCC_QDSS_DAP_CLK 199 217d33faa9eSStephen Boyd #define GCC_QDSS_ETR_USB_CLK 200 218d33faa9eSStephen Boyd #define GCC_QDSS_STM_CLK 201 219d33faa9eSStephen Boyd #define GCC_QDSS_TRACECLKIN_CLK 202 220d33faa9eSStephen Boyd #define GCC_QDSS_TSCTR_DIV16_CLK 203 221d33faa9eSStephen Boyd #define GCC_QDSS_TSCTR_DIV2_CLK 204 222d33faa9eSStephen Boyd #define GCC_QDSS_TSCTR_DIV3_CLK 205 223d33faa9eSStephen Boyd #define GCC_QDSS_TSCTR_DIV4_CLK 206 224d33faa9eSStephen Boyd #define GCC_QDSS_TSCTR_DIV8_CLK 207 225d33faa9eSStephen Boyd #define GCC_QDSS_RBCPR_XPU_AHB_CLK 208 226d33faa9eSStephen Boyd #define GCC_RBCPR_AHB_CLK 209 227d33faa9eSStephen Boyd #define GCC_RBCPR_CLK 210 228d33faa9eSStephen Boyd #define GCC_RPM_BUS_AHB_CLK 211 229d33faa9eSStephen Boyd #define GCC_RPM_PROC_HCLK 212 230d33faa9eSStephen Boyd #define GCC_RPM_SLEEP_CLK 213 231d33faa9eSStephen Boyd #define GCC_RPM_TIMER_CLK 214 232d33faa9eSStephen Boyd #define GCC_SDCC1_AHB_CLK 215 233d33faa9eSStephen Boyd #define GCC_SDCC1_APPS_CLK 216 234d33faa9eSStephen Boyd #define GCC_SDCC1_INACTIVITY_TIMERS_CLK 217 235d33faa9eSStephen Boyd #define GCC_SDCC2_AHB_CLK 218 236d33faa9eSStephen Boyd #define GCC_SDCC2_APPS_CLK 219 237d33faa9eSStephen Boyd #define GCC_SDCC2_INACTIVITY_TIMERS_CLK 220 238d33faa9eSStephen Boyd #define GCC_SDCC3_AHB_CLK 221 239d33faa9eSStephen Boyd #define GCC_SDCC3_APPS_CLK 222 240d33faa9eSStephen Boyd #define GCC_SDCC3_INACTIVITY_TIMERS_CLK 223 241d33faa9eSStephen Boyd #define GCC_SDCC4_AHB_CLK 224 242d33faa9eSStephen Boyd #define GCC_SDCC4_APPS_CLK 225 243d33faa9eSStephen Boyd #define GCC_SDCC4_INACTIVITY_TIMERS_CLK 226 244d33faa9eSStephen Boyd #define GCC_SEC_CTRL_ACC_CLK 227 245d33faa9eSStephen Boyd #define GCC_SEC_CTRL_AHB_CLK 228 246d33faa9eSStephen Boyd #define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 229 247d33faa9eSStephen Boyd #define GCC_SEC_CTRL_CLK 230 248d33faa9eSStephen Boyd #define GCC_SEC_CTRL_SENSE_CLK 231 249d33faa9eSStephen Boyd #define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 232 250d33faa9eSStephen Boyd #define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 233 251d33faa9eSStephen Boyd #define GCC_SPDM_BIMC_CY_CLK 234 252d33faa9eSStephen Boyd #define GCC_SPDM_CFG_AHB_CLK 235 253d33faa9eSStephen Boyd #define GCC_SPDM_DEBUG_CY_CLK 236 254d33faa9eSStephen Boyd #define GCC_SPDM_FF_CLK 237 255d33faa9eSStephen Boyd #define GCC_SPDM_MSTR_AHB_CLK 238 256d33faa9eSStephen Boyd #define GCC_SPDM_PNOC_CY_CLK 239 257d33faa9eSStephen Boyd #define GCC_SPDM_RPM_CY_CLK 240 258d33faa9eSStephen Boyd #define GCC_SPDM_SNOC_CY_CLK 241 259d33faa9eSStephen Boyd #define GCC_SPMI_AHB_CLK 242 260d33faa9eSStephen Boyd #define GCC_SPMI_CNOC_AHB_CLK 243 261d33faa9eSStephen Boyd #define GCC_SPMI_SER_CLK 244 262d33faa9eSStephen Boyd #define GCC_SNOC_CNOC_AHB_CLK 245 263d33faa9eSStephen Boyd #define GCC_SNOC_PNOC_AHB_CLK 246 264d33faa9eSStephen Boyd #define GCC_SYS_NOC_AT_CLK 247 265d33faa9eSStephen Boyd #define GCC_SYS_NOC_AXI_CLK 248 266d33faa9eSStephen Boyd #define GCC_SYS_NOC_KPSS_AHB_CLK 249 267d33faa9eSStephen Boyd #define GCC_SYS_NOC_QDSS_STM_AXI_CLK 250 268d33faa9eSStephen Boyd #define GCC_SYS_NOC_USB3_AXI_CLK 251 269d33faa9eSStephen Boyd #define GCC_TCSR_AHB_CLK 252 270d33faa9eSStephen Boyd #define GCC_TLMM_AHB_CLK 253 271d33faa9eSStephen Boyd #define GCC_TLMM_CLK 254 272d33faa9eSStephen Boyd #define GCC_TSIF_AHB_CLK 255 273d33faa9eSStephen Boyd #define GCC_TSIF_INACTIVITY_TIMERS_CLK 256 274d33faa9eSStephen Boyd #define GCC_TSIF_REF_CLK 257 275d33faa9eSStephen Boyd #define GCC_USB2A_PHY_SLEEP_CLK 258 276d33faa9eSStephen Boyd #define GCC_USB2B_PHY_SLEEP_CLK 259 277d33faa9eSStephen Boyd #define GCC_USB30_MASTER_CLK 260 278d33faa9eSStephen Boyd #define GCC_USB30_MOCK_UTMI_CLK 261 279d33faa9eSStephen Boyd #define GCC_USB30_SLEEP_CLK 262 280d33faa9eSStephen Boyd #define GCC_USB_HS_AHB_CLK 263 281d33faa9eSStephen Boyd #define GCC_USB_HS_INACTIVITY_TIMERS_CLK 264 282d33faa9eSStephen Boyd #define GCC_USB_HS_SYSTEM_CLK 265 283d33faa9eSStephen Boyd #define GCC_USB_HSIC_AHB_CLK 266 284d33faa9eSStephen Boyd #define GCC_USB_HSIC_CLK 267 285d33faa9eSStephen Boyd #define GCC_USB_HSIC_IO_CAL_CLK 268 286d33faa9eSStephen Boyd #define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 269 287d33faa9eSStephen Boyd #define GCC_USB_HSIC_SYSTEM_CLK 270 288d33faa9eSStephen Boyd #define GCC_WCSS_GPLL1_CLK_SRC 271 289d33faa9eSStephen Boyd #define GCC_MMSS_GPLL0_CLK_SRC 272 290d33faa9eSStephen Boyd #define GCC_LPASS_GPLL0_CLK_SRC 273 291d33faa9eSStephen Boyd #define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA 274 292d33faa9eSStephen Boyd #define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA 275 293d33faa9eSStephen Boyd #define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA 276 294d33faa9eSStephen Boyd #define GCC_IMEM_AXI_CLK_SLEEP_ENA 277 295d33faa9eSStephen Boyd #define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA 278 296d33faa9eSStephen Boyd #define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA 279 297d33faa9eSStephen Boyd #define GCC_KPSS_AHB_CLK_SLEEP_ENA 280 298d33faa9eSStephen Boyd #define GCC_KPSS_AXI_CLK_SLEEP_ENA 281 299d33faa9eSStephen Boyd #define GCC_MPM_AHB_CLK_SLEEP_ENA 282 300d33faa9eSStephen Boyd #define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA 283 301d33faa9eSStephen Boyd #define GCC_BLSP1_AHB_CLK_SLEEP_ENA 284 302d33faa9eSStephen Boyd #define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA 285 303d33faa9eSStephen Boyd #define GCC_BLSP2_AHB_CLK_SLEEP_ENA 286 304d33faa9eSStephen Boyd #define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA 287 305d33faa9eSStephen Boyd #define GCC_PRNG_AHB_CLK_SLEEP_ENA 288 306d33faa9eSStephen Boyd #define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA 289 307d33faa9eSStephen Boyd #define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA 290 308d33faa9eSStephen Boyd #define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA 291 309d33faa9eSStephen Boyd #define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA 292 310d33faa9eSStephen Boyd #define GCC_TLMM_AHB_CLK_SLEEP_ENA 293 311d33faa9eSStephen Boyd #define GCC_TLMM_CLK_SLEEP_ENA 294 312d33faa9eSStephen Boyd #define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA 295 313d33faa9eSStephen Boyd #define GCC_CE1_CLK_SLEEP_ENA 296 314d33faa9eSStephen Boyd #define GCC_CE1_AXI_CLK_SLEEP_ENA 297 315d33faa9eSStephen Boyd #define GCC_CE1_AHB_CLK_SLEEP_ENA 298 316d33faa9eSStephen Boyd #define GCC_CE2_CLK_SLEEP_ENA 299 317d33faa9eSStephen Boyd #define GCC_CE2_AXI_CLK_SLEEP_ENA 300 318d33faa9eSStephen Boyd #define GCC_CE2_AHB_CLK_SLEEP_ENA 301 319*c685841eSStephen Boyd #define GPLL4 302 320*c685841eSStephen Boyd #define GPLL4_VOTE 303 321*c685841eSStephen Boyd #define GCC_SDCC1_CDCCAL_SLEEP_CLK 304 322*c685841eSStephen Boyd #define GCC_SDCC1_CDCCAL_FF_CLK 305 323d33faa9eSStephen Boyd 324d33faa9eSStephen Boyd #endif 325