1*7046c6b0SManivannan Sadhasivam /* SPDX-License-Identifier: GPL-2.0+ */ 2*7046c6b0SManivannan Sadhasivam /* 3*7046c6b0SManivannan Sadhasivam * Device Tree binding constants for Bitmain BM1880 SoC 4*7046c6b0SManivannan Sadhasivam * 5*7046c6b0SManivannan Sadhasivam * Copyright (c) 2019 Linaro Ltd. 6*7046c6b0SManivannan Sadhasivam */ 7*7046c6b0SManivannan Sadhasivam 8*7046c6b0SManivannan Sadhasivam #ifndef __DT_BINDINGS_CLOCK_BM1880_H 9*7046c6b0SManivannan Sadhasivam #define __DT_BINDINGS_CLOCK_BM1880_H 10*7046c6b0SManivannan Sadhasivam 11*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_OSC 0 12*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_MPLL 1 13*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_SPLL 2 14*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_FPLL 3 15*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_DDRPLL 4 16*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_A53 5 17*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_50M_A53 6 18*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AHB_ROM 7 19*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI_SRAM 8 20*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_DDR_AXI 9 21*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_EFUSE 10 22*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_EFUSE 11 23*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI5_EMMC 12 24*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_EMMC 13 25*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_100K_EMMC 14 26*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI5_SD 15 27*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_SD 16 28*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_100K_SD 17 29*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_500M_ETH0 18 30*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI4_ETH0 19 31*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_500M_ETH1 20 32*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI4_ETH1 21 33*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI1_GDMA 22 34*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_GPIO 23 35*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_GPIO_INTR 24 36*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_GPIO_DB 25 37*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI1_MINER 26 38*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AHB_SF 27 39*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_SDMA_AXI 28 40*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_SDMA_AUD 29 41*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_I2C 30 42*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_WDT 31 43*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_JPEG 32 44*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_JPEG_AXI 33 45*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI5_NF 34 46*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_NF 35 47*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_NF 36 48*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_PWM 37 49*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_0_RV 38 50*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_1_RV 39 51*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_MUX_RV 40 52*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_RV 41 53*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_SPI 42 54*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_TPU_AXI 43 55*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_UART_500M 44 56*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_UART_500M 45 57*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_UART 46 58*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_I2S 47 59*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI4_USB 48 60*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_USB 49 61*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_125M_USB 50 62*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_33K_USB 51 63*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_12M_USB 52 64*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_12M_USB 53 65*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_VIDEO 54 66*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_VIDEO_AXI 55 67*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_VPP_AXI 56 68*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_APB_VPP 57 69*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_0_AXI1 58 70*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_1_AXI1 59 71*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI1 60 72*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI2 61 73*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI3 62 74*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI4 63 75*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI5 64 76*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_0_AXI6 65 77*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_DIV_1_AXI6 66 78*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_MUX_AXI6 67 79*7046c6b0SManivannan Sadhasivam #define BM1880_CLK_AXI6 68 80*7046c6b0SManivannan Sadhasivam #define BM1880_NR_CLKS 69 81*7046c6b0SManivannan Sadhasivam 82*7046c6b0SManivannan Sadhasivam #endif /* __DT_BINDINGS_CLOCK_BM1880_H */ 83