12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
24cfbfa97SStefano Babic /*
34cfbfa97SStefano Babic * (C) Copyright 2008
44cfbfa97SStefano Babic * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
54cfbfa97SStefano Babic *
64cfbfa97SStefano Babic * This driver implements a lcd device for the ILITEK 922x display
74cfbfa97SStefano Babic * controller. The interface to the display is SPI and the display's
84cfbfa97SStefano Babic * memory is cyclically updated over the RGB interface.
94cfbfa97SStefano Babic */
104cfbfa97SStefano Babic
114cfbfa97SStefano Babic #include <linux/fb.h>
124cfbfa97SStefano Babic #include <linux/delay.h>
134cfbfa97SStefano Babic #include <linux/errno.h>
144cfbfa97SStefano Babic #include <linux/init.h>
154cfbfa97SStefano Babic #include <linux/kernel.h>
164cfbfa97SStefano Babic #include <linux/lcd.h>
174cfbfa97SStefano Babic #include <linux/module.h>
184cfbfa97SStefano Babic #include <linux/of.h>
194cfbfa97SStefano Babic #include <linux/slab.h>
204cfbfa97SStefano Babic #include <linux/spi/spi.h>
214cfbfa97SStefano Babic #include <linux/string.h>
224cfbfa97SStefano Babic
234cfbfa97SStefano Babic /* Register offset, see manual section 8.2 */
244cfbfa97SStefano Babic #define REG_START_OSCILLATION 0x00
254cfbfa97SStefano Babic #define REG_DRIVER_CODE_READ 0x00
264cfbfa97SStefano Babic #define REG_DRIVER_OUTPUT_CONTROL 0x01
274cfbfa97SStefano Babic #define REG_LCD_AC_DRIVEING_CONTROL 0x02
284cfbfa97SStefano Babic #define REG_ENTRY_MODE 0x03
294cfbfa97SStefano Babic #define REG_COMPARE_1 0x04
304cfbfa97SStefano Babic #define REG_COMPARE_2 0x05
314cfbfa97SStefano Babic #define REG_DISPLAY_CONTROL_1 0x07
324cfbfa97SStefano Babic #define REG_DISPLAY_CONTROL_2 0x08
334cfbfa97SStefano Babic #define REG_DISPLAY_CONTROL_3 0x09
344cfbfa97SStefano Babic #define REG_FRAME_CYCLE_CONTROL 0x0B
354cfbfa97SStefano Babic #define REG_EXT_INTF_CONTROL 0x0C
364cfbfa97SStefano Babic #define REG_POWER_CONTROL_1 0x10
374cfbfa97SStefano Babic #define REG_POWER_CONTROL_2 0x11
384cfbfa97SStefano Babic #define REG_POWER_CONTROL_3 0x12
394cfbfa97SStefano Babic #define REG_POWER_CONTROL_4 0x13
404cfbfa97SStefano Babic #define REG_RAM_ADDRESS_SET 0x21
414cfbfa97SStefano Babic #define REG_WRITE_DATA_TO_GRAM 0x22
424cfbfa97SStefano Babic #define REG_RAM_WRITE_MASK1 0x23
434cfbfa97SStefano Babic #define REG_RAM_WRITE_MASK2 0x24
444cfbfa97SStefano Babic #define REG_GAMMA_CONTROL_1 0x30
454cfbfa97SStefano Babic #define REG_GAMMA_CONTROL_2 0x31
464cfbfa97SStefano Babic #define REG_GAMMA_CONTROL_3 0x32
474cfbfa97SStefano Babic #define REG_GAMMA_CONTROL_4 0x33
484cfbfa97SStefano Babic #define REG_GAMMA_CONTROL_5 0x34
494cfbfa97SStefano Babic #define REG_GAMMA_CONTROL_6 0x35
504cfbfa97SStefano Babic #define REG_GAMMA_CONTROL_7 0x36
514cfbfa97SStefano Babic #define REG_GAMMA_CONTROL_8 0x37
524cfbfa97SStefano Babic #define REG_GAMMA_CONTROL_9 0x38
534cfbfa97SStefano Babic #define REG_GAMMA_CONTROL_10 0x39
544cfbfa97SStefano Babic #define REG_GATE_SCAN_CONTROL 0x40
554cfbfa97SStefano Babic #define REG_VERT_SCROLL_CONTROL 0x41
564cfbfa97SStefano Babic #define REG_FIRST_SCREEN_DRIVE_POS 0x42
574cfbfa97SStefano Babic #define REG_SECOND_SCREEN_DRIVE_POS 0x43
584cfbfa97SStefano Babic #define REG_RAM_ADDR_POS_H 0x44
594cfbfa97SStefano Babic #define REG_RAM_ADDR_POS_V 0x45
604cfbfa97SStefano Babic #define REG_OSCILLATOR_CONTROL 0x4F
614cfbfa97SStefano Babic #define REG_GPIO 0x60
624cfbfa97SStefano Babic #define REG_OTP_VCM_PROGRAMMING 0x61
634cfbfa97SStefano Babic #define REG_OTP_VCM_STATUS_ENABLE 0x62
644cfbfa97SStefano Babic #define REG_OTP_PROGRAMMING_ID_KEY 0x65
654cfbfa97SStefano Babic
664cfbfa97SStefano Babic /*
674cfbfa97SStefano Babic * maximum frequency for register access
684cfbfa97SStefano Babic * (not for the GRAM access)
694cfbfa97SStefano Babic */
704cfbfa97SStefano Babic #define ILITEK_MAX_FREQ_REG 4000000
714cfbfa97SStefano Babic
724cfbfa97SStefano Babic /*
734cfbfa97SStefano Babic * Device ID as found in the datasheet (supports 9221 and 9222)
744cfbfa97SStefano Babic */
754cfbfa97SStefano Babic #define ILITEK_DEVICE_ID 0x9220
764cfbfa97SStefano Babic #define ILITEK_DEVICE_ID_MASK 0xFFF0
774cfbfa97SStefano Babic
784cfbfa97SStefano Babic /* Last two bits in the START BYTE */
794cfbfa97SStefano Babic #define START_RS_INDEX 0
804cfbfa97SStefano Babic #define START_RS_REG 1
814cfbfa97SStefano Babic #define START_RW_WRITE 0
824cfbfa97SStefano Babic #define START_RW_READ 1
834cfbfa97SStefano Babic
844cfbfa97SStefano Babic /**
854cfbfa97SStefano Babic * START_BYTE(id, rs, rw)
864cfbfa97SStefano Babic *
874cfbfa97SStefano Babic * Set the start byte according to the required operation.
884cfbfa97SStefano Babic * The start byte is defined as:
894cfbfa97SStefano Babic * ----------------------------------
904cfbfa97SStefano Babic * | 0 | 1 | 1 | 1 | 0 | ID | RS | RW |
914cfbfa97SStefano Babic * ----------------------------------
924cfbfa97SStefano Babic * @id: display's id as set by the manufacturer
934cfbfa97SStefano Babic * @rs: operation type bit, one of:
944cfbfa97SStefano Babic * - START_RS_INDEX set the index register
954cfbfa97SStefano Babic * - START_RS_REG write/read registers/GRAM
964cfbfa97SStefano Babic * @rw: read/write operation
974cfbfa97SStefano Babic * - START_RW_WRITE write
984cfbfa97SStefano Babic * - START_RW_READ read
994cfbfa97SStefano Babic */
1004cfbfa97SStefano Babic #define START_BYTE(id, rs, rw) \
1014cfbfa97SStefano Babic (0x70 | (((id) & 0x01) << 2) | (((rs) & 0x01) << 1) | ((rw) & 0x01))
1024cfbfa97SStefano Babic
1034cfbfa97SStefano Babic /**
1044cfbfa97SStefano Babic * CHECK_FREQ_REG(spi_device s, spi_transfer x) - Check the frequency
1054cfbfa97SStefano Babic * for the SPI transfer. According to the datasheet, the controller
1064cfbfa97SStefano Babic * accept higher frequency for the GRAM transfer, but it requires
1074cfbfa97SStefano Babic * lower frequency when the registers are read/written.
1084cfbfa97SStefano Babic * The macro sets the frequency in the spi_transfer structure if
1094cfbfa97SStefano Babic * the frequency exceeds the maximum value.
1100e0428beSLee Jones * @s: pointer to an SPI device
1110e0428beSLee Jones * @x: pointer to the read/write buffer pair
1124cfbfa97SStefano Babic */
1134cfbfa97SStefano Babic #define CHECK_FREQ_REG(s, x) \
1144cfbfa97SStefano Babic do { \
1154cfbfa97SStefano Babic if (s->max_speed_hz > ILITEK_MAX_FREQ_REG) \
1164cfbfa97SStefano Babic ((struct spi_transfer *)x)->speed_hz = \
1174cfbfa97SStefano Babic ILITEK_MAX_FREQ_REG; \
1184cfbfa97SStefano Babic } while (0)
1194cfbfa97SStefano Babic
1204cfbfa97SStefano Babic #define CMD_BUFSIZE 16
1214cfbfa97SStefano Babic
1224cfbfa97SStefano Babic #define POWER_IS_ON(pwr) ((pwr) <= FB_BLANK_NORMAL)
1234cfbfa97SStefano Babic
1244cfbfa97SStefano Babic #define set_tx_byte(b) (tx_invert ? ~(b) : b)
1254cfbfa97SStefano Babic
126ee555c1dSLee Jones /*
1274cfbfa97SStefano Babic * ili922x_id - id as set by manufacturer
1284cfbfa97SStefano Babic */
1294cfbfa97SStefano Babic static int ili922x_id = 1;
1304cfbfa97SStefano Babic module_param(ili922x_id, int, 0);
1314cfbfa97SStefano Babic
1324cfbfa97SStefano Babic static int tx_invert;
1334cfbfa97SStefano Babic module_param(tx_invert, int, 0);
1344cfbfa97SStefano Babic
135ee555c1dSLee Jones /*
1364cfbfa97SStefano Babic * driver's private structure
1374cfbfa97SStefano Babic */
1384cfbfa97SStefano Babic struct ili922x {
1394cfbfa97SStefano Babic struct spi_device *spi;
1404cfbfa97SStefano Babic struct lcd_device *ld;
1414cfbfa97SStefano Babic int power;
1424cfbfa97SStefano Babic };
1434cfbfa97SStefano Babic
1444cfbfa97SStefano Babic /**
1454cfbfa97SStefano Babic * ili922x_read_status - read status register from display
1464cfbfa97SStefano Babic * @spi: spi device
1474cfbfa97SStefano Babic * @rs: output value
1484cfbfa97SStefano Babic */
ili922x_read_status(struct spi_device * spi,u16 * rs)1494cfbfa97SStefano Babic static int ili922x_read_status(struct spi_device *spi, u16 *rs)
1504cfbfa97SStefano Babic {
1514cfbfa97SStefano Babic struct spi_message msg;
1524cfbfa97SStefano Babic struct spi_transfer xfer;
1534cfbfa97SStefano Babic unsigned char tbuf[CMD_BUFSIZE];
1544cfbfa97SStefano Babic unsigned char rbuf[CMD_BUFSIZE];
1554cfbfa97SStefano Babic int ret, i;
1564cfbfa97SStefano Babic
1574cfbfa97SStefano Babic memset(&xfer, 0, sizeof(struct spi_transfer));
1584cfbfa97SStefano Babic spi_message_init(&msg);
1594cfbfa97SStefano Babic xfer.tx_buf = tbuf;
1604cfbfa97SStefano Babic xfer.rx_buf = rbuf;
1614cfbfa97SStefano Babic xfer.cs_change = 1;
1624cfbfa97SStefano Babic CHECK_FREQ_REG(spi, &xfer);
1634cfbfa97SStefano Babic
1644cfbfa97SStefano Babic tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
1654cfbfa97SStefano Babic START_RW_READ));
1664cfbfa97SStefano Babic /*
1674cfbfa97SStefano Babic * we need 4-byte xfer here due to invalid dummy byte
1684cfbfa97SStefano Babic * received after start byte
1694cfbfa97SStefano Babic */
1704cfbfa97SStefano Babic for (i = 1; i < 4; i++)
1714cfbfa97SStefano Babic tbuf[i] = set_tx_byte(0); /* dummy */
1724cfbfa97SStefano Babic
1734cfbfa97SStefano Babic xfer.bits_per_word = 8;
1744cfbfa97SStefano Babic xfer.len = 4;
1754cfbfa97SStefano Babic spi_message_add_tail(&xfer, &msg);
1764cfbfa97SStefano Babic ret = spi_sync(spi, &msg);
1774cfbfa97SStefano Babic if (ret < 0) {
1784cfbfa97SStefano Babic dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
1794cfbfa97SStefano Babic return ret;
1804cfbfa97SStefano Babic }
1814cfbfa97SStefano Babic
1824cfbfa97SStefano Babic *rs = (rbuf[2] << 8) + rbuf[3];
1834cfbfa97SStefano Babic return 0;
1844cfbfa97SStefano Babic }
1854cfbfa97SStefano Babic
1864cfbfa97SStefano Babic /**
1874cfbfa97SStefano Babic * ili922x_read - read register from display
1884cfbfa97SStefano Babic * @spi: spi device
1894cfbfa97SStefano Babic * @reg: offset of the register to be read
1904cfbfa97SStefano Babic * @rx: output value
1914cfbfa97SStefano Babic */
ili922x_read(struct spi_device * spi,u8 reg,u16 * rx)1924cfbfa97SStefano Babic static int ili922x_read(struct spi_device *spi, u8 reg, u16 *rx)
1934cfbfa97SStefano Babic {
1944cfbfa97SStefano Babic struct spi_message msg;
1954cfbfa97SStefano Babic struct spi_transfer xfer_regindex, xfer_regvalue;
1964cfbfa97SStefano Babic unsigned char tbuf[CMD_BUFSIZE];
1974cfbfa97SStefano Babic unsigned char rbuf[CMD_BUFSIZE];
1984cfbfa97SStefano Babic int ret, len = 0, send_bytes;
1994cfbfa97SStefano Babic
2004cfbfa97SStefano Babic memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
2014cfbfa97SStefano Babic memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
2024cfbfa97SStefano Babic spi_message_init(&msg);
2034cfbfa97SStefano Babic xfer_regindex.tx_buf = tbuf;
2044cfbfa97SStefano Babic xfer_regindex.rx_buf = rbuf;
2054cfbfa97SStefano Babic xfer_regindex.cs_change = 1;
2064cfbfa97SStefano Babic CHECK_FREQ_REG(spi, &xfer_regindex);
2074cfbfa97SStefano Babic
2084cfbfa97SStefano Babic tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
2094cfbfa97SStefano Babic START_RW_WRITE));
2104cfbfa97SStefano Babic tbuf[1] = set_tx_byte(0);
2114cfbfa97SStefano Babic tbuf[2] = set_tx_byte(reg);
2124cfbfa97SStefano Babic xfer_regindex.bits_per_word = 8;
2134cfbfa97SStefano Babic len = xfer_regindex.len = 3;
2144cfbfa97SStefano Babic spi_message_add_tail(&xfer_regindex, &msg);
2154cfbfa97SStefano Babic
2164cfbfa97SStefano Babic send_bytes = len;
2174cfbfa97SStefano Babic
2184cfbfa97SStefano Babic tbuf[len++] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
2194cfbfa97SStefano Babic START_RW_READ));
2204cfbfa97SStefano Babic tbuf[len++] = set_tx_byte(0);
2214cfbfa97SStefano Babic tbuf[len] = set_tx_byte(0);
2224cfbfa97SStefano Babic
2234cfbfa97SStefano Babic xfer_regvalue.cs_change = 1;
2244cfbfa97SStefano Babic xfer_regvalue.len = 3;
2254cfbfa97SStefano Babic xfer_regvalue.tx_buf = &tbuf[send_bytes];
2264cfbfa97SStefano Babic xfer_regvalue.rx_buf = &rbuf[send_bytes];
2274cfbfa97SStefano Babic CHECK_FREQ_REG(spi, &xfer_regvalue);
2284cfbfa97SStefano Babic
2294cfbfa97SStefano Babic spi_message_add_tail(&xfer_regvalue, &msg);
2304cfbfa97SStefano Babic ret = spi_sync(spi, &msg);
2314cfbfa97SStefano Babic if (ret < 0) {
2324cfbfa97SStefano Babic dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
2334cfbfa97SStefano Babic return ret;
2344cfbfa97SStefano Babic }
2354cfbfa97SStefano Babic
2364cfbfa97SStefano Babic *rx = (rbuf[1 + send_bytes] << 8) + rbuf[2 + send_bytes];
2374cfbfa97SStefano Babic return 0;
2384cfbfa97SStefano Babic }
2394cfbfa97SStefano Babic
2404cfbfa97SStefano Babic /**
2414cfbfa97SStefano Babic * ili922x_write - write a controller register
2424cfbfa97SStefano Babic * @spi: struct spi_device *
2434cfbfa97SStefano Babic * @reg: offset of the register to be written
2444cfbfa97SStefano Babic * @value: value to be written
2454cfbfa97SStefano Babic */
ili922x_write(struct spi_device * spi,u8 reg,u16 value)2464cfbfa97SStefano Babic static int ili922x_write(struct spi_device *spi, u8 reg, u16 value)
2474cfbfa97SStefano Babic {
2484cfbfa97SStefano Babic struct spi_message msg;
2494cfbfa97SStefano Babic struct spi_transfer xfer_regindex, xfer_regvalue;
2504cfbfa97SStefano Babic unsigned char tbuf[CMD_BUFSIZE];
2514cfbfa97SStefano Babic unsigned char rbuf[CMD_BUFSIZE];
25229fae2c1SColin Ian King int ret;
2534cfbfa97SStefano Babic
2544cfbfa97SStefano Babic memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
2554cfbfa97SStefano Babic memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
2564cfbfa97SStefano Babic
2574cfbfa97SStefano Babic spi_message_init(&msg);
2584cfbfa97SStefano Babic xfer_regindex.tx_buf = tbuf;
2594cfbfa97SStefano Babic xfer_regindex.rx_buf = rbuf;
2604cfbfa97SStefano Babic xfer_regindex.cs_change = 1;
2614cfbfa97SStefano Babic CHECK_FREQ_REG(spi, &xfer_regindex);
2624cfbfa97SStefano Babic
2634cfbfa97SStefano Babic tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
2644cfbfa97SStefano Babic START_RW_WRITE));
2654cfbfa97SStefano Babic tbuf[1] = set_tx_byte(0);
2664cfbfa97SStefano Babic tbuf[2] = set_tx_byte(reg);
2674cfbfa97SStefano Babic xfer_regindex.bits_per_word = 8;
2684cfbfa97SStefano Babic xfer_regindex.len = 3;
2694cfbfa97SStefano Babic spi_message_add_tail(&xfer_regindex, &msg);
2704cfbfa97SStefano Babic
2714cfbfa97SStefano Babic ret = spi_sync(spi, &msg);
2724cfbfa97SStefano Babic
2734cfbfa97SStefano Babic spi_message_init(&msg);
2744cfbfa97SStefano Babic tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
2754cfbfa97SStefano Babic START_RW_WRITE));
2764cfbfa97SStefano Babic tbuf[1] = set_tx_byte((value & 0xFF00) >> 8);
2774cfbfa97SStefano Babic tbuf[2] = set_tx_byte(value & 0x00FF);
2784cfbfa97SStefano Babic
2794cfbfa97SStefano Babic xfer_regvalue.cs_change = 1;
2804cfbfa97SStefano Babic xfer_regvalue.len = 3;
2814cfbfa97SStefano Babic xfer_regvalue.tx_buf = tbuf;
2824cfbfa97SStefano Babic xfer_regvalue.rx_buf = rbuf;
2834cfbfa97SStefano Babic CHECK_FREQ_REG(spi, &xfer_regvalue);
2844cfbfa97SStefano Babic
2854cfbfa97SStefano Babic spi_message_add_tail(&xfer_regvalue, &msg);
2864cfbfa97SStefano Babic
2874cfbfa97SStefano Babic ret = spi_sync(spi, &msg);
2884cfbfa97SStefano Babic if (ret < 0) {
2894cfbfa97SStefano Babic dev_err(&spi->dev, "Error sending SPI message 0x%x", ret);
2904cfbfa97SStefano Babic return ret;
2914cfbfa97SStefano Babic }
2924cfbfa97SStefano Babic return 0;
2934cfbfa97SStefano Babic }
2944cfbfa97SStefano Babic
2954cfbfa97SStefano Babic #ifdef DEBUG
2964cfbfa97SStefano Babic /**
2974cfbfa97SStefano Babic * ili922x_reg_dump - dump all registers
2987099c930SLee Jones *
2997099c930SLee Jones * @spi: pointer to an SPI device
3004cfbfa97SStefano Babic */
ili922x_reg_dump(struct spi_device * spi)3014cfbfa97SStefano Babic static void ili922x_reg_dump(struct spi_device *spi)
3024cfbfa97SStefano Babic {
3034cfbfa97SStefano Babic u8 reg;
3044cfbfa97SStefano Babic u16 rx;
3054cfbfa97SStefano Babic
3064cfbfa97SStefano Babic dev_dbg(&spi->dev, "ILI922x configuration registers:\n");
3074cfbfa97SStefano Babic for (reg = REG_START_OSCILLATION;
3084cfbfa97SStefano Babic reg <= REG_OTP_PROGRAMMING_ID_KEY; reg++) {
3094cfbfa97SStefano Babic ili922x_read(spi, reg, &rx);
3104cfbfa97SStefano Babic dev_dbg(&spi->dev, "reg @ 0x%02X: 0x%04X\n", reg, rx);
3114cfbfa97SStefano Babic }
3124cfbfa97SStefano Babic }
3134cfbfa97SStefano Babic #else
ili922x_reg_dump(struct spi_device * spi)3144cfbfa97SStefano Babic static inline void ili922x_reg_dump(struct spi_device *spi) {}
3154cfbfa97SStefano Babic #endif
3164cfbfa97SStefano Babic
3174cfbfa97SStefano Babic /**
3184cfbfa97SStefano Babic * set_write_to_gram_reg - initialize the display to write the GRAM
3194cfbfa97SStefano Babic * @spi: spi device
3204cfbfa97SStefano Babic */
set_write_to_gram_reg(struct spi_device * spi)3214cfbfa97SStefano Babic static void set_write_to_gram_reg(struct spi_device *spi)
3224cfbfa97SStefano Babic {
3234cfbfa97SStefano Babic struct spi_message msg;
3244cfbfa97SStefano Babic struct spi_transfer xfer;
3254cfbfa97SStefano Babic unsigned char tbuf[CMD_BUFSIZE];
3264cfbfa97SStefano Babic
3274cfbfa97SStefano Babic memset(&xfer, 0, sizeof(struct spi_transfer));
3284cfbfa97SStefano Babic
3294cfbfa97SStefano Babic spi_message_init(&msg);
3304cfbfa97SStefano Babic xfer.tx_buf = tbuf;
3314cfbfa97SStefano Babic xfer.rx_buf = NULL;
3324cfbfa97SStefano Babic xfer.cs_change = 1;
3334cfbfa97SStefano Babic
3344cfbfa97SStefano Babic tbuf[0] = START_BYTE(ili922x_id, START_RS_INDEX, START_RW_WRITE);
3354cfbfa97SStefano Babic tbuf[1] = 0;
3364cfbfa97SStefano Babic tbuf[2] = REG_WRITE_DATA_TO_GRAM;
3374cfbfa97SStefano Babic
3384cfbfa97SStefano Babic xfer.bits_per_word = 8;
3394cfbfa97SStefano Babic xfer.len = 3;
3404cfbfa97SStefano Babic spi_message_add_tail(&xfer, &msg);
3414cfbfa97SStefano Babic spi_sync(spi, &msg);
3424cfbfa97SStefano Babic }
3434cfbfa97SStefano Babic
3444cfbfa97SStefano Babic /**
3454cfbfa97SStefano Babic * ili922x_poweron - turn the display on
3464cfbfa97SStefano Babic * @spi: spi device
3474cfbfa97SStefano Babic *
3484cfbfa97SStefano Babic * The sequence to turn on the display is taken from
3494cfbfa97SStefano Babic * the datasheet and/or the example code provided by the
3504cfbfa97SStefano Babic * manufacturer.
3514cfbfa97SStefano Babic */
ili922x_poweron(struct spi_device * spi)3524cfbfa97SStefano Babic static int ili922x_poweron(struct spi_device *spi)
3534cfbfa97SStefano Babic {
3544cfbfa97SStefano Babic int ret;
3554cfbfa97SStefano Babic
3564cfbfa97SStefano Babic /* Power on */
3574cfbfa97SStefano Babic ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
3584cfbfa97SStefano Babic usleep_range(10000, 10500);
3594cfbfa97SStefano Babic ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
3604cfbfa97SStefano Babic ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
3614cfbfa97SStefano Babic msleep(40);
3624cfbfa97SStefano Babic ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
3634cfbfa97SStefano Babic msleep(40);
3644cfbfa97SStefano Babic /* register 0x56 is not documented in the datasheet */
3654cfbfa97SStefano Babic ret += ili922x_write(spi, 0x56, 0x080F);
3664cfbfa97SStefano Babic ret += ili922x_write(spi, REG_POWER_CONTROL_1, 0x4240);
3674cfbfa97SStefano Babic usleep_range(10000, 10500);
3684cfbfa97SStefano Babic ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
3694cfbfa97SStefano Babic ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0014);
3704cfbfa97SStefano Babic msleep(40);
3714cfbfa97SStefano Babic ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x1319);
3724cfbfa97SStefano Babic msleep(40);
3734cfbfa97SStefano Babic
3744cfbfa97SStefano Babic return ret;
3754cfbfa97SStefano Babic }
3764cfbfa97SStefano Babic
3774cfbfa97SStefano Babic /**
3784cfbfa97SStefano Babic * ili922x_poweroff - turn the display off
3794cfbfa97SStefano Babic * @spi: spi device
3804cfbfa97SStefano Babic */
ili922x_poweroff(struct spi_device * spi)3814cfbfa97SStefano Babic static int ili922x_poweroff(struct spi_device *spi)
3824cfbfa97SStefano Babic {
3834cfbfa97SStefano Babic int ret;
3844cfbfa97SStefano Babic
3854cfbfa97SStefano Babic /* Power off */
3864cfbfa97SStefano Babic ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
3874cfbfa97SStefano Babic usleep_range(10000, 10500);
3884cfbfa97SStefano Babic ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
3894cfbfa97SStefano Babic ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
3904cfbfa97SStefano Babic msleep(40);
3914cfbfa97SStefano Babic ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
3924cfbfa97SStefano Babic msleep(40);
3934cfbfa97SStefano Babic
3944cfbfa97SStefano Babic return ret;
3954cfbfa97SStefano Babic }
3964cfbfa97SStefano Babic
3974cfbfa97SStefano Babic /**
3984cfbfa97SStefano Babic * ili922x_display_init - initialize the display by setting
3994cfbfa97SStefano Babic * the configuration registers
4004cfbfa97SStefano Babic * @spi: spi device
4014cfbfa97SStefano Babic */
ili922x_display_init(struct spi_device * spi)4024cfbfa97SStefano Babic static void ili922x_display_init(struct spi_device *spi)
4034cfbfa97SStefano Babic {
4044cfbfa97SStefano Babic ili922x_write(spi, REG_START_OSCILLATION, 1);
4054cfbfa97SStefano Babic usleep_range(10000, 10500);
4064cfbfa97SStefano Babic ili922x_write(spi, REG_DRIVER_OUTPUT_CONTROL, 0x691B);
4074cfbfa97SStefano Babic ili922x_write(spi, REG_LCD_AC_DRIVEING_CONTROL, 0x0700);
4084cfbfa97SStefano Babic ili922x_write(spi, REG_ENTRY_MODE, 0x1030);
4094cfbfa97SStefano Babic ili922x_write(spi, REG_COMPARE_1, 0x0000);
4104cfbfa97SStefano Babic ili922x_write(spi, REG_COMPARE_2, 0x0000);
4114cfbfa97SStefano Babic ili922x_write(spi, REG_DISPLAY_CONTROL_1, 0x0037);
4124cfbfa97SStefano Babic ili922x_write(spi, REG_DISPLAY_CONTROL_2, 0x0202);
4134cfbfa97SStefano Babic ili922x_write(spi, REG_DISPLAY_CONTROL_3, 0x0000);
4144cfbfa97SStefano Babic ili922x_write(spi, REG_FRAME_CYCLE_CONTROL, 0x0000);
4154cfbfa97SStefano Babic
4164cfbfa97SStefano Babic /* Set RGB interface */
4174cfbfa97SStefano Babic ili922x_write(spi, REG_EXT_INTF_CONTROL, 0x0110);
4184cfbfa97SStefano Babic
4194cfbfa97SStefano Babic ili922x_poweron(spi);
4204cfbfa97SStefano Babic
4214cfbfa97SStefano Babic ili922x_write(spi, REG_GAMMA_CONTROL_1, 0x0302);
4224cfbfa97SStefano Babic ili922x_write(spi, REG_GAMMA_CONTROL_2, 0x0407);
4234cfbfa97SStefano Babic ili922x_write(spi, REG_GAMMA_CONTROL_3, 0x0304);
4244cfbfa97SStefano Babic ili922x_write(spi, REG_GAMMA_CONTROL_4, 0x0203);
4254cfbfa97SStefano Babic ili922x_write(spi, REG_GAMMA_CONTROL_5, 0x0706);
4264cfbfa97SStefano Babic ili922x_write(spi, REG_GAMMA_CONTROL_6, 0x0407);
4274cfbfa97SStefano Babic ili922x_write(spi, REG_GAMMA_CONTROL_7, 0x0706);
4284cfbfa97SStefano Babic ili922x_write(spi, REG_GAMMA_CONTROL_8, 0x0000);
4294cfbfa97SStefano Babic ili922x_write(spi, REG_GAMMA_CONTROL_9, 0x0C06);
4304cfbfa97SStefano Babic ili922x_write(spi, REG_GAMMA_CONTROL_10, 0x0F00);
4314cfbfa97SStefano Babic ili922x_write(spi, REG_RAM_ADDRESS_SET, 0x0000);
4324cfbfa97SStefano Babic ili922x_write(spi, REG_GATE_SCAN_CONTROL, 0x0000);
4334cfbfa97SStefano Babic ili922x_write(spi, REG_VERT_SCROLL_CONTROL, 0x0000);
4344cfbfa97SStefano Babic ili922x_write(spi, REG_FIRST_SCREEN_DRIVE_POS, 0xDB00);
4354cfbfa97SStefano Babic ili922x_write(spi, REG_SECOND_SCREEN_DRIVE_POS, 0xDB00);
4364cfbfa97SStefano Babic ili922x_write(spi, REG_RAM_ADDR_POS_H, 0xAF00);
4374cfbfa97SStefano Babic ili922x_write(spi, REG_RAM_ADDR_POS_V, 0xDB00);
4384cfbfa97SStefano Babic ili922x_reg_dump(spi);
4394cfbfa97SStefano Babic set_write_to_gram_reg(spi);
4404cfbfa97SStefano Babic }
4414cfbfa97SStefano Babic
ili922x_lcd_power(struct ili922x * lcd,int power)4424cfbfa97SStefano Babic static int ili922x_lcd_power(struct ili922x *lcd, int power)
4434cfbfa97SStefano Babic {
4444cfbfa97SStefano Babic int ret = 0;
4454cfbfa97SStefano Babic
4464cfbfa97SStefano Babic if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
4474cfbfa97SStefano Babic ret = ili922x_poweron(lcd->spi);
4484cfbfa97SStefano Babic else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
4494cfbfa97SStefano Babic ret = ili922x_poweroff(lcd->spi);
4504cfbfa97SStefano Babic
4514cfbfa97SStefano Babic if (!ret)
4524cfbfa97SStefano Babic lcd->power = power;
4534cfbfa97SStefano Babic
4544cfbfa97SStefano Babic return ret;
4554cfbfa97SStefano Babic }
4564cfbfa97SStefano Babic
ili922x_set_power(struct lcd_device * ld,int power)4574cfbfa97SStefano Babic static int ili922x_set_power(struct lcd_device *ld, int power)
4584cfbfa97SStefano Babic {
4594cfbfa97SStefano Babic struct ili922x *ili = lcd_get_data(ld);
4604cfbfa97SStefano Babic
4614cfbfa97SStefano Babic return ili922x_lcd_power(ili, power);
4624cfbfa97SStefano Babic }
4634cfbfa97SStefano Babic
ili922x_get_power(struct lcd_device * ld)4644cfbfa97SStefano Babic static int ili922x_get_power(struct lcd_device *ld)
4654cfbfa97SStefano Babic {
4664cfbfa97SStefano Babic struct ili922x *ili = lcd_get_data(ld);
4674cfbfa97SStefano Babic
4684cfbfa97SStefano Babic return ili->power;
4694cfbfa97SStefano Babic }
4704cfbfa97SStefano Babic
4714cfbfa97SStefano Babic static struct lcd_ops ili922x_ops = {
4724cfbfa97SStefano Babic .get_power = ili922x_get_power,
4734cfbfa97SStefano Babic .set_power = ili922x_set_power,
4744cfbfa97SStefano Babic };
4754cfbfa97SStefano Babic
ili922x_probe(struct spi_device * spi)4764cfbfa97SStefano Babic static int ili922x_probe(struct spi_device *spi)
4774cfbfa97SStefano Babic {
4784cfbfa97SStefano Babic struct ili922x *ili;
4794cfbfa97SStefano Babic struct lcd_device *lcd;
4804cfbfa97SStefano Babic int ret;
4814cfbfa97SStefano Babic u16 reg = 0;
4824cfbfa97SStefano Babic
4834cfbfa97SStefano Babic ili = devm_kzalloc(&spi->dev, sizeof(*ili), GFP_KERNEL);
484619e1b49SJingoo Han if (!ili)
4854cfbfa97SStefano Babic return -ENOMEM;
4864cfbfa97SStefano Babic
4874cfbfa97SStefano Babic ili->spi = spi;
48840d88fc6SJingoo Han spi_set_drvdata(spi, ili);
4894cfbfa97SStefano Babic
4904cfbfa97SStefano Babic /* check if the device is connected */
4914cfbfa97SStefano Babic ret = ili922x_read(spi, REG_DRIVER_CODE_READ, ®);
4924cfbfa97SStefano Babic if (ret || ((reg & ILITEK_DEVICE_ID_MASK) != ILITEK_DEVICE_ID)) {
4934cfbfa97SStefano Babic dev_err(&spi->dev,
4944cfbfa97SStefano Babic "no LCD found: Chip ID 0x%x, ret %d\n",
4954cfbfa97SStefano Babic reg, ret);
4964cfbfa97SStefano Babic return -ENODEV;
497547f60ceSJingoo Han }
498547f60ceSJingoo Han
4994cfbfa97SStefano Babic dev_info(&spi->dev, "ILI%x found, SPI freq %d, mode %d\n",
5004cfbfa97SStefano Babic reg, spi->max_speed_hz, spi->mode);
5014cfbfa97SStefano Babic
5024cfbfa97SStefano Babic ret = ili922x_read_status(spi, ®);
5034cfbfa97SStefano Babic if (ret) {
5044cfbfa97SStefano Babic dev_err(&spi->dev, "reading RS failed...\n");
5054cfbfa97SStefano Babic return ret;
506547f60ceSJingoo Han }
507547f60ceSJingoo Han
5084cfbfa97SStefano Babic dev_dbg(&spi->dev, "status: 0x%x\n", reg);
5094cfbfa97SStefano Babic
5104cfbfa97SStefano Babic ili922x_display_init(spi);
5114cfbfa97SStefano Babic
5124cfbfa97SStefano Babic ili->power = FB_BLANK_POWERDOWN;
5134cfbfa97SStefano Babic
514a7e9e3ffSJingoo Han lcd = devm_lcd_device_register(&spi->dev, "ili922xlcd", &spi->dev, ili,
5154cfbfa97SStefano Babic &ili922x_ops);
5164cfbfa97SStefano Babic if (IS_ERR(lcd)) {
5174cfbfa97SStefano Babic dev_err(&spi->dev, "cannot register LCD\n");
5184cfbfa97SStefano Babic return PTR_ERR(lcd);
5194cfbfa97SStefano Babic }
5204cfbfa97SStefano Babic
5214cfbfa97SStefano Babic ili->ld = lcd;
5224cfbfa97SStefano Babic spi_set_drvdata(spi, ili);
5234cfbfa97SStefano Babic
5244cfbfa97SStefano Babic ili922x_lcd_power(ili, FB_BLANK_UNBLANK);
5254cfbfa97SStefano Babic
5264cfbfa97SStefano Babic return 0;
5274cfbfa97SStefano Babic }
5284cfbfa97SStefano Babic
ili922x_remove(struct spi_device * spi)529*a0386bbaSUwe Kleine-König static void ili922x_remove(struct spi_device *spi)
5304cfbfa97SStefano Babic {
5314cfbfa97SStefano Babic ili922x_poweroff(spi);
5324cfbfa97SStefano Babic }
5334cfbfa97SStefano Babic
5344cfbfa97SStefano Babic static struct spi_driver ili922x_driver = {
5354cfbfa97SStefano Babic .driver = {
5364cfbfa97SStefano Babic .name = "ili922x",
5374cfbfa97SStefano Babic },
5384cfbfa97SStefano Babic .probe = ili922x_probe,
5394cfbfa97SStefano Babic .remove = ili922x_remove,
5404cfbfa97SStefano Babic };
5414cfbfa97SStefano Babic
5424cfbfa97SStefano Babic module_spi_driver(ili922x_driver);
5434cfbfa97SStefano Babic
5444cfbfa97SStefano Babic MODULE_AUTHOR("Stefano Babic <sbabic@denx.de>");
5454cfbfa97SStefano Babic MODULE_DESCRIPTION("ILI9221/9222 LCD driver");
5464cfbfa97SStefano Babic MODULE_LICENSE("GPL");
5474cfbfa97SStefano Babic MODULE_PARM_DESC(ili922x_id, "set controller identifier (default=1)");
5484cfbfa97SStefano Babic MODULE_PARM_DESC(tx_invert, "invert bytes before sending");
549