1*234489acSNipun Gupta /* SPDX-License-Identifier: GPL-2.0 */ 2*234489acSNipun Gupta /* 3*234489acSNipun Gupta * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. 4*234489acSNipun Gupta */ 5*234489acSNipun Gupta 6*234489acSNipun Gupta #ifndef VFIO_CDX_PRIVATE_H 7*234489acSNipun Gupta #define VFIO_CDX_PRIVATE_H 8*234489acSNipun Gupta 9*234489acSNipun Gupta #define VFIO_CDX_OFFSET_SHIFT 40 10*234489acSNipun Gupta vfio_cdx_index_to_offset(u32 index)11*234489acSNipun Guptastatic inline u64 vfio_cdx_index_to_offset(u32 index) 12*234489acSNipun Gupta { 13*234489acSNipun Gupta return ((u64)(index) << VFIO_CDX_OFFSET_SHIFT); 14*234489acSNipun Gupta } 15*234489acSNipun Gupta 16*234489acSNipun Gupta struct vfio_cdx_region { 17*234489acSNipun Gupta u32 flags; 18*234489acSNipun Gupta u32 type; 19*234489acSNipun Gupta u64 addr; 20*234489acSNipun Gupta resource_size_t size; 21*234489acSNipun Gupta }; 22*234489acSNipun Gupta 23*234489acSNipun Gupta struct vfio_cdx_device { 24*234489acSNipun Gupta struct vfio_device vdev; 25*234489acSNipun Gupta struct vfio_cdx_region *regions; 26*234489acSNipun Gupta }; 27*234489acSNipun Gupta 28*234489acSNipun Gupta #endif /* VFIO_CDX_PRIVATE_H */ 29