1*c16d5a41SShannon Nelson /* SPDX-License-Identifier: GPL-2.0-only */ 2*c16d5a41SShannon Nelson /* Copyright(c) 2023 Advanced Micro Devices, Inc */ 3*c16d5a41SShannon Nelson 4*c16d5a41SShannon Nelson #ifndef _VDPA_CMDS_H_ 5*c16d5a41SShannon Nelson #define _VDPA_CMDS_H_ 6*c16d5a41SShannon Nelson 7*c16d5a41SShannon Nelson int pds_vdpa_init_hw(struct pds_vdpa_device *pdsv); 8*c16d5a41SShannon Nelson 9*c16d5a41SShannon Nelson int pds_vdpa_cmd_reset(struct pds_vdpa_device *pdsv); 10*c16d5a41SShannon Nelson int pds_vdpa_cmd_set_status(struct pds_vdpa_device *pdsv, u8 status); 11*c16d5a41SShannon Nelson int pds_vdpa_cmd_set_mac(struct pds_vdpa_device *pdsv, u8 *mac); 12*c16d5a41SShannon Nelson int pds_vdpa_cmd_set_max_vq_pairs(struct pds_vdpa_device *pdsv, u16 max_vqp); 13*c16d5a41SShannon Nelson int pds_vdpa_cmd_init_vq(struct pds_vdpa_device *pdsv, u16 qid, u16 invert_idx, 14*c16d5a41SShannon Nelson struct pds_vdpa_vq_info *vq_info); 15*c16d5a41SShannon Nelson int pds_vdpa_cmd_reset_vq(struct pds_vdpa_device *pdsv, u16 qid, u16 invert_idx, 16*c16d5a41SShannon Nelson struct pds_vdpa_vq_info *vq_info); 17*c16d5a41SShannon Nelson int pds_vdpa_cmd_set_features(struct pds_vdpa_device *pdsv, u64 features); 18*c16d5a41SShannon Nelson #endif /* _VDPA_CMDS_H_ */ 19