1 /* 2 * TUSB6010 USB 2.0 OTG Dual Role controller 3 * 4 * Copyright (C) 2006 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Notes: 12 * - Driver assumes that interface to external host (main CPU) is 13 * configured for NOR FLASH interface instead of VLYNQ serial 14 * interface. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/errno.h> 20 #include <linux/init.h> 21 #include <linux/usb.h> 22 #include <linux/irq.h> 23 #include <linux/platform_device.h> 24 #include <linux/dma-mapping.h> 25 26 #include "musb_core.h" 27 28 struct tusb6010_glue { 29 struct device *dev; 30 struct platform_device *musb; 31 }; 32 33 static void tusb_musb_set_vbus(struct musb *musb, int is_on); 34 35 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) 36 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) 37 38 /* 39 * Checks the revision. We need to use the DMA register as 3.0 does not 40 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. 41 */ 42 u8 tusb_get_revision(struct musb *musb) 43 { 44 void __iomem *tbase = musb->ctrl_base; 45 u32 die_id; 46 u8 rev; 47 48 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff; 49 if (TUSB_REV_MAJOR(rev) == 3) { 50 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, 51 TUSB_DIDR1_HI)); 52 if (die_id >= TUSB_DIDR1_HI_REV_31) 53 rev |= 1; 54 } 55 56 return rev; 57 } 58 59 static int tusb_print_revision(struct musb *musb) 60 { 61 void __iomem *tbase = musb->ctrl_base; 62 u8 rev; 63 64 rev = tusb_get_revision(musb); 65 66 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n", 67 "prcm", 68 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)), 69 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)), 70 "int", 71 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 72 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 73 "gpio", 74 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)), 75 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)), 76 "dma", 77 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 78 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 79 "dieid", 80 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)), 81 "rev", 82 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev)); 83 84 return tusb_get_revision(musb); 85 } 86 87 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \ 88 | TUSB_PHY_OTG_CTRL_TESTM0) 89 90 /* 91 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0. 92 * Disables power detection in PHY for the duration of idle. 93 */ 94 static void tusb_wbus_quirk(struct musb *musb, int enabled) 95 { 96 void __iomem *tbase = musb->ctrl_base; 97 static u32 phy_otg_ctrl, phy_otg_ena; 98 u32 tmp; 99 100 if (enabled) { 101 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 102 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 103 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT 104 | phy_otg_ena | WBUS_QUIRK_MASK; 105 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 109 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 110 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 113 & TUSB_PHY_OTG_CTRL_TESTM2) { 114 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl; 115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 118 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 119 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 121 phy_otg_ctrl = 0; 122 phy_otg_ena = 0; 123 } 124 } 125 126 /* 127 * TUSB 6010 may use a parallel bus that doesn't support byte ops; 128 * so both loading and unloading FIFOs need explicit byte counts. 129 */ 130 131 static inline void 132 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len) 133 { 134 u32 val; 135 int i; 136 137 if (len > 4) { 138 for (i = 0; i < (len >> 2); i++) { 139 memcpy(&val, buf, 4); 140 musb_writel(fifo, 0, val); 141 buf += 4; 142 } 143 len %= 4; 144 } 145 if (len > 0) { 146 /* Write the rest 1 - 3 bytes to FIFO */ 147 memcpy(&val, buf, len); 148 musb_writel(fifo, 0, val); 149 } 150 } 151 152 static inline void tusb_fifo_read_unaligned(void __iomem *fifo, 153 void __iomem *buf, u16 len) 154 { 155 u32 val; 156 int i; 157 158 if (len > 4) { 159 for (i = 0; i < (len >> 2); i++) { 160 val = musb_readl(fifo, 0); 161 memcpy(buf, &val, 4); 162 buf += 4; 163 } 164 len %= 4; 165 } 166 if (len > 0) { 167 /* Read the rest 1 - 3 bytes from FIFO */ 168 val = musb_readl(fifo, 0); 169 memcpy(buf, &val, len); 170 } 171 } 172 173 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) 174 { 175 void __iomem *ep_conf = hw_ep->conf; 176 void __iomem *fifo = hw_ep->fifo; 177 u8 epnum = hw_ep->epnum; 178 179 prefetch(buf); 180 181 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 182 'T', epnum, fifo, len, buf); 183 184 if (epnum) 185 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 186 TUSB_EP_CONFIG_XFR_SIZE(len)); 187 else 188 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX | 189 TUSB_EP0_CONFIG_XFR_SIZE(len)); 190 191 if (likely((0x01 & (unsigned long) buf) == 0)) { 192 193 /* Best case is 32bit-aligned destination address */ 194 if ((0x02 & (unsigned long) buf) == 0) { 195 if (len >= 4) { 196 writesl(fifo, buf, len >> 2); 197 buf += (len & ~0x03); 198 len &= 0x03; 199 } 200 } else { 201 if (len >= 2) { 202 u32 val; 203 int i; 204 205 /* Cannot use writesw, fifo is 32-bit */ 206 for (i = 0; i < (len >> 2); i++) { 207 val = (u32)(*(u16 *)buf); 208 buf += 2; 209 val |= (*(u16 *)buf) << 16; 210 buf += 2; 211 musb_writel(fifo, 0, val); 212 } 213 len &= 0x03; 214 } 215 } 216 } 217 218 if (len > 0) 219 tusb_fifo_write_unaligned(fifo, buf, len); 220 } 221 222 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) 223 { 224 void __iomem *ep_conf = hw_ep->conf; 225 void __iomem *fifo = hw_ep->fifo; 226 u8 epnum = hw_ep->epnum; 227 228 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 229 'R', epnum, fifo, len, buf); 230 231 if (epnum) 232 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 233 TUSB_EP_CONFIG_XFR_SIZE(len)); 234 else 235 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len)); 236 237 if (likely((0x01 & (unsigned long) buf) == 0)) { 238 239 /* Best case is 32bit-aligned destination address */ 240 if ((0x02 & (unsigned long) buf) == 0) { 241 if (len >= 4) { 242 readsl(fifo, buf, len >> 2); 243 buf += (len & ~0x03); 244 len &= 0x03; 245 } 246 } else { 247 if (len >= 2) { 248 u32 val; 249 int i; 250 251 /* Cannot use readsw, fifo is 32-bit */ 252 for (i = 0; i < (len >> 2); i++) { 253 val = musb_readl(fifo, 0); 254 *(u16 *)buf = (u16)(val & 0xffff); 255 buf += 2; 256 *(u16 *)buf = (u16)(val >> 16); 257 buf += 2; 258 } 259 len &= 0x03; 260 } 261 } 262 } 263 264 if (len > 0) 265 tusb_fifo_read_unaligned(fifo, buf, len); 266 } 267 268 static struct musb *the_musb; 269 270 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 271 272 /* This is used by gadget drivers, and OTG transceiver logic, allowing 273 * at most mA current to be drawn from VBUS during a Default-B session 274 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host 275 * mode), or low power Default-B sessions, something else supplies power. 276 * Caller must take care of locking. 277 */ 278 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA) 279 { 280 struct musb *musb = the_musb; 281 void __iomem *tbase = musb->ctrl_base; 282 u32 reg; 283 284 /* 285 * Keep clock active when enabled. Note that this is not tied to 286 * drawing VBUS, as with OTG mA can be less than musb->min_power. 287 */ 288 if (musb->set_clock) { 289 if (mA) 290 musb->set_clock(musb->clock, 1); 291 else 292 musb->set_clock(musb->clock, 0); 293 } 294 295 /* tps65030 seems to consume max 100mA, with maybe 60mA available 296 * (measured on one board) for things other than tps and tusb. 297 * 298 * Boards sharing the CPU clock with CLKIN will need to prevent 299 * certain idle sleep states while the USB link is active. 300 * 301 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }. 302 * The actual current usage would be very board-specific. For now, 303 * it's simpler to just use an aggregate (also board-specific). 304 */ 305 if (x->default_a || mA < (musb->min_power << 1)) 306 mA = 0; 307 308 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 309 if (mA) { 310 musb->is_bus_powered = 1; 311 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; 312 } else { 313 musb->is_bus_powered = 0; 314 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 315 } 316 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 317 318 DBG(2, "draw max %d mA VBUS\n", mA); 319 return 0; 320 } 321 322 #else 323 #define tusb_draw_power NULL 324 #endif 325 326 /* workaround for issue 13: change clock during chip idle 327 * (to be fixed in rev3 silicon) ... symptoms include disconnect 328 * or looping suspend/resume cycles 329 */ 330 static void tusb_set_clock_source(struct musb *musb, unsigned mode) 331 { 332 void __iomem *tbase = musb->ctrl_base; 333 u32 reg; 334 335 reg = musb_readl(tbase, TUSB_PRCM_CONF); 336 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); 337 338 /* 0 = refclk (clkin, XI) 339 * 1 = PHY 60 MHz (internal PLL) 340 * 2 = not supported 341 * 3 = what? 342 */ 343 if (mode > 0) 344 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); 345 346 musb_writel(tbase, TUSB_PRCM_CONF, reg); 347 348 /* FIXME tusb6010_platform_retime(mode == 0); */ 349 } 350 351 /* 352 * Idle TUSB6010 until next wake-up event; NOR access always wakes. 353 * Other code ensures that we idle unless we're connected _and_ the 354 * USB link is not suspended ... and tells us the relevant wakeup 355 * events. SW_EN for voltage is handled separately. 356 */ 357 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables) 358 { 359 void __iomem *tbase = musb->ctrl_base; 360 u32 reg; 361 362 if ((wakeup_enables & TUSB_PRCM_WBUS) 363 && (tusb_get_revision(musb) == TUSB_REV_30)) 364 tusb_wbus_quirk(musb, 1); 365 366 tusb_set_clock_source(musb, 0); 367 368 wakeup_enables |= TUSB_PRCM_WNORCS; 369 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables); 370 371 /* REVISIT writeup of WID implies that if WID set and ID is grounded, 372 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared. 373 * Presumably that's mostly to save power, hence WID is immaterial ... 374 */ 375 376 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 377 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */ 378 if (is_host_active(musb)) { 379 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 380 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 381 } else { 382 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 383 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 384 } 385 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 386 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 387 388 DBG(6, "idle, wake on %02x\n", wakeup_enables); 389 } 390 391 /* 392 * Updates cable VBUS status. Caller must take care of locking. 393 */ 394 static int tusb_musb_vbus_status(struct musb *musb) 395 { 396 void __iomem *tbase = musb->ctrl_base; 397 u32 otg_stat, prcm_mngmt; 398 int ret = 0; 399 400 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 401 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT); 402 403 /* Temporarily enable VBUS detection if it was disabled for 404 * suspend mode. Unless it's enabled otg_stat and devctl will 405 * not show correct VBUS state. 406 */ 407 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) { 408 u32 tmp = prcm_mngmt; 409 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 410 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp); 411 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 412 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt); 413 } 414 415 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) 416 ret = 1; 417 418 return ret; 419 } 420 421 static struct timer_list musb_idle_timer; 422 423 static void musb_do_idle(unsigned long _musb) 424 { 425 struct musb *musb = (void *)_musb; 426 unsigned long flags; 427 428 spin_lock_irqsave(&musb->lock, flags); 429 430 switch (musb->xceiv->state) { 431 case OTG_STATE_A_WAIT_BCON: 432 if ((musb->a_wait_bcon != 0) 433 && (musb->idle_timeout == 0 434 || time_after(jiffies, musb->idle_timeout))) { 435 DBG(4, "Nothing connected %s, turning off VBUS\n", 436 otg_state_string(musb)); 437 } 438 /* FALLTHROUGH */ 439 case OTG_STATE_A_IDLE: 440 tusb_musb_set_vbus(musb, 0); 441 default: 442 break; 443 } 444 445 if (!musb->is_active) { 446 u32 wakeups; 447 448 /* wait until khubd handles port change status */ 449 if (is_host_active(musb) && (musb->port1_status >> 16)) 450 goto done; 451 452 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 453 if (is_peripheral_enabled(musb) && !musb->gadget_driver) 454 wakeups = 0; 455 else { 456 wakeups = TUSB_PRCM_WHOSTDISCON 457 | TUSB_PRCM_WBUS 458 | TUSB_PRCM_WVBUS; 459 if (is_otg_enabled(musb)) 460 wakeups |= TUSB_PRCM_WID; 461 } 462 #else 463 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS; 464 #endif 465 tusb_allow_idle(musb, wakeups); 466 } 467 done: 468 spin_unlock_irqrestore(&musb->lock, flags); 469 } 470 471 /* 472 * Maybe put TUSB6010 into idle mode mode depending on USB link status, 473 * like "disconnected" or "suspended". We'll be woken out of it by 474 * connect, resume, or disconnect. 475 * 476 * Needs to be called as the last function everywhere where there is 477 * register access to TUSB6010 because of NOR flash wake-up. 478 * Caller should own controller spinlock. 479 * 480 * Delay because peripheral enables D+ pullup 3msec after SE0, and 481 * we don't want to treat that full speed J as a wakeup event. 482 * ... peripherals must draw only suspend current after 10 msec. 483 */ 484 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout) 485 { 486 unsigned long default_timeout = jiffies + msecs_to_jiffies(3); 487 static unsigned long last_timer; 488 489 if (timeout == 0) 490 timeout = default_timeout; 491 492 /* Never idle if active, or when VBUS timeout is not set as host */ 493 if (musb->is_active || ((musb->a_wait_bcon == 0) 494 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) { 495 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 496 del_timer(&musb_idle_timer); 497 last_timer = jiffies; 498 return; 499 } 500 501 if (time_after(last_timer, timeout)) { 502 if (!timer_pending(&musb_idle_timer)) 503 last_timer = timeout; 504 else { 505 DBG(4, "Longer idle timer already pending, ignoring\n"); 506 return; 507 } 508 } 509 last_timer = timeout; 510 511 DBG(4, "%s inactive, for idle timer for %lu ms\n", 512 otg_state_string(musb), 513 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 514 mod_timer(&musb_idle_timer, timeout); 515 } 516 517 /* ticks of 60 MHz clock */ 518 #define DEVCLOCK 60000000 519 #define OTG_TIMER_MS(msecs) ((msecs) \ 520 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \ 521 | TUSB_DEV_OTG_TIMER_ENABLE) \ 522 : 0) 523 524 static void tusb_musb_set_vbus(struct musb *musb, int is_on) 525 { 526 void __iomem *tbase = musb->ctrl_base; 527 u32 conf, prcm, timer; 528 u8 devctl; 529 530 /* HDRC controls CPEN, but beware current surges during device 531 * connect. They can trigger transient overcurrent conditions 532 * that must be ignored. 533 */ 534 535 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT); 536 conf = musb_readl(tbase, TUSB_DEV_CONF); 537 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 538 539 if (is_on) { 540 if (musb->set_clock) 541 musb->set_clock(musb->clock, 1); 542 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); 543 musb->xceiv->default_a = 1; 544 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 545 devctl |= MUSB_DEVCTL_SESSION; 546 547 conf |= TUSB_DEV_CONF_USB_HOST_MODE; 548 MUSB_HST_MODE(musb); 549 } else { 550 u32 otg_stat; 551 552 timer = 0; 553 554 /* If ID pin is grounded, we want to be a_idle */ 555 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 556 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { 557 switch (musb->xceiv->state) { 558 case OTG_STATE_A_WAIT_VRISE: 559 case OTG_STATE_A_WAIT_BCON: 560 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 561 break; 562 case OTG_STATE_A_WAIT_VFALL: 563 musb->xceiv->state = OTG_STATE_A_IDLE; 564 break; 565 default: 566 musb->xceiv->state = OTG_STATE_A_IDLE; 567 } 568 musb->is_active = 0; 569 musb->xceiv->default_a = 1; 570 MUSB_HST_MODE(musb); 571 } else { 572 musb->is_active = 0; 573 musb->xceiv->default_a = 0; 574 musb->xceiv->state = OTG_STATE_B_IDLE; 575 MUSB_DEV_MODE(musb); 576 } 577 578 devctl &= ~MUSB_DEVCTL_SESSION; 579 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE; 580 if (musb->set_clock) 581 musb->set_clock(musb->clock, 0); 582 } 583 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 584 585 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm); 586 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer); 587 musb_writel(tbase, TUSB_DEV_CONF, conf); 588 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 589 590 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 591 otg_state_string(musb), 592 musb_readb(musb->mregs, MUSB_DEVCTL), 593 musb_readl(tbase, TUSB_DEV_OTG_STAT), 594 conf, prcm); 595 } 596 597 /* 598 * Sets the mode to OTG, peripheral or host by changing the ID detection. 599 * Caller must take care of locking. 600 * 601 * Note that if a mini-A cable is plugged in the ID line will stay down as 602 * the weak ID pull-up is not able to pull the ID up. 603 * 604 * REVISIT: It would be possible to add support for changing between host 605 * and peripheral modes in non-OTG configurations by reconfiguring hardware 606 * and then setting musb->board_mode. For now, only support OTG mode. 607 */ 608 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode) 609 { 610 void __iomem *tbase = musb->ctrl_base; 611 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf; 612 613 if (musb->board_mode != MUSB_OTG) { 614 ERR("Changing mode currently only supported in OTG mode\n"); 615 return -EINVAL; 616 } 617 618 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 619 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 620 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 621 dev_conf = musb_readl(tbase, TUSB_DEV_CONF); 622 623 switch (musb_mode) { 624 625 #ifdef CONFIG_USB_MUSB_HDRC_HCD 626 case MUSB_HOST: /* Disable PHY ID detect, ground ID */ 627 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 628 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 629 dev_conf |= TUSB_DEV_CONF_ID_SEL; 630 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID; 631 break; 632 #endif 633 634 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 635 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */ 636 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 637 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 638 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 639 break; 640 #endif 641 642 #ifdef CONFIG_USB_MUSB_OTG 643 case MUSB_OTG: /* Use PHY ID detection */ 644 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 645 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 646 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 647 break; 648 #endif 649 650 default: 651 DBG(2, "Trying to set mode %i\n", musb_mode); 652 return -EINVAL; 653 } 654 655 musb_writel(tbase, TUSB_PHY_OTG_CTRL, 656 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl); 657 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, 658 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena); 659 musb_writel(tbase, TUSB_DEV_CONF, dev_conf); 660 661 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 662 if ((musb_mode == MUSB_PERIPHERAL) && 663 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) 664 INFO("Cannot be peripheral with mini-A cable " 665 "otg_stat: %08x\n", otg_stat); 666 667 return 0; 668 } 669 670 static inline unsigned long 671 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) 672 { 673 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 674 unsigned long idle_timeout = 0; 675 676 /* ID pin */ 677 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) { 678 int default_a; 679 680 if (is_otg_enabled(musb)) 681 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 682 else 683 default_a = is_host_enabled(musb); 684 DBG(2, "Default-%c\n", default_a ? 'A' : 'B'); 685 musb->xceiv->default_a = default_a; 686 tusb_musb_set_vbus(musb, default_a); 687 688 /* Don't allow idling immediately */ 689 if (default_a) 690 idle_timeout = jiffies + (HZ * 3); 691 } 692 693 /* VBUS state change */ 694 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { 695 696 /* B-dev state machine: no vbus ~= disconnect */ 697 if ((is_otg_enabled(musb) && !musb->xceiv->default_a) 698 || !is_host_enabled(musb)) { 699 #ifdef CONFIG_USB_MUSB_HDRC_HCD 700 /* ? musb_root_disconnect(musb); */ 701 musb->port1_status &= 702 ~(USB_PORT_STAT_CONNECTION 703 | USB_PORT_STAT_ENABLE 704 | USB_PORT_STAT_LOW_SPEED 705 | USB_PORT_STAT_HIGH_SPEED 706 | USB_PORT_STAT_TEST 707 ); 708 #endif 709 710 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 711 DBG(1, "Forcing disconnect (no interrupt)\n"); 712 if (musb->xceiv->state != OTG_STATE_B_IDLE) { 713 /* INTR_DISCONNECT can hide... */ 714 musb->xceiv->state = OTG_STATE_B_IDLE; 715 musb->int_usb |= MUSB_INTR_DISCONNECT; 716 } 717 musb->is_active = 0; 718 } 719 DBG(2, "vbus change, %s, otg %03x\n", 720 otg_state_string(musb), otg_stat); 721 idle_timeout = jiffies + (1 * HZ); 722 schedule_work(&musb->irq_work); 723 724 } else /* A-dev state machine */ { 725 DBG(2, "vbus change, %s, otg %03x\n", 726 otg_state_string(musb), otg_stat); 727 728 switch (musb->xceiv->state) { 729 case OTG_STATE_A_IDLE: 730 DBG(2, "Got SRP, turning on VBUS\n"); 731 musb_platform_set_vbus(musb, 1); 732 733 /* CONNECT can wake if a_wait_bcon is set */ 734 if (musb->a_wait_bcon != 0) 735 musb->is_active = 0; 736 else 737 musb->is_active = 1; 738 739 /* 740 * OPT FS A TD.4.6 needs few seconds for 741 * A_WAIT_VRISE 742 */ 743 idle_timeout = jiffies + (2 * HZ); 744 745 break; 746 case OTG_STATE_A_WAIT_VRISE: 747 /* ignore; A-session-valid < VBUS_VALID/2, 748 * we monitor this with the timer 749 */ 750 break; 751 case OTG_STATE_A_WAIT_VFALL: 752 /* REVISIT this irq triggers during short 753 * spikes caused by enumeration ... 754 */ 755 if (musb->vbuserr_retry) { 756 musb->vbuserr_retry--; 757 tusb_musb_set_vbus(musb, 1); 758 } else { 759 musb->vbuserr_retry 760 = VBUSERR_RETRY_COUNT; 761 tusb_musb_set_vbus(musb, 0); 762 } 763 break; 764 default: 765 break; 766 } 767 } 768 } 769 770 /* OTG timer expiration */ 771 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 772 u8 devctl; 773 774 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat); 775 776 switch (musb->xceiv->state) { 777 case OTG_STATE_A_WAIT_VRISE: 778 /* VBUS has probably been valid for a while now, 779 * but may well have bounced out of range a bit 780 */ 781 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 782 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 783 if ((devctl & MUSB_DEVCTL_VBUS) 784 != MUSB_DEVCTL_VBUS) { 785 DBG(2, "devctl %02x\n", devctl); 786 break; 787 } 788 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 789 musb->is_active = 0; 790 idle_timeout = jiffies 791 + msecs_to_jiffies(musb->a_wait_bcon); 792 } else { 793 /* REVISIT report overcurrent to hub? */ 794 ERR("vbus too slow, devctl %02x\n", devctl); 795 tusb_musb_set_vbus(musb, 0); 796 } 797 break; 798 case OTG_STATE_A_WAIT_BCON: 799 if (musb->a_wait_bcon != 0) 800 idle_timeout = jiffies 801 + msecs_to_jiffies(musb->a_wait_bcon); 802 break; 803 case OTG_STATE_A_SUSPEND: 804 break; 805 case OTG_STATE_B_WAIT_ACON: 806 break; 807 default: 808 break; 809 } 810 } 811 schedule_work(&musb->irq_work); 812 813 return idle_timeout; 814 } 815 816 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci) 817 { 818 struct musb *musb = __hci; 819 void __iomem *tbase = musb->ctrl_base; 820 unsigned long flags, idle_timeout = 0; 821 u32 int_mask, int_src; 822 823 spin_lock_irqsave(&musb->lock, flags); 824 825 /* Mask all interrupts to allow using both edge and level GPIO irq */ 826 int_mask = musb_readl(tbase, TUSB_INT_MASK); 827 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 828 829 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 830 DBG(3, "TUSB IRQ %08x\n", int_src); 831 832 musb->int_usb = (u8) int_src; 833 834 /* Acknowledge wake-up source interrupts */ 835 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) { 836 u32 reg; 837 u32 i; 838 839 if (tusb_get_revision(musb) == TUSB_REV_30) 840 tusb_wbus_quirk(musb, 0); 841 842 /* there are issues re-locking the PLL on wakeup ... */ 843 844 /* work around issue 8 */ 845 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) { 846 musb_writel(tbase, TUSB_SCRATCH_PAD, 0); 847 musb_writel(tbase, TUSB_SCRATCH_PAD, i); 848 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 849 if (reg == i) 850 break; 851 DBG(6, "TUSB NOR not ready\n"); 852 } 853 854 /* work around issue 13 (2nd half) */ 855 tusb_set_clock_source(musb, 1); 856 857 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE); 858 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); 859 if (reg & ~TUSB_PRCM_WNORCS) { 860 musb->is_active = 1; 861 schedule_work(&musb->irq_work); 862 } 863 DBG(3, "wake %sactive %02x\n", 864 musb->is_active ? "" : "in", reg); 865 866 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 867 } 868 869 if (int_src & TUSB_INT_SRC_USB_IP_CONN) 870 del_timer(&musb_idle_timer); 871 872 /* OTG state change reports (annoyingly) not issued by Mentor core */ 873 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG 874 | TUSB_INT_SRC_OTG_TIMEOUT 875 | TUSB_INT_SRC_ID_STATUS_CHNG)) 876 idle_timeout = tusb_otg_ints(musb, int_src, tbase); 877 878 /* TX dma callback must be handled here, RX dma callback is 879 * handled in tusb_omap_dma_cb. 880 */ 881 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) { 882 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 883 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK); 884 885 DBG(3, "DMA IRQ %08x\n", dma_src); 886 real_dma_src = ~real_dma_src & dma_src; 887 if (tusb_dma_omap() && real_dma_src) { 888 int tx_source = (real_dma_src & 0xffff); 889 int i; 890 891 for (i = 1; i <= 15; i++) { 892 if (tx_source & (1 << i)) { 893 DBG(3, "completing ep%i %s\n", i, "tx"); 894 musb_dma_completion(musb, i, 1); 895 } 896 } 897 } 898 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src); 899 } 900 901 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */ 902 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) { 903 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC); 904 905 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src); 906 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1); 907 musb->int_tx = (musb_src & 0xffff); 908 } else { 909 musb->int_rx = 0; 910 musb->int_tx = 0; 911 } 912 913 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff)) 914 musb_interrupt(musb); 915 916 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */ 917 musb_writel(tbase, TUSB_INT_SRC_CLEAR, 918 int_src & ~TUSB_INT_MASK_RESERVED_BITS); 919 920 tusb_musb_try_idle(musb, idle_timeout); 921 922 musb_writel(tbase, TUSB_INT_MASK, int_mask); 923 spin_unlock_irqrestore(&musb->lock, flags); 924 925 return IRQ_HANDLED; 926 } 927 928 static int dma_off; 929 930 /* 931 * Enables TUSB6010. Caller must take care of locking. 932 * REVISIT: 933 * - Check what is unnecessary in MGC_HdrcStart() 934 */ 935 static void tusb_musb_enable(struct musb *musb) 936 { 937 void __iomem *tbase = musb->ctrl_base; 938 939 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF. 940 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */ 941 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF); 942 943 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */ 944 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0); 945 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 946 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 947 948 /* Clear all subsystem interrups */ 949 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff); 950 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff); 951 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff); 952 953 /* Acknowledge pending interrupt(s) */ 954 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS); 955 956 /* Only 0 clock cycles for minimum interrupt de-assertion time and 957 * interrupt polarity active low seems to work reliably here */ 958 musb_writel(tbase, TUSB_INT_CTRL_CONF, 959 TUSB_INT_CTRL_CONF_INT_RELCYC(0)); 960 961 set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW); 962 963 /* maybe force into the Default-A OTG state machine */ 964 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT) 965 & TUSB_DEV_OTG_STAT_ID_STATUS)) 966 musb_writel(tbase, TUSB_INT_SRC_SET, 967 TUSB_INT_SRC_ID_STATUS_CHNG); 968 969 if (is_dma_capable() && dma_off) 970 printk(KERN_WARNING "%s %s: dma not reactivated\n", 971 __FILE__, __func__); 972 else 973 dma_off = 1; 974 } 975 976 /* 977 * Disables TUSB6010. Caller must take care of locking. 978 */ 979 static void tusb_musb_disable(struct musb *musb) 980 { 981 void __iomem *tbase = musb->ctrl_base; 982 983 /* FIXME stop DMA, IRQs, timers, ... */ 984 985 /* disable all IRQs */ 986 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 987 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff); 988 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 989 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 990 991 del_timer(&musb_idle_timer); 992 993 if (is_dma_capable() && !dma_off) { 994 printk(KERN_WARNING "%s %s: dma still active\n", 995 __FILE__, __func__); 996 dma_off = 1; 997 } 998 } 999 1000 /* 1001 * Sets up TUSB6010 CPU interface specific signals and registers 1002 * Note: Settings optimized for OMAP24xx 1003 */ 1004 static void tusb_setup_cpu_interface(struct musb *musb) 1005 { 1006 void __iomem *tbase = musb->ctrl_base; 1007 1008 /* 1009 * Disable GPIO[5:0] pullups (used as output DMA requests) 1010 * Don't disable GPIO[7:6] as they are needed for wake-up. 1011 */ 1012 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F); 1013 1014 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */ 1015 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF); 1016 1017 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */ 1018 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f)); 1019 1020 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request 1021 * de-assertion time 2 system clocks p 62 */ 1022 musb_writel(tbase, TUSB_DMA_REQ_CONF, 1023 TUSB_DMA_REQ_CONF_BURST_SIZE(2) | 1024 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | 1025 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 1026 1027 /* Set 0 wait count for synchronous burst access */ 1028 musb_writel(tbase, TUSB_WAIT_COUNT, 1); 1029 } 1030 1031 static int tusb_musb_start(struct musb *musb) 1032 { 1033 void __iomem *tbase = musb->ctrl_base; 1034 int ret = 0; 1035 unsigned long flags; 1036 u32 reg; 1037 1038 if (musb->board_set_power) 1039 ret = musb->board_set_power(1); 1040 if (ret != 0) { 1041 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n"); 1042 return ret; 1043 } 1044 1045 spin_lock_irqsave(&musb->lock, flags); 1046 1047 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) != 1048 TUSB_PROD_TEST_RESET_VAL) { 1049 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n"); 1050 goto err; 1051 } 1052 1053 ret = tusb_print_revision(musb); 1054 if (ret < 2) { 1055 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n", 1056 ret); 1057 goto err; 1058 } 1059 1060 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when 1061 * NOR FLASH interface is used */ 1062 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8); 1063 1064 /* Select PHY free running 60MHz as a system clock */ 1065 tusb_set_clock_source(musb, 1); 1066 1067 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for 1068 * power saving, enable VBus detect and session end comparators, 1069 * enable IDpullup, enable VBus charging */ 1070 musb_writel(tbase, TUSB_PRCM_MNGMT, 1071 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) | 1072 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN | 1073 TUSB_PRCM_MNGMT_OTG_SESS_END_EN | 1074 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN | 1075 TUSB_PRCM_MNGMT_OTG_ID_PULLUP); 1076 tusb_setup_cpu_interface(musb); 1077 1078 /* simplify: always sense/pullup ID pins, as if in OTG mode */ 1079 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 1080 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1081 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg); 1082 1083 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 1084 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1085 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg); 1086 1087 spin_unlock_irqrestore(&musb->lock, flags); 1088 1089 return 0; 1090 1091 err: 1092 spin_unlock_irqrestore(&musb->lock, flags); 1093 1094 if (musb->board_set_power) 1095 musb->board_set_power(0); 1096 1097 return -ENODEV; 1098 } 1099 1100 static int tusb_musb_init(struct musb *musb) 1101 { 1102 struct platform_device *pdev; 1103 struct resource *mem; 1104 void __iomem *sync = NULL; 1105 int ret; 1106 1107 usb_nop_xceiv_register(); 1108 musb->xceiv = otg_get_transceiver(); 1109 if (!musb->xceiv) 1110 return -ENODEV; 1111 1112 pdev = to_platform_device(musb->controller); 1113 1114 /* dma address for async dma */ 1115 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1116 musb->async = mem->start; 1117 1118 /* dma address for sync dma */ 1119 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1120 if (!mem) { 1121 pr_debug("no sync dma resource?\n"); 1122 ret = -ENODEV; 1123 goto done; 1124 } 1125 musb->sync = mem->start; 1126 1127 sync = ioremap(mem->start, resource_size(mem)); 1128 if (!sync) { 1129 pr_debug("ioremap for sync failed\n"); 1130 ret = -ENOMEM; 1131 goto done; 1132 } 1133 musb->sync_va = sync; 1134 1135 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400, 1136 * FIFOs at 0x600, TUSB at 0x800 1137 */ 1138 musb->mregs += TUSB_BASE_OFFSET; 1139 1140 ret = tusb_musb_start(musb); 1141 if (ret) { 1142 printk(KERN_ERR "Could not start tusb6010 (%d)\n", 1143 ret); 1144 goto done; 1145 } 1146 musb->isr = tusb_musb_interrupt; 1147 1148 if (is_peripheral_enabled(musb)) { 1149 musb->xceiv->set_power = tusb_draw_power; 1150 the_musb = musb; 1151 } 1152 1153 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); 1154 1155 done: 1156 if (ret < 0) { 1157 if (sync) 1158 iounmap(sync); 1159 1160 otg_put_transceiver(musb->xceiv); 1161 usb_nop_xceiv_unregister(); 1162 } 1163 return ret; 1164 } 1165 1166 static int tusb_musb_exit(struct musb *musb) 1167 { 1168 del_timer_sync(&musb_idle_timer); 1169 the_musb = NULL; 1170 1171 if (musb->board_set_power) 1172 musb->board_set_power(0); 1173 1174 iounmap(musb->sync_va); 1175 1176 otg_put_transceiver(musb->xceiv); 1177 usb_nop_xceiv_unregister(); 1178 return 0; 1179 } 1180 1181 const struct musb_platform_ops musb_ops = { 1182 .init = tusb_musb_init, 1183 .exit = tusb_musb_exit, 1184 1185 .enable = tusb_musb_enable, 1186 .disable = tusb_musb_disable, 1187 1188 .set_mode = tusb_musb_set_mode, 1189 .try_idle = tusb_musb_try_idle, 1190 1191 .vbus_status = tusb_musb_vbus_status, 1192 .set_vbus = tusb_musb_set_vbus, 1193 }; 1194 1195 static u64 tusb_dmamask = DMA_BIT_MASK(32); 1196 1197 static int __init tusb_probe(struct platform_device *pdev) 1198 { 1199 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; 1200 struct platform_device *musb; 1201 struct tusb6010_glue *glue; 1202 1203 int ret = -ENOMEM; 1204 1205 glue = kzalloc(sizeof(*glue), GFP_KERNEL); 1206 if (!glue) { 1207 dev_err(&pdev->dev, "failed to allocate glue context\n"); 1208 goto err0; 1209 } 1210 1211 musb = platform_device_alloc("musb-hdrc", -1); 1212 if (!musb) { 1213 dev_err(&pdev->dev, "failed to allocate musb device\n"); 1214 goto err1; 1215 } 1216 1217 musb->dev.parent = &pdev->dev; 1218 musb->dev.dma_mask = &tusb_dmamask; 1219 musb->dev.coherent_dma_mask = tusb_dmamask; 1220 1221 glue->dev = &pdev->dev; 1222 glue->musb = musb; 1223 1224 platform_set_drvdata(pdev, glue); 1225 1226 ret = platform_device_add_resources(musb, pdev->resource, 1227 pdev->num_resources); 1228 if (ret) { 1229 dev_err(&pdev->dev, "failed to add resources\n"); 1230 goto err2; 1231 } 1232 1233 ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); 1234 if (ret) { 1235 dev_err(&pdev->dev, "failed to add platform_data\n"); 1236 goto err2; 1237 } 1238 1239 ret = platform_device_add(musb); 1240 if (ret) { 1241 dev_err(&pdev->dev, "failed to register musb device\n"); 1242 goto err1; 1243 } 1244 1245 return 0; 1246 1247 err2: 1248 platform_device_put(musb); 1249 1250 err1: 1251 kfree(glue); 1252 1253 err0: 1254 return ret; 1255 } 1256 1257 static int __exit tusb_remove(struct platform_device *pdev) 1258 { 1259 struct tusb6010_glue *glue = platform_get_drvdata(pdev); 1260 1261 platform_device_del(glue->musb); 1262 platform_device_put(glue->musb); 1263 kfree(glue); 1264 1265 return 0; 1266 } 1267 1268 static struct platform_driver tusb_driver = { 1269 .remove = __exit_p(tusb_remove), 1270 .driver = { 1271 .name = "musb-tusb", 1272 }, 1273 }; 1274 1275 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer"); 1276 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1277 MODULE_LICENSE("GPL v2"); 1278 1279 static int __init tusb_init(void) 1280 { 1281 return platform_driver_probe(&tusb_driver, tusb_probe); 1282 } 1283 subsys_initcall(tusb_init); 1284 1285 static void __exit tusb_exit(void) 1286 { 1287 platform_driver_unregister(&tusb_driver); 1288 } 1289 module_exit(tusb_exit); 1290