1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * xHCI host controller driver 5 * 6 * Copyright (C) 2008 Intel Corp. 7 * 8 * Author: Sarah Sharp 9 * Some code borrowed from the Linux EHCI driver. 10 */ 11 12 #ifndef __LINUX_XHCI_HCD_H 13 #define __LINUX_XHCI_HCD_H 14 15 #include <linux/usb.h> 16 #include <linux/timer.h> 17 #include <linux/kernel.h> 18 #include <linux/usb/hcd.h> 19 #include <linux/io-64-nonatomic-lo-hi.h> 20 #include <linux/io-64-nonatomic-hi-lo.h> 21 22 /* Code sharing between pci-quirks and xhci hcd */ 23 #include "xhci-ext-caps.h" 24 #include "pci-quirks.h" 25 26 /* max buffer size for trace and debug messages */ 27 #define XHCI_MSG_MAX 500 28 29 /* xHCI PCI Configuration Registers */ 30 #define XHCI_SBRN_OFFSET (0x60) 31 32 /* Max number of USB devices for any host controller - limit in section 6.1 */ 33 #define MAX_HC_SLOTS 256 34 /* Section 5.3.3 - MaxPorts */ 35 #define MAX_HC_PORTS 127 36 37 /* 38 * xHCI register interface. 39 * This corresponds to the eXtensible Host Controller Interface (xHCI) 40 * Revision 0.95 specification 41 */ 42 43 /** 44 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 45 * @hc_capbase: length of the capabilities register and HC version number 46 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 47 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 48 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 49 * @hcc_params: HCCPARAMS - Capability Parameters 50 * @db_off: DBOFF - Doorbell array offset 51 * @run_regs_off: RTSOFF - Runtime register space offset 52 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 53 */ 54 struct xhci_cap_regs { 55 __le32 hc_capbase; 56 __le32 hcs_params1; 57 __le32 hcs_params2; 58 __le32 hcs_params3; 59 __le32 hcc_params; 60 __le32 db_off; 61 __le32 run_regs_off; 62 __le32 hcc_params2; /* xhci 1.1 */ 63 /* Reserved up to (CAPLENGTH - 0x1C) */ 64 }; 65 66 /* hc_capbase bitmasks */ 67 /* bits 7:0 - how long is the Capabilities register */ 68 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 69 /* bits 31:16 */ 70 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 71 72 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 73 /* bits 0:7, Max Device Slots */ 74 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 75 #define HCS_SLOTS_MASK 0xff 76 /* bits 8:18, Max Interrupters */ 77 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 78 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 79 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 80 81 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 82 /* bits 0:3, frames or uframes that SW needs to queue transactions 83 * ahead of the HW to meet periodic deadlines */ 84 #define HCS_IST(p) (((p) >> 0) & 0xf) 85 /* bits 4:7, max number of Event Ring segments */ 86 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 87 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 88 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 89 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 90 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 91 92 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 93 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 94 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 95 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 96 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 97 98 /* HCCPARAMS - hcc_params - bitmasks */ 99 /* true: HC can use 64-bit address pointers */ 100 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 101 /* true: HC can do bandwidth negotiation */ 102 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 103 /* true: HC uses 64-byte Device Context structures 104 * FIXME 64-byte context structures aren't supported yet. 105 */ 106 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 107 /* true: HC has port power switches */ 108 #define HCC_PPC(p) ((p) & (1 << 3)) 109 /* true: HC has port indicators */ 110 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 111 /* true: HC has Light HC Reset Capability */ 112 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 113 /* true: HC supports latency tolerance messaging */ 114 #define HCC_LTC(p) ((p) & (1 << 6)) 115 /* true: no secondary Stream ID Support */ 116 #define HCC_NSS(p) ((p) & (1 << 7)) 117 /* true: HC supports Stopped - Short Packet */ 118 #define HCC_SPC(p) ((p) & (1 << 9)) 119 /* true: HC has Contiguous Frame ID Capability */ 120 #define HCC_CFC(p) ((p) & (1 << 11)) 121 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 122 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 123 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 124 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 125 126 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 127 128 /* db_off bitmask - bits 0:1 reserved */ 129 #define DBOFF_MASK (~0x3) 130 131 /* run_regs_off bitmask - bits 0:4 reserved */ 132 #define RTSOFF_MASK (~0x1f) 133 134 /* HCCPARAMS2 - hcc_params2 - bitmasks */ 135 /* true: HC supports U3 entry Capability */ 136 #define HCC2_U3C(p) ((p) & (1 << 0)) 137 /* true: HC supports Configure endpoint command Max exit latency too large */ 138 #define HCC2_CMC(p) ((p) & (1 << 1)) 139 /* true: HC supports Force Save context Capability */ 140 #define HCC2_FSC(p) ((p) & (1 << 2)) 141 /* true: HC supports Compliance Transition Capability */ 142 #define HCC2_CTC(p) ((p) & (1 << 3)) 143 /* true: HC support Large ESIT payload Capability > 48k */ 144 #define HCC2_LEC(p) ((p) & (1 << 4)) 145 /* true: HC support Configuration Information Capability */ 146 #define HCC2_CIC(p) ((p) & (1 << 5)) 147 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ 148 #define HCC2_ETC(p) ((p) & (1 << 6)) 149 150 /* Number of registers per port */ 151 #define NUM_PORT_REGS 4 152 153 #define PORTSC 0 154 #define PORTPMSC 1 155 #define PORTLI 2 156 #define PORTHLPMC 3 157 158 /** 159 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 160 * @command: USBCMD - xHC command register 161 * @status: USBSTS - xHC status register 162 * @page_size: This indicates the page size that the host controller 163 * supports. If bit n is set, the HC supports a page size 164 * of 2^(n+12), up to a 128MB page size. 165 * 4K is the minimum page size. 166 * @cmd_ring: CRP - 64-bit Command Ring Pointer 167 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 168 * @config_reg: CONFIG - Configure Register 169 * @port_status_base: PORTSCn - base address for Port Status and Control 170 * Each port has a Port Status and Control register, 171 * followed by a Port Power Management Status and Control 172 * register, a Port Link Info register, and a reserved 173 * register. 174 * @port_power_base: PORTPMSCn - base address for 175 * Port Power Management Status and Control 176 * @port_link_base: PORTLIn - base address for Port Link Info (current 177 * Link PM state and control) for USB 2.1 and USB 3.0 178 * devices. 179 */ 180 struct xhci_op_regs { 181 __le32 command; 182 __le32 status; 183 __le32 page_size; 184 __le32 reserved1; 185 __le32 reserved2; 186 __le32 dev_notification; 187 __le64 cmd_ring; 188 /* rsvd: offset 0x20-2F */ 189 __le32 reserved3[4]; 190 __le64 dcbaa_ptr; 191 __le32 config_reg; 192 /* rsvd: offset 0x3C-3FF */ 193 __le32 reserved4[241]; 194 /* port 1 registers, which serve as a base address for other ports */ 195 __le32 port_status_base; 196 __le32 port_power_base; 197 __le32 port_link_base; 198 __le32 reserved5; 199 /* registers for ports 2-255 */ 200 __le32 reserved6[NUM_PORT_REGS*254]; 201 }; 202 203 /* USBCMD - USB command - command bitmasks */ 204 /* start/stop HC execution - do not write unless HC is halted*/ 205 #define CMD_RUN XHCI_CMD_RUN 206 /* Reset HC - resets internal HC state machine and all registers (except 207 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 208 * The xHCI driver must reinitialize the xHC after setting this bit. 209 */ 210 #define CMD_RESET (1 << 1) 211 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 212 #define CMD_EIE XHCI_CMD_EIE 213 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 214 #define CMD_HSEIE XHCI_CMD_HSEIE 215 /* bits 4:6 are reserved (and should be preserved on writes). */ 216 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 217 #define CMD_LRESET (1 << 7) 218 /* host controller save/restore state. */ 219 #define CMD_CSS (1 << 8) 220 #define CMD_CRS (1 << 9) 221 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 222 #define CMD_EWE XHCI_CMD_EWE 223 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 224 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 225 * '0' means the xHC can power it off if all ports are in the disconnect, 226 * disabled, or powered-off state. 227 */ 228 #define CMD_PM_INDEX (1 << 11) 229 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 230 #define CMD_ETE (1 << 14) 231 /* bits 15:31 are reserved (and should be preserved on writes). */ 232 233 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000) 234 #define XHCI_RESET_SHORT_USEC (250 * 1000) 235 236 /* IMAN - Interrupt Management Register */ 237 #define IMAN_IE (1 << 1) 238 #define IMAN_IP (1 << 0) 239 240 /* USBSTS - USB status - status bitmasks */ 241 /* HC not running - set to 1 when run/stop bit is cleared. */ 242 #define STS_HALT XHCI_STS_HALT 243 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 244 #define STS_FATAL (1 << 2) 245 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 246 #define STS_EINT (1 << 3) 247 /* port change detect */ 248 #define STS_PORT (1 << 4) 249 /* bits 5:7 reserved and zeroed */ 250 /* save state status - '1' means xHC is saving state */ 251 #define STS_SAVE (1 << 8) 252 /* restore state status - '1' means xHC is restoring state */ 253 #define STS_RESTORE (1 << 9) 254 /* true: save or restore error */ 255 #define STS_SRE (1 << 10) 256 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 257 #define STS_CNR XHCI_STS_CNR 258 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 259 #define STS_HCE (1 << 12) 260 /* bits 13:31 reserved and should be preserved */ 261 262 /* 263 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 264 * Generate a device notification event when the HC sees a transaction with a 265 * notification type that matches a bit set in this bit field. 266 */ 267 #define DEV_NOTE_MASK (0xffff) 268 #define ENABLE_DEV_NOTE(x) (1 << (x)) 269 /* Most of the device notification types should only be used for debug. 270 * SW does need to pay attention to function wake notifications. 271 */ 272 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 273 274 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 275 /* bit 0 is the command ring cycle state */ 276 /* stop ring operation after completion of the currently executing command */ 277 #define CMD_RING_PAUSE (1 << 1) 278 /* stop ring immediately - abort the currently executing command */ 279 #define CMD_RING_ABORT (1 << 2) 280 /* true: command ring is running */ 281 #define CMD_RING_RUNNING (1 << 3) 282 /* bits 4:5 reserved and should be preserved */ 283 /* Command Ring pointer - bit mask for the lower 32 bits. */ 284 #define CMD_RING_RSVD_BITS (0x3f) 285 286 /* CONFIG - Configure Register - config_reg bitmasks */ 287 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 288 #define MAX_DEVS(p) ((p) & 0xff) 289 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 290 #define CONFIG_U3E (1 << 8) 291 /* bit 9: Configuration Information Enable, xhci 1.1 */ 292 #define CONFIG_CIE (1 << 9) 293 /* bits 10:31 - reserved and should be preserved */ 294 295 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 296 /* true: device connected */ 297 #define PORT_CONNECT (1 << 0) 298 /* true: port enabled */ 299 #define PORT_PE (1 << 1) 300 /* bit 2 reserved and zeroed */ 301 /* true: port has an over-current condition */ 302 #define PORT_OC (1 << 3) 303 /* true: port reset signaling asserted */ 304 #define PORT_RESET (1 << 4) 305 /* Port Link State - bits 5:8 306 * A read gives the current link PM state of the port, 307 * a write with Link State Write Strobe set sets the link state. 308 */ 309 #define PORT_PLS_MASK (0xf << 5) 310 #define XDEV_U0 (0x0 << 5) 311 #define XDEV_U1 (0x1 << 5) 312 #define XDEV_U2 (0x2 << 5) 313 #define XDEV_U3 (0x3 << 5) 314 #define XDEV_DISABLED (0x4 << 5) 315 #define XDEV_RXDETECT (0x5 << 5) 316 #define XDEV_INACTIVE (0x6 << 5) 317 #define XDEV_POLLING (0x7 << 5) 318 #define XDEV_RECOVERY (0x8 << 5) 319 #define XDEV_HOT_RESET (0x9 << 5) 320 #define XDEV_COMP_MODE (0xa << 5) 321 #define XDEV_TEST_MODE (0xb << 5) 322 #define XDEV_RESUME (0xf << 5) 323 324 /* true: port has power (see HCC_PPC) */ 325 #define PORT_POWER (1 << 9) 326 /* bits 10:13 indicate device speed: 327 * 0 - undefined speed - port hasn't be initialized by a reset yet 328 * 1 - full speed 329 * 2 - low speed 330 * 3 - high speed 331 * 4 - super speed 332 * 5-15 reserved 333 */ 334 #define DEV_SPEED_MASK (0xf << 10) 335 #define XDEV_FS (0x1 << 10) 336 #define XDEV_LS (0x2 << 10) 337 #define XDEV_HS (0x3 << 10) 338 #define XDEV_SS (0x4 << 10) 339 #define XDEV_SSP (0x5 << 10) 340 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 341 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 342 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 343 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 344 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 345 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP) 346 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS) 347 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f) 348 349 /* Bits 20:23 in the Slot Context are the speed for the device */ 350 #define SLOT_SPEED_FS (XDEV_FS << 10) 351 #define SLOT_SPEED_LS (XDEV_LS << 10) 352 #define SLOT_SPEED_HS (XDEV_HS << 10) 353 #define SLOT_SPEED_SS (XDEV_SS << 10) 354 #define SLOT_SPEED_SSP (XDEV_SSP << 10) 355 /* Port Indicator Control */ 356 #define PORT_LED_OFF (0 << 14) 357 #define PORT_LED_AMBER (1 << 14) 358 #define PORT_LED_GREEN (2 << 14) 359 #define PORT_LED_MASK (3 << 14) 360 /* Port Link State Write Strobe - set this when changing link state */ 361 #define PORT_LINK_STROBE (1 << 16) 362 /* true: connect status change */ 363 #define PORT_CSC (1 << 17) 364 /* true: port enable change */ 365 #define PORT_PEC (1 << 18) 366 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 367 * into an enabled state, and the device into the default state. A "warm" reset 368 * also resets the link, forcing the device through the link training sequence. 369 * SW can also look at the Port Reset register to see when warm reset is done. 370 */ 371 #define PORT_WRC (1 << 19) 372 /* true: over-current change */ 373 #define PORT_OCC (1 << 20) 374 /* true: reset change - 1 to 0 transition of PORT_RESET */ 375 #define PORT_RC (1 << 21) 376 /* port link status change - set on some port link state transitions: 377 * Transition Reason 378 * ------------------------------------------------------------------------------ 379 * - U3 to Resume Wakeup signaling from a device 380 * - Resume to Recovery to U0 USB 3.0 device resume 381 * - Resume to U0 USB 2.0 device resume 382 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 383 * - U3 to U0 Software resume of USB 2.0 device complete 384 * - U2 to U0 L1 resume of USB 2.1 device complete 385 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 386 * - U0 to disabled L1 entry error with USB 2.1 device 387 * - Any state to inactive Error on USB 3.0 port 388 */ 389 #define PORT_PLC (1 << 22) 390 /* port configure error change - port failed to configure its link partner */ 391 #define PORT_CEC (1 << 23) 392 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 393 PORT_RC | PORT_PLC | PORT_CEC) 394 395 396 /* Cold Attach Status - xHC can set this bit to report device attached during 397 * Sx state. Warm port reset should be perfomed to clear this bit and move port 398 * to connected state. 399 */ 400 #define PORT_CAS (1 << 24) 401 /* wake on connect (enable) */ 402 #define PORT_WKCONN_E (1 << 25) 403 /* wake on disconnect (enable) */ 404 #define PORT_WKDISC_E (1 << 26) 405 /* wake on over-current (enable) */ 406 #define PORT_WKOC_E (1 << 27) 407 /* bits 28:29 reserved */ 408 /* true: device is non-removable - for USB 3.0 roothub emulation */ 409 #define PORT_DEV_REMOVE (1 << 30) 410 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 411 #define PORT_WR (1 << 31) 412 413 /* We mark duplicate entries with -1 */ 414 #define DUPLICATE_ENTRY ((u8)(-1)) 415 416 /* Port Power Management Status and Control - port_power_base bitmasks */ 417 /* Inactivity timer value for transitions into U1, in microseconds. 418 * Timeout can be up to 127us. 0xFF means an infinite timeout. 419 */ 420 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 421 #define PORT_U1_TIMEOUT_MASK 0xff 422 /* Inactivity timer value for transitions into U2 */ 423 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 424 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 425 /* Bits 24:31 for port testing */ 426 427 /* USB2 Protocol PORTSPMSC */ 428 #define PORT_L1S_MASK 7 429 #define PORT_L1S_SUCCESS 1 430 #define PORT_RWE (1 << 3) 431 #define PORT_HIRD(p) (((p) & 0xf) << 4) 432 #define PORT_HIRD_MASK (0xf << 4) 433 #define PORT_L1DS_MASK (0xff << 8) 434 #define PORT_L1DS(p) (((p) & 0xff) << 8) 435 #define PORT_HLE (1 << 16) 436 #define PORT_TEST_MODE_SHIFT 28 437 438 /* USB3 Protocol PORTLI Port Link Information */ 439 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) 440 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf) 441 442 /* USB2 Protocol PORTHLPMC */ 443 #define PORT_HIRDM(p)((p) & 3) 444 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 445 #define PORT_BESLD(p)(((p) & 0xf) << 10) 446 447 /* use 512 microseconds as USB2 LPM L1 default timeout. */ 448 #define XHCI_L1_TIMEOUT 512 449 450 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 451 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 452 * by other operating systems. 453 * 454 * XHCI 1.0 errata 8/14/12 Table 13 notes: 455 * "Software should choose xHC BESL/BESLD field values that do not violate a 456 * device's resume latency requirements, 457 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 458 * or not program values < '4' if BLC = '0' and a BESL device is attached. 459 */ 460 #define XHCI_DEFAULT_BESL 4 461 462 /* 463 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports 464 * to complete link training. usually link trainig completes much faster 465 * so check status 10 times with 36ms sleep in places we need to wait for 466 * polling to complete. 467 */ 468 #define XHCI_PORT_POLLING_LFPS_TIME 36 469 470 /** 471 * struct xhci_intr_reg - Interrupt Register Set 472 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 473 * interrupts and check for pending interrupts. 474 * @irq_control: IMOD - Interrupt Moderation Register. 475 * Used to throttle interrupts. 476 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 477 * @erst_base: ERST base address. 478 * @erst_dequeue: Event ring dequeue pointer. 479 * 480 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 481 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 482 * multiple segments of the same size. The HC places events on the ring and 483 * "updates the Cycle bit in the TRBs to indicate to software the current 484 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 485 * updates the dequeue pointer. 486 */ 487 struct xhci_intr_reg { 488 __le32 irq_pending; 489 __le32 irq_control; 490 __le32 erst_size; 491 __le32 rsvd; 492 __le64 erst_base; 493 __le64 erst_dequeue; 494 }; 495 496 /* irq_pending bitmasks */ 497 #define ER_IRQ_PENDING(p) ((p) & 0x1) 498 /* bits 2:31 need to be preserved */ 499 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 500 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 501 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 502 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 503 504 /* irq_control bitmasks */ 505 /* Minimum interval between interrupts (in 250ns intervals). The interval 506 * between interrupts will be longer if there are no events on the event ring. 507 * Default is 4000 (1 ms). 508 */ 509 #define ER_IRQ_INTERVAL_MASK (0xffff) 510 /* Counter used to count down the time to the next interrupt - HW use only */ 511 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 512 513 /* erst_size bitmasks */ 514 /* Preserve bits 16:31 of erst_size */ 515 #define ERST_SIZE_MASK (0xffff << 16) 516 517 /* erst_base bitmasks */ 518 #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0)) 519 520 /* erst_dequeue bitmasks */ 521 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 522 * where the current dequeue pointer lies. This is an optional HW hint. 523 */ 524 #define ERST_DESI_MASK (0x7) 525 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 526 * a work queue (or delayed service routine)? 527 */ 528 #define ERST_EHB (1 << 3) 529 #define ERST_PTR_MASK (0xf) 530 531 /** 532 * struct xhci_run_regs 533 * @microframe_index: 534 * MFINDEX - current microframe number 535 * 536 * Section 5.5 Host Controller Runtime Registers: 537 * "Software should read and write these registers using only Dword (32 bit) 538 * or larger accesses" 539 */ 540 struct xhci_run_regs { 541 __le32 microframe_index; 542 __le32 rsvd[7]; 543 struct xhci_intr_reg ir_set[128]; 544 }; 545 546 /** 547 * struct doorbell_array 548 * 549 * Bits 0 - 7: Endpoint target 550 * Bits 8 - 15: RsvdZ 551 * Bits 16 - 31: Stream ID 552 * 553 * Section 5.6 554 */ 555 struct xhci_doorbell_array { 556 __le32 doorbell[256]; 557 }; 558 559 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 560 #define DB_VALUE_HOST 0x00000000 561 562 /** 563 * struct xhci_protocol_caps 564 * @revision: major revision, minor revision, capability ID, 565 * and next capability pointer. 566 * @name_string: Four ASCII characters to say which spec this xHC 567 * follows, typically "USB ". 568 * @port_info: Port offset, count, and protocol-defined information. 569 */ 570 struct xhci_protocol_caps { 571 u32 revision; 572 u32 name_string; 573 u32 port_info; 574 }; 575 576 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 577 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff) 578 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f) 579 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 580 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 581 582 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f) 583 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03) 584 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03) 585 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01) 586 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03) 587 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff) 588 589 #define PLT_MASK (0x03 << 6) 590 #define PLT_SYM (0x00 << 6) 591 #define PLT_ASYM_RX (0x02 << 6) 592 #define PLT_ASYM_TX (0x03 << 6) 593 594 /** 595 * struct xhci_container_ctx 596 * @type: Type of context. Used to calculated offsets to contained contexts. 597 * @size: Size of the context data 598 * @bytes: The raw context data given to HW 599 * @dma: dma address of the bytes 600 * 601 * Represents either a Device or Input context. Holds a pointer to the raw 602 * memory used for the context (bytes) and dma address of it (dma). 603 */ 604 struct xhci_container_ctx { 605 unsigned type; 606 #define XHCI_CTX_TYPE_DEVICE 0x1 607 #define XHCI_CTX_TYPE_INPUT 0x2 608 609 int size; 610 611 u8 *bytes; 612 dma_addr_t dma; 613 }; 614 615 /** 616 * struct xhci_slot_ctx 617 * @dev_info: Route string, device speed, hub info, and last valid endpoint 618 * @dev_info2: Max exit latency for device number, root hub port number 619 * @tt_info: tt_info is used to construct split transaction tokens 620 * @dev_state: slot state and device address 621 * 622 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 623 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 624 * reserved at the end of the slot context for HC internal use. 625 */ 626 struct xhci_slot_ctx { 627 __le32 dev_info; 628 __le32 dev_info2; 629 __le32 tt_info; 630 __le32 dev_state; 631 /* offset 0x10 to 0x1f reserved for HC internal use */ 632 __le32 reserved[4]; 633 }; 634 635 /* dev_info bitmasks */ 636 /* Route String - 0:19 */ 637 #define ROUTE_STRING_MASK (0xfffff) 638 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 639 #define DEV_SPEED (0xf << 20) 640 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 641 /* bit 24 reserved */ 642 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 643 #define DEV_MTT (0x1 << 25) 644 /* Set if the device is a hub - bit 26 */ 645 #define DEV_HUB (0x1 << 26) 646 /* Index of the last valid endpoint context in this device context - 27:31 */ 647 #define LAST_CTX_MASK (0x1f << 27) 648 #define LAST_CTX(p) ((p) << 27) 649 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 650 #define SLOT_FLAG (1 << 0) 651 #define EP0_FLAG (1 << 1) 652 653 /* dev_info2 bitmasks */ 654 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 655 #define MAX_EXIT (0xffff) 656 /* Root hub port number that is needed to access the USB device */ 657 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 658 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 659 /* Maximum number of ports under a hub device */ 660 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 661 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 662 663 /* tt_info bitmasks */ 664 /* 665 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 666 * The Slot ID of the hub that isolates the high speed signaling from 667 * this low or full-speed device. '0' if attached to root hub port. 668 */ 669 #define TT_SLOT (0xff) 670 /* 671 * The number of the downstream facing port of the high-speed hub 672 * '0' if the device is not low or full speed. 673 */ 674 #define TT_PORT (0xff << 8) 675 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 676 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 677 678 /* dev_state bitmasks */ 679 /* USB device address - assigned by the HC */ 680 #define DEV_ADDR_MASK (0xff) 681 /* bits 8:26 reserved */ 682 /* Slot state */ 683 #define SLOT_STATE (0x1f << 27) 684 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 685 686 #define SLOT_STATE_DISABLED 0 687 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 688 #define SLOT_STATE_DEFAULT 1 689 #define SLOT_STATE_ADDRESSED 2 690 #define SLOT_STATE_CONFIGURED 3 691 692 /** 693 * struct xhci_ep_ctx 694 * @ep_info: endpoint state, streams, mult, and interval information. 695 * @ep_info2: information on endpoint type, max packet size, max burst size, 696 * error count, and whether the HC will force an event for all 697 * transactions. 698 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 699 * defines one stream, this points to the endpoint transfer ring. 700 * Otherwise, it points to a stream context array, which has a 701 * ring pointer for each flow. 702 * @tx_info: 703 * Average TRB lengths for the endpoint ring and 704 * max payload within an Endpoint Service Interval Time (ESIT). 705 * 706 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 707 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 708 * reserved at the end of the endpoint context for HC internal use. 709 */ 710 struct xhci_ep_ctx { 711 __le32 ep_info; 712 __le32 ep_info2; 713 __le64 deq; 714 __le32 tx_info; 715 /* offset 0x14 - 0x1f reserved for HC internal use */ 716 __le32 reserved[3]; 717 }; 718 719 /* ep_info bitmasks */ 720 /* 721 * Endpoint State - bits 0:2 722 * 0 - disabled 723 * 1 - running 724 * 2 - halted due to halt condition - ok to manipulate endpoint ring 725 * 3 - stopped 726 * 4 - TRB error 727 * 5-7 - reserved 728 */ 729 #define EP_STATE_MASK (0x7) 730 #define EP_STATE_DISABLED 0 731 #define EP_STATE_RUNNING 1 732 #define EP_STATE_HALTED 2 733 #define EP_STATE_STOPPED 3 734 #define EP_STATE_ERROR 4 735 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 736 737 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 738 #define EP_MULT(p) (((p) & 0x3) << 8) 739 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 740 /* bits 10:14 are Max Primary Streams */ 741 /* bit 15 is Linear Stream Array */ 742 /* Interval - period between requests to an endpoint - 125u increments. */ 743 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 744 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 745 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 746 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 747 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 748 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 749 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 750 #define EP_HAS_LSA (1 << 15) 751 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 752 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 753 754 /* ep_info2 bitmasks */ 755 /* 756 * Force Event - generate transfer events for all TRBs for this endpoint 757 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 758 */ 759 #define FORCE_EVENT (0x1) 760 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 761 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 762 #define EP_TYPE(p) ((p) << 3) 763 #define ISOC_OUT_EP 1 764 #define BULK_OUT_EP 2 765 #define INT_OUT_EP 3 766 #define CTRL_EP 4 767 #define ISOC_IN_EP 5 768 #define BULK_IN_EP 6 769 #define INT_IN_EP 7 770 /* bit 6 reserved */ 771 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 772 #define MAX_BURST(p) (((p)&0xff) << 8) 773 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 774 #define MAX_PACKET(p) (((p)&0xffff) << 16) 775 #define MAX_PACKET_MASK (0xffff << 16) 776 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 777 778 /* tx_info bitmasks */ 779 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 780 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 781 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 782 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 783 784 /* deq bitmasks */ 785 #define EP_CTX_CYCLE_MASK (1 << 0) 786 #define SCTX_DEQ_MASK (~0xfL) 787 788 789 /** 790 * struct xhci_input_control_context 791 * Input control context; see section 6.2.5. 792 * 793 * @drop_context: set the bit of the endpoint context you want to disable 794 * @add_context: set the bit of the endpoint context you want to enable 795 */ 796 struct xhci_input_control_ctx { 797 __le32 drop_flags; 798 __le32 add_flags; 799 __le32 rsvd2[6]; 800 }; 801 802 #define EP_IS_ADDED(ctrl_ctx, i) \ 803 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 804 #define EP_IS_DROPPED(ctrl_ctx, i) \ 805 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 806 807 /* Represents everything that is needed to issue a command on the command ring. 808 * It's useful to pre-allocate these for commands that cannot fail due to 809 * out-of-memory errors, like freeing streams. 810 */ 811 struct xhci_command { 812 /* Input context for changing device state */ 813 struct xhci_container_ctx *in_ctx; 814 u32 status; 815 int slot_id; 816 /* If completion is null, no one is waiting on this command 817 * and the structure can be freed after the command completes. 818 */ 819 struct completion *completion; 820 union xhci_trb *command_trb; 821 struct list_head cmd_list; 822 /* xHCI command response timeout in milliseconds */ 823 unsigned int timeout_ms; 824 }; 825 826 /* drop context bitmasks */ 827 #define DROP_EP(x) (0x1 << x) 828 /* add context bitmasks */ 829 #define ADD_EP(x) (0x1 << x) 830 831 struct xhci_stream_ctx { 832 /* 64-bit stream ring address, cycle state, and stream type */ 833 __le64 stream_ring; 834 /* offset 0x14 - 0x1f reserved for HC internal use */ 835 __le32 reserved[2]; 836 }; 837 838 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 839 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 840 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 841 #define SCT_SEC_TR 0 842 /* Primary stream array type, dequeue pointer is to a transfer ring */ 843 #define SCT_PRI_TR 1 844 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 845 #define SCT_SSA_8 2 846 #define SCT_SSA_16 3 847 #define SCT_SSA_32 4 848 #define SCT_SSA_64 5 849 #define SCT_SSA_128 6 850 #define SCT_SSA_256 7 851 852 /* Assume no secondary streams for now */ 853 struct xhci_stream_info { 854 struct xhci_ring **stream_rings; 855 /* Number of streams, including stream 0 (which drivers can't use) */ 856 unsigned int num_streams; 857 /* The stream context array may be bigger than 858 * the number of streams the driver asked for 859 */ 860 struct xhci_stream_ctx *stream_ctx_array; 861 unsigned int num_stream_ctxs; 862 dma_addr_t ctx_array_dma; 863 /* For mapping physical TRB addresses to segments in stream rings */ 864 struct radix_tree_root trb_address_map; 865 struct xhci_command *free_streams_command; 866 }; 867 868 #define SMALL_STREAM_ARRAY_SIZE 256 869 #define MEDIUM_STREAM_ARRAY_SIZE 1024 870 871 /* Some Intel xHCI host controllers need software to keep track of the bus 872 * bandwidth. Keep track of endpoint info here. Each root port is allocated 873 * the full bus bandwidth. We must also treat TTs (including each port under a 874 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 875 * (DMI) also limits the total bandwidth (across all domains) that can be used. 876 */ 877 struct xhci_bw_info { 878 /* ep_interval is zero-based */ 879 unsigned int ep_interval; 880 /* mult and num_packets are one-based */ 881 unsigned int mult; 882 unsigned int num_packets; 883 unsigned int max_packet_size; 884 unsigned int max_esit_payload; 885 unsigned int type; 886 }; 887 888 /* "Block" sizes in bytes the hardware uses for different device speeds. 889 * The logic in this part of the hardware limits the number of bits the hardware 890 * can use, so must represent bandwidth in a less precise manner to mimic what 891 * the scheduler hardware computes. 892 */ 893 #define FS_BLOCK 1 894 #define HS_BLOCK 4 895 #define SS_BLOCK 16 896 #define DMI_BLOCK 32 897 898 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 899 * with each byte transferred. SuperSpeed devices have an initial overhead to 900 * set up bursts. These are in blocks, see above. LS overhead has already been 901 * translated into FS blocks. 902 */ 903 #define DMI_OVERHEAD 8 904 #define DMI_OVERHEAD_BURST 4 905 #define SS_OVERHEAD 8 906 #define SS_OVERHEAD_BURST 32 907 #define HS_OVERHEAD 26 908 #define FS_OVERHEAD 20 909 #define LS_OVERHEAD 128 910 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 911 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 912 * of overhead associated with split transfers crossing microframe boundaries. 913 * 31 blocks is pure protocol overhead. 914 */ 915 #define TT_HS_OVERHEAD (31 + 94) 916 #define TT_DMI_OVERHEAD (25 + 12) 917 918 /* Bandwidth limits in blocks */ 919 #define FS_BW_LIMIT 1285 920 #define TT_BW_LIMIT 1320 921 #define HS_BW_LIMIT 1607 922 #define SS_BW_LIMIT_IN 3906 923 #define DMI_BW_LIMIT_IN 3906 924 #define SS_BW_LIMIT_OUT 3906 925 #define DMI_BW_LIMIT_OUT 3906 926 927 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 928 #define FS_BW_RESERVED 10 929 #define HS_BW_RESERVED 20 930 #define SS_BW_RESERVED 10 931 932 struct xhci_virt_ep { 933 struct xhci_virt_device *vdev; /* parent */ 934 unsigned int ep_index; 935 struct xhci_ring *ring; 936 /* Related to endpoints that are configured to use stream IDs only */ 937 struct xhci_stream_info *stream_info; 938 /* Temporary storage in case the configure endpoint command fails and we 939 * have to restore the device state to the previous state 940 */ 941 struct xhci_ring *new_ring; 942 unsigned int err_count; 943 unsigned int ep_state; 944 #define SET_DEQ_PENDING (1 << 0) 945 #define EP_HALTED (1 << 1) /* For stall handling */ 946 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 947 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 948 #define EP_GETTING_STREAMS (1 << 3) 949 #define EP_HAS_STREAMS (1 << 4) 950 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 951 #define EP_GETTING_NO_STREAMS (1 << 5) 952 #define EP_HARD_CLEAR_TOGGLE (1 << 6) 953 #define EP_SOFT_CLEAR_TOGGLE (1 << 7) 954 /* usb_hub_clear_tt_buffer is in progress */ 955 #define EP_CLEARING_TT (1 << 8) 956 /* ---- Related to URB cancellation ---- */ 957 struct list_head cancelled_td_list; 958 struct xhci_hcd *xhci; 959 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 960 * command. We'll need to update the ring's dequeue segment and dequeue 961 * pointer after the command completes. 962 */ 963 struct xhci_segment *queued_deq_seg; 964 union xhci_trb *queued_deq_ptr; 965 /* 966 * Sometimes the xHC can not process isochronous endpoint ring quickly 967 * enough, and it will miss some isoc tds on the ring and generate 968 * a Missed Service Error Event. 969 * Set skip flag when receive a Missed Service Error Event and 970 * process the missed tds on the endpoint ring. 971 */ 972 bool skip; 973 /* Bandwidth checking storage */ 974 struct xhci_bw_info bw_info; 975 struct list_head bw_endpoint_list; 976 /* Isoch Frame ID checking storage */ 977 int next_frame_id; 978 /* Use new Isoch TRB layout needed for extended TBC support */ 979 bool use_extended_tbc; 980 }; 981 982 enum xhci_overhead_type { 983 LS_OVERHEAD_TYPE = 0, 984 FS_OVERHEAD_TYPE, 985 HS_OVERHEAD_TYPE, 986 }; 987 988 struct xhci_interval_bw { 989 unsigned int num_packets; 990 /* Sorted by max packet size. 991 * Head of the list is the greatest max packet size. 992 */ 993 struct list_head endpoints; 994 /* How many endpoints of each speed are present. */ 995 unsigned int overhead[3]; 996 }; 997 998 #define XHCI_MAX_INTERVAL 16 999 1000 struct xhci_interval_bw_table { 1001 unsigned int interval0_esit_payload; 1002 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 1003 /* Includes reserved bandwidth for async endpoints */ 1004 unsigned int bw_used; 1005 unsigned int ss_bw_in; 1006 unsigned int ss_bw_out; 1007 }; 1008 1009 #define EP_CTX_PER_DEV 31 1010 1011 struct xhci_virt_device { 1012 int slot_id; 1013 struct usb_device *udev; 1014 /* 1015 * Commands to the hardware are passed an "input context" that 1016 * tells the hardware what to change in its data structures. 1017 * The hardware will return changes in an "output context" that 1018 * software must allocate for the hardware. We need to keep 1019 * track of input and output contexts separately because 1020 * these commands might fail and we don't trust the hardware. 1021 */ 1022 struct xhci_container_ctx *out_ctx; 1023 /* Used for addressing devices and configuration changes */ 1024 struct xhci_container_ctx *in_ctx; 1025 struct xhci_virt_ep eps[EP_CTX_PER_DEV]; 1026 u8 fake_port; 1027 u8 real_port; 1028 struct xhci_interval_bw_table *bw_table; 1029 struct xhci_tt_bw_info *tt_info; 1030 /* 1031 * flags for state tracking based on events and issued commands. 1032 * Software can not rely on states from output contexts because of 1033 * latency between events and xHC updating output context values. 1034 * See xhci 1.1 section 4.8.3 for more details 1035 */ 1036 unsigned long flags; 1037 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */ 1038 1039 /* The current max exit latency for the enabled USB3 link states. */ 1040 u16 current_mel; 1041 /* Used for the debugfs interfaces. */ 1042 void *debugfs_private; 1043 }; 1044 1045 /* 1046 * For each roothub, keep track of the bandwidth information for each periodic 1047 * interval. 1048 * 1049 * If a high speed hub is attached to the roothub, each TT associated with that 1050 * hub is a separate bandwidth domain. The interval information for the 1051 * endpoints on the devices under that TT will appear in the TT structure. 1052 */ 1053 struct xhci_root_port_bw_info { 1054 struct list_head tts; 1055 unsigned int num_active_tts; 1056 struct xhci_interval_bw_table bw_table; 1057 }; 1058 1059 struct xhci_tt_bw_info { 1060 struct list_head tt_list; 1061 int slot_id; 1062 int ttport; 1063 struct xhci_interval_bw_table bw_table; 1064 int active_eps; 1065 }; 1066 1067 1068 /** 1069 * struct xhci_device_context_array 1070 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 1071 */ 1072 struct xhci_device_context_array { 1073 /* 64-bit device addresses; we only write 32-bit addresses */ 1074 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 1075 /* private xHCD pointers */ 1076 dma_addr_t dma; 1077 }; 1078 /* TODO: write function to set the 64-bit device DMA address */ 1079 /* 1080 * TODO: change this to be dynamically sized at HC mem init time since the HC 1081 * might not be able to handle the maximum number of devices possible. 1082 */ 1083 1084 1085 struct xhci_transfer_event { 1086 /* 64-bit buffer address, or immediate data */ 1087 __le64 buffer; 1088 __le32 transfer_len; 1089 /* This field is interpreted differently based on the type of TRB */ 1090 __le32 flags; 1091 }; 1092 1093 /* Transfer event TRB length bit mask */ 1094 /* bits 0:23 */ 1095 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1096 1097 /** Transfer Event bit fields **/ 1098 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1099 1100 /* Completion Code - only applicable for some types of TRBs */ 1101 #define COMP_CODE_MASK (0xff << 24) 1102 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1103 #define COMP_INVALID 0 1104 #define COMP_SUCCESS 1 1105 #define COMP_DATA_BUFFER_ERROR 2 1106 #define COMP_BABBLE_DETECTED_ERROR 3 1107 #define COMP_USB_TRANSACTION_ERROR 4 1108 #define COMP_TRB_ERROR 5 1109 #define COMP_STALL_ERROR 6 1110 #define COMP_RESOURCE_ERROR 7 1111 #define COMP_BANDWIDTH_ERROR 8 1112 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 1113 #define COMP_INVALID_STREAM_TYPE_ERROR 10 1114 #define COMP_SLOT_NOT_ENABLED_ERROR 11 1115 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 1116 #define COMP_SHORT_PACKET 13 1117 #define COMP_RING_UNDERRUN 14 1118 #define COMP_RING_OVERRUN 15 1119 #define COMP_VF_EVENT_RING_FULL_ERROR 16 1120 #define COMP_PARAMETER_ERROR 17 1121 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 1122 #define COMP_CONTEXT_STATE_ERROR 19 1123 #define COMP_NO_PING_RESPONSE_ERROR 20 1124 #define COMP_EVENT_RING_FULL_ERROR 21 1125 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 1126 #define COMP_MISSED_SERVICE_ERROR 23 1127 #define COMP_COMMAND_RING_STOPPED 24 1128 #define COMP_COMMAND_ABORTED 25 1129 #define COMP_STOPPED 26 1130 #define COMP_STOPPED_LENGTH_INVALID 27 1131 #define COMP_STOPPED_SHORT_PACKET 28 1132 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 1133 #define COMP_ISOCH_BUFFER_OVERRUN 31 1134 #define COMP_EVENT_LOST_ERROR 32 1135 #define COMP_UNDEFINED_ERROR 33 1136 #define COMP_INVALID_STREAM_ID_ERROR 34 1137 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 1138 #define COMP_SPLIT_TRANSACTION_ERROR 36 1139 1140 static inline const char *xhci_trb_comp_code_string(u8 status) 1141 { 1142 switch (status) { 1143 case COMP_INVALID: 1144 return "Invalid"; 1145 case COMP_SUCCESS: 1146 return "Success"; 1147 case COMP_DATA_BUFFER_ERROR: 1148 return "Data Buffer Error"; 1149 case COMP_BABBLE_DETECTED_ERROR: 1150 return "Babble Detected"; 1151 case COMP_USB_TRANSACTION_ERROR: 1152 return "USB Transaction Error"; 1153 case COMP_TRB_ERROR: 1154 return "TRB Error"; 1155 case COMP_STALL_ERROR: 1156 return "Stall Error"; 1157 case COMP_RESOURCE_ERROR: 1158 return "Resource Error"; 1159 case COMP_BANDWIDTH_ERROR: 1160 return "Bandwidth Error"; 1161 case COMP_NO_SLOTS_AVAILABLE_ERROR: 1162 return "No Slots Available Error"; 1163 case COMP_INVALID_STREAM_TYPE_ERROR: 1164 return "Invalid Stream Type Error"; 1165 case COMP_SLOT_NOT_ENABLED_ERROR: 1166 return "Slot Not Enabled Error"; 1167 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 1168 return "Endpoint Not Enabled Error"; 1169 case COMP_SHORT_PACKET: 1170 return "Short Packet"; 1171 case COMP_RING_UNDERRUN: 1172 return "Ring Underrun"; 1173 case COMP_RING_OVERRUN: 1174 return "Ring Overrun"; 1175 case COMP_VF_EVENT_RING_FULL_ERROR: 1176 return "VF Event Ring Full Error"; 1177 case COMP_PARAMETER_ERROR: 1178 return "Parameter Error"; 1179 case COMP_BANDWIDTH_OVERRUN_ERROR: 1180 return "Bandwidth Overrun Error"; 1181 case COMP_CONTEXT_STATE_ERROR: 1182 return "Context State Error"; 1183 case COMP_NO_PING_RESPONSE_ERROR: 1184 return "No Ping Response Error"; 1185 case COMP_EVENT_RING_FULL_ERROR: 1186 return "Event Ring Full Error"; 1187 case COMP_INCOMPATIBLE_DEVICE_ERROR: 1188 return "Incompatible Device Error"; 1189 case COMP_MISSED_SERVICE_ERROR: 1190 return "Missed Service Error"; 1191 case COMP_COMMAND_RING_STOPPED: 1192 return "Command Ring Stopped"; 1193 case COMP_COMMAND_ABORTED: 1194 return "Command Aborted"; 1195 case COMP_STOPPED: 1196 return "Stopped"; 1197 case COMP_STOPPED_LENGTH_INVALID: 1198 return "Stopped - Length Invalid"; 1199 case COMP_STOPPED_SHORT_PACKET: 1200 return "Stopped - Short Packet"; 1201 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 1202 return "Max Exit Latency Too Large Error"; 1203 case COMP_ISOCH_BUFFER_OVERRUN: 1204 return "Isoch Buffer Overrun"; 1205 case COMP_EVENT_LOST_ERROR: 1206 return "Event Lost Error"; 1207 case COMP_UNDEFINED_ERROR: 1208 return "Undefined Error"; 1209 case COMP_INVALID_STREAM_ID_ERROR: 1210 return "Invalid Stream ID Error"; 1211 case COMP_SECONDARY_BANDWIDTH_ERROR: 1212 return "Secondary Bandwidth Error"; 1213 case COMP_SPLIT_TRANSACTION_ERROR: 1214 return "Split Transaction Error"; 1215 default: 1216 return "Unknown!!"; 1217 } 1218 } 1219 1220 struct xhci_link_trb { 1221 /* 64-bit segment pointer*/ 1222 __le64 segment_ptr; 1223 __le32 intr_target; 1224 __le32 control; 1225 }; 1226 1227 /* control bitfields */ 1228 #define LINK_TOGGLE (0x1<<1) 1229 1230 /* Command completion event TRB */ 1231 struct xhci_event_cmd { 1232 /* Pointer to command TRB, or the value passed by the event data trb */ 1233 __le64 cmd_trb; 1234 __le32 status; 1235 __le32 flags; 1236 }; 1237 1238 /* flags bitmasks */ 1239 1240 /* Address device - disable SetAddress */ 1241 #define TRB_BSR (1<<9) 1242 1243 /* Configure Endpoint - Deconfigure */ 1244 #define TRB_DC (1<<9) 1245 1246 /* Stop Ring - Transfer State Preserve */ 1247 #define TRB_TSP (1<<9) 1248 1249 enum xhci_ep_reset_type { 1250 EP_HARD_RESET, 1251 EP_SOFT_RESET, 1252 }; 1253 1254 /* Force Event */ 1255 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 1256 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 1257 1258 /* Set Latency Tolerance Value */ 1259 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 1260 1261 /* Get Port Bandwidth */ 1262 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 1263 1264 /* Force Header */ 1265 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 1266 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 1267 1268 enum xhci_setup_dev { 1269 SETUP_CONTEXT_ONLY, 1270 SETUP_CONTEXT_ADDRESS, 1271 }; 1272 1273 /* bits 16:23 are the virtual function ID */ 1274 /* bits 24:31 are the slot ID */ 1275 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1276 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1277 1278 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1279 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1280 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1281 1282 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1283 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1284 #define LAST_EP_INDEX 30 1285 1286 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1287 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1288 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1289 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 1290 1291 /* Link TRB specific fields */ 1292 #define TRB_TC (1<<1) 1293 1294 /* Port Status Change Event TRB fields */ 1295 /* Port ID - bits 31:24 */ 1296 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1297 1298 #define EVENT_DATA (1 << 2) 1299 1300 /* Normal TRB fields */ 1301 /* transfer_len bitmasks - bits 0:16 */ 1302 #define TRB_LEN(p) ((p) & 0x1ffff) 1303 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1304 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1305 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1306 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1307 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1308 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1309 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1310 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1311 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1312 #define TRB_TBC(p) (((p) & 0x3) << 7) 1313 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1314 1315 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1316 #define TRB_CYCLE (1<<0) 1317 /* 1318 * Force next event data TRB to be evaluated before task switch. 1319 * Used to pass OS data back after a TD completes. 1320 */ 1321 #define TRB_ENT (1<<1) 1322 /* Interrupt on short packet */ 1323 #define TRB_ISP (1<<2) 1324 /* Set PCIe no snoop attribute */ 1325 #define TRB_NO_SNOOP (1<<3) 1326 /* Chain multiple TRBs into a TD */ 1327 #define TRB_CHAIN (1<<4) 1328 /* Interrupt on completion */ 1329 #define TRB_IOC (1<<5) 1330 /* The buffer pointer contains immediate data */ 1331 #define TRB_IDT (1<<6) 1332 /* TDs smaller than this might use IDT */ 1333 #define TRB_IDT_MAX_SIZE 8 1334 1335 /* Block Event Interrupt */ 1336 #define TRB_BEI (1<<9) 1337 1338 /* Control transfer TRB specific fields */ 1339 #define TRB_DIR_IN (1<<16) 1340 #define TRB_TX_TYPE(p) ((p) << 16) 1341 #define TRB_DATA_OUT 2 1342 #define TRB_DATA_IN 3 1343 1344 /* Isochronous TRB specific fields */ 1345 #define TRB_SIA (1<<31) 1346 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1347 1348 /* TRB cache size for xHC with TRB cache */ 1349 #define TRB_CACHE_SIZE_HS 8 1350 #define TRB_CACHE_SIZE_SS 16 1351 1352 struct xhci_generic_trb { 1353 __le32 field[4]; 1354 }; 1355 1356 union xhci_trb { 1357 struct xhci_link_trb link; 1358 struct xhci_transfer_event trans_event; 1359 struct xhci_event_cmd event_cmd; 1360 struct xhci_generic_trb generic; 1361 }; 1362 1363 /* TRB bit mask */ 1364 #define TRB_TYPE_BITMASK (0xfc00) 1365 #define TRB_TYPE(p) ((p) << 10) 1366 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1367 /* TRB type IDs */ 1368 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1369 #define TRB_NORMAL 1 1370 /* setup stage for control transfers */ 1371 #define TRB_SETUP 2 1372 /* data stage for control transfers */ 1373 #define TRB_DATA 3 1374 /* status stage for control transfers */ 1375 #define TRB_STATUS 4 1376 /* isoc transfers */ 1377 #define TRB_ISOC 5 1378 /* TRB for linking ring segments */ 1379 #define TRB_LINK 6 1380 #define TRB_EVENT_DATA 7 1381 /* Transfer Ring No-op (not for the command ring) */ 1382 #define TRB_TR_NOOP 8 1383 /* Command TRBs */ 1384 /* Enable Slot Command */ 1385 #define TRB_ENABLE_SLOT 9 1386 /* Disable Slot Command */ 1387 #define TRB_DISABLE_SLOT 10 1388 /* Address Device Command */ 1389 #define TRB_ADDR_DEV 11 1390 /* Configure Endpoint Command */ 1391 #define TRB_CONFIG_EP 12 1392 /* Evaluate Context Command */ 1393 #define TRB_EVAL_CONTEXT 13 1394 /* Reset Endpoint Command */ 1395 #define TRB_RESET_EP 14 1396 /* Stop Transfer Ring Command */ 1397 #define TRB_STOP_RING 15 1398 /* Set Transfer Ring Dequeue Pointer Command */ 1399 #define TRB_SET_DEQ 16 1400 /* Reset Device Command */ 1401 #define TRB_RESET_DEV 17 1402 /* Force Event Command (opt) */ 1403 #define TRB_FORCE_EVENT 18 1404 /* Negotiate Bandwidth Command (opt) */ 1405 #define TRB_NEG_BANDWIDTH 19 1406 /* Set Latency Tolerance Value Command (opt) */ 1407 #define TRB_SET_LT 20 1408 /* Get port bandwidth Command */ 1409 #define TRB_GET_BW 21 1410 /* Force Header Command - generate a transaction or link management packet */ 1411 #define TRB_FORCE_HEADER 22 1412 /* No-op Command - not for transfer rings */ 1413 #define TRB_CMD_NOOP 23 1414 /* TRB IDs 24-31 reserved */ 1415 /* Event TRBS */ 1416 /* Transfer Event */ 1417 #define TRB_TRANSFER 32 1418 /* Command Completion Event */ 1419 #define TRB_COMPLETION 33 1420 /* Port Status Change Event */ 1421 #define TRB_PORT_STATUS 34 1422 /* Bandwidth Request Event (opt) */ 1423 #define TRB_BANDWIDTH_EVENT 35 1424 /* Doorbell Event (opt) */ 1425 #define TRB_DOORBELL 36 1426 /* Host Controller Event */ 1427 #define TRB_HC_EVENT 37 1428 /* Device Notification Event - device sent function wake notification */ 1429 #define TRB_DEV_NOTE 38 1430 /* MFINDEX Wrap Event - microframe counter wrapped */ 1431 #define TRB_MFINDEX_WRAP 39 1432 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1433 #define TRB_VENDOR_DEFINED_LOW 48 1434 /* Nec vendor-specific command completion event. */ 1435 #define TRB_NEC_CMD_COMP 48 1436 /* Get NEC firmware revision. */ 1437 #define TRB_NEC_GET_FW 49 1438 1439 static inline const char *xhci_trb_type_string(u8 type) 1440 { 1441 switch (type) { 1442 case TRB_NORMAL: 1443 return "Normal"; 1444 case TRB_SETUP: 1445 return "Setup Stage"; 1446 case TRB_DATA: 1447 return "Data Stage"; 1448 case TRB_STATUS: 1449 return "Status Stage"; 1450 case TRB_ISOC: 1451 return "Isoch"; 1452 case TRB_LINK: 1453 return "Link"; 1454 case TRB_EVENT_DATA: 1455 return "Event Data"; 1456 case TRB_TR_NOOP: 1457 return "No-Op"; 1458 case TRB_ENABLE_SLOT: 1459 return "Enable Slot Command"; 1460 case TRB_DISABLE_SLOT: 1461 return "Disable Slot Command"; 1462 case TRB_ADDR_DEV: 1463 return "Address Device Command"; 1464 case TRB_CONFIG_EP: 1465 return "Configure Endpoint Command"; 1466 case TRB_EVAL_CONTEXT: 1467 return "Evaluate Context Command"; 1468 case TRB_RESET_EP: 1469 return "Reset Endpoint Command"; 1470 case TRB_STOP_RING: 1471 return "Stop Ring Command"; 1472 case TRB_SET_DEQ: 1473 return "Set TR Dequeue Pointer Command"; 1474 case TRB_RESET_DEV: 1475 return "Reset Device Command"; 1476 case TRB_FORCE_EVENT: 1477 return "Force Event Command"; 1478 case TRB_NEG_BANDWIDTH: 1479 return "Negotiate Bandwidth Command"; 1480 case TRB_SET_LT: 1481 return "Set Latency Tolerance Value Command"; 1482 case TRB_GET_BW: 1483 return "Get Port Bandwidth Command"; 1484 case TRB_FORCE_HEADER: 1485 return "Force Header Command"; 1486 case TRB_CMD_NOOP: 1487 return "No-Op Command"; 1488 case TRB_TRANSFER: 1489 return "Transfer Event"; 1490 case TRB_COMPLETION: 1491 return "Command Completion Event"; 1492 case TRB_PORT_STATUS: 1493 return "Port Status Change Event"; 1494 case TRB_BANDWIDTH_EVENT: 1495 return "Bandwidth Request Event"; 1496 case TRB_DOORBELL: 1497 return "Doorbell Event"; 1498 case TRB_HC_EVENT: 1499 return "Host Controller Event"; 1500 case TRB_DEV_NOTE: 1501 return "Device Notification Event"; 1502 case TRB_MFINDEX_WRAP: 1503 return "MFINDEX Wrap Event"; 1504 case TRB_NEC_CMD_COMP: 1505 return "NEC Command Completion Event"; 1506 case TRB_NEC_GET_FW: 1507 return "NET Get Firmware Revision Command"; 1508 default: 1509 return "UNKNOWN"; 1510 } 1511 } 1512 1513 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1514 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1515 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1516 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1517 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1518 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1519 1520 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1521 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1522 1523 /* 1524 * TRBS_PER_SEGMENT must be a multiple of 4, 1525 * since the command ring is 64-byte aligned. 1526 * It must also be greater than 16. 1527 */ 1528 #define TRBS_PER_SEGMENT 256 1529 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1530 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1531 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1532 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1533 /* TRB buffer pointers can't cross 64KB boundaries */ 1534 #define TRB_MAX_BUFF_SHIFT 16 1535 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1536 /* How much data is left before the 64KB boundary? */ 1537 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1538 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1539 #define MAX_SOFT_RETRY 3 1540 /* 1541 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if 1542 * XHCI_AVOID_BEI quirk is in use. 1543 */ 1544 #define AVOID_BEI_INTERVAL_MIN 8 1545 #define AVOID_BEI_INTERVAL_MAX 32 1546 1547 struct xhci_segment { 1548 union xhci_trb *trbs; 1549 /* private to HCD */ 1550 struct xhci_segment *next; 1551 dma_addr_t dma; 1552 /* Max packet sized bounce buffer for td-fragmant alignment */ 1553 dma_addr_t bounce_dma; 1554 void *bounce_buf; 1555 unsigned int bounce_offs; 1556 unsigned int bounce_len; 1557 }; 1558 1559 enum xhci_cancelled_td_status { 1560 TD_DIRTY = 0, 1561 TD_HALTED, 1562 TD_CLEARING_CACHE, 1563 TD_CLEARING_CACHE_DEFERRED, 1564 TD_CLEARED, 1565 }; 1566 1567 struct xhci_td { 1568 struct list_head td_list; 1569 struct list_head cancelled_td_list; 1570 int status; 1571 enum xhci_cancelled_td_status cancel_status; 1572 struct urb *urb; 1573 struct xhci_segment *start_seg; 1574 union xhci_trb *first_trb; 1575 union xhci_trb *last_trb; 1576 struct xhci_segment *last_trb_seg; 1577 struct xhci_segment *bounce_seg; 1578 /* actual_length of the URB has already been set */ 1579 bool urb_length_set; 1580 bool error_mid_td; 1581 unsigned int num_trbs; 1582 }; 1583 1584 /* 1585 * xHCI command default timeout value in milliseconds. 1586 * USB 3.2 spec, section 9.2.6.1 1587 */ 1588 #define XHCI_CMD_DEFAULT_TIMEOUT 5000 1589 1590 /* command descriptor */ 1591 struct xhci_cd { 1592 struct xhci_command *command; 1593 union xhci_trb *cmd_trb; 1594 }; 1595 1596 enum xhci_ring_type { 1597 TYPE_CTRL = 0, 1598 TYPE_ISOC, 1599 TYPE_BULK, 1600 TYPE_INTR, 1601 TYPE_STREAM, 1602 TYPE_COMMAND, 1603 TYPE_EVENT, 1604 }; 1605 1606 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1607 { 1608 switch (type) { 1609 case TYPE_CTRL: 1610 return "CTRL"; 1611 case TYPE_ISOC: 1612 return "ISOC"; 1613 case TYPE_BULK: 1614 return "BULK"; 1615 case TYPE_INTR: 1616 return "INTR"; 1617 case TYPE_STREAM: 1618 return "STREAM"; 1619 case TYPE_COMMAND: 1620 return "CMD"; 1621 case TYPE_EVENT: 1622 return "EVENT"; 1623 } 1624 1625 return "UNKNOWN"; 1626 } 1627 1628 struct xhci_ring { 1629 struct xhci_segment *first_seg; 1630 struct xhci_segment *last_seg; 1631 union xhci_trb *enqueue; 1632 struct xhci_segment *enq_seg; 1633 union xhci_trb *dequeue; 1634 struct xhci_segment *deq_seg; 1635 struct list_head td_list; 1636 /* 1637 * Write the cycle state into the TRB cycle field to give ownership of 1638 * the TRB to the host controller (if we are the producer), or to check 1639 * if we own the TRB (if we are the consumer). See section 4.9.1. 1640 */ 1641 u32 cycle_state; 1642 unsigned int stream_id; 1643 unsigned int num_segs; 1644 unsigned int num_trbs_free; /* used only by xhci DbC */ 1645 unsigned int bounce_buf_len; 1646 enum xhci_ring_type type; 1647 bool last_td_was_short; 1648 struct radix_tree_root *trb_address_map; 1649 }; 1650 1651 struct xhci_erst_entry { 1652 /* 64-bit event ring segment address */ 1653 __le64 seg_addr; 1654 __le32 seg_size; 1655 /* Set to zero */ 1656 __le32 rsvd; 1657 }; 1658 1659 struct xhci_erst { 1660 struct xhci_erst_entry *entries; 1661 unsigned int num_entries; 1662 /* xhci->event_ring keeps track of segment dma addresses */ 1663 dma_addr_t erst_dma_addr; 1664 /* Num entries the ERST can contain */ 1665 unsigned int erst_size; 1666 }; 1667 1668 struct xhci_scratchpad { 1669 u64 *sp_array; 1670 dma_addr_t sp_dma; 1671 void **sp_buffers; 1672 }; 1673 1674 struct urb_priv { 1675 int num_tds; 1676 int num_tds_done; 1677 struct xhci_td td[]; 1678 }; 1679 1680 /* 1681 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1682 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1683 * meaning 64 ring segments. 1684 * Initial allocated size of the ERST, in number of entries */ 1685 #define ERST_NUM_SEGS 1 1686 /* Poll every 60 seconds */ 1687 #define POLL_TIMEOUT 60 1688 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1689 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1690 /* XXX: Make these module parameters */ 1691 1692 struct s3_save { 1693 u32 command; 1694 u32 dev_nt; 1695 u64 dcbaa_ptr; 1696 u32 config_reg; 1697 }; 1698 1699 /* Use for lpm */ 1700 struct dev_info { 1701 u32 dev_id; 1702 struct list_head list; 1703 }; 1704 1705 struct xhci_bus_state { 1706 unsigned long bus_suspended; 1707 unsigned long next_statechange; 1708 1709 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1710 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1711 u32 port_c_suspend; 1712 u32 suspended_ports; 1713 u32 port_remote_wakeup; 1714 /* which ports have started to resume */ 1715 unsigned long resuming_ports; 1716 }; 1717 1718 struct xhci_interrupter { 1719 struct xhci_ring *event_ring; 1720 struct xhci_erst erst; 1721 struct xhci_intr_reg __iomem *ir_set; 1722 unsigned int intr_num; 1723 /* For interrupter registers save and restore over suspend/resume */ 1724 u32 s3_irq_pending; 1725 u32 s3_irq_control; 1726 u32 s3_erst_size; 1727 u64 s3_erst_base; 1728 u64 s3_erst_dequeue; 1729 }; 1730 /* 1731 * It can take up to 20 ms to transition from RExit to U0 on the 1732 * Intel Lynx Point LP xHCI host. 1733 */ 1734 #define XHCI_MAX_REXIT_TIMEOUT_MS 20 1735 struct xhci_port_cap { 1736 u32 *psi; /* array of protocol speed ID entries */ 1737 u8 psi_count; 1738 u8 psi_uid_count; 1739 u8 maj_rev; 1740 u8 min_rev; 1741 }; 1742 1743 struct xhci_port { 1744 __le32 __iomem *addr; 1745 int hw_portnum; 1746 int hcd_portnum; 1747 struct xhci_hub *rhub; 1748 struct xhci_port_cap *port_cap; 1749 unsigned int lpm_incapable:1; 1750 unsigned long resume_timestamp; 1751 bool rexit_active; 1752 struct completion rexit_done; 1753 struct completion u3exit_done; 1754 }; 1755 1756 struct xhci_hub { 1757 struct xhci_port **ports; 1758 unsigned int num_ports; 1759 struct usb_hcd *hcd; 1760 /* keep track of bus suspend info */ 1761 struct xhci_bus_state bus_state; 1762 /* supported prococol extended capabiliy values */ 1763 u8 maj_rev; 1764 u8 min_rev; 1765 }; 1766 1767 /* There is one xhci_hcd structure per controller */ 1768 struct xhci_hcd { 1769 struct usb_hcd *main_hcd; 1770 struct usb_hcd *shared_hcd; 1771 /* glue to PCI and HCD framework */ 1772 struct xhci_cap_regs __iomem *cap_regs; 1773 struct xhci_op_regs __iomem *op_regs; 1774 struct xhci_run_regs __iomem *run_regs; 1775 struct xhci_doorbell_array __iomem *dba; 1776 1777 /* Cached register copies of read-only HC data */ 1778 __u32 hcs_params1; 1779 __u32 hcs_params2; 1780 __u32 hcs_params3; 1781 __u32 hcc_params; 1782 __u32 hcc_params2; 1783 1784 spinlock_t lock; 1785 1786 /* packed release number */ 1787 u8 sbrn; 1788 u16 hci_version; 1789 u8 max_slots; 1790 u16 max_interrupters; 1791 u8 max_ports; 1792 u8 isoc_threshold; 1793 /* imod_interval in ns (I * 250ns) */ 1794 u32 imod_interval; 1795 u32 isoc_bei_interval; 1796 int event_ring_max; 1797 /* 4KB min, 128MB max */ 1798 int page_size; 1799 /* Valid values are 12 to 20, inclusive */ 1800 int page_shift; 1801 /* msi-x vectors */ 1802 int msix_count; 1803 /* optional clocks */ 1804 struct clk *clk; 1805 struct clk *reg_clk; 1806 /* optional reset controller */ 1807 struct reset_control *reset; 1808 /* data structures */ 1809 struct xhci_device_context_array *dcbaa; 1810 struct xhci_interrupter *interrupter; 1811 struct xhci_ring *cmd_ring; 1812 unsigned int cmd_ring_state; 1813 #define CMD_RING_STATE_RUNNING (1 << 0) 1814 #define CMD_RING_STATE_ABORTED (1 << 1) 1815 #define CMD_RING_STATE_STOPPED (1 << 2) 1816 struct list_head cmd_list; 1817 unsigned int cmd_ring_reserved_trbs; 1818 struct delayed_work cmd_timer; 1819 struct completion cmd_ring_stop_completion; 1820 struct xhci_command *current_cmd; 1821 1822 /* Scratchpad */ 1823 struct xhci_scratchpad *scratchpad; 1824 1825 /* slot enabling and address device helpers */ 1826 /* these are not thread safe so use mutex */ 1827 struct mutex mutex; 1828 /* Internal mirror of the HW's dcbaa */ 1829 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1830 /* For keeping track of bandwidth domains per roothub. */ 1831 struct xhci_root_port_bw_info *rh_bw; 1832 1833 /* DMA pools */ 1834 struct dma_pool *device_pool; 1835 struct dma_pool *segment_pool; 1836 struct dma_pool *small_streams_pool; 1837 struct dma_pool *medium_streams_pool; 1838 1839 /* Host controller watchdog timer structures */ 1840 unsigned int xhc_state; 1841 unsigned long run_graceperiod; 1842 struct s3_save s3; 1843 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1844 * 1845 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1846 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1847 * that sees this status (other than the timer that set it) should stop touching 1848 * hardware immediately. Interrupt handlers should return immediately when 1849 * they see this status (any time they drop and re-acquire xhci->lock). 1850 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1851 * putting the TD on the canceled list, etc. 1852 * 1853 * There are no reports of xHCI host controllers that display this issue. 1854 */ 1855 #define XHCI_STATE_DYING (1 << 0) 1856 #define XHCI_STATE_HALTED (1 << 1) 1857 #define XHCI_STATE_REMOVING (1 << 2) 1858 unsigned long long quirks; 1859 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0) 1860 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */ 1861 #define XHCI_NEC_HOST BIT_ULL(2) 1862 #define XHCI_AMD_PLL_FIX BIT_ULL(3) 1863 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) 1864 /* 1865 * Certain Intel host controllers have a limit to the number of endpoint 1866 * contexts they can handle. Ideally, they would signal that they can't handle 1867 * anymore endpoint contexts by returning a Resource Error for the Configure 1868 * Endpoint command, but they don't. Instead they expect software to keep track 1869 * of the number of active endpoints for them, across configure endpoint 1870 * commands, reset device commands, disable slot commands, and address device 1871 * commands. 1872 */ 1873 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) 1874 #define XHCI_BROKEN_MSI BIT_ULL(6) 1875 #define XHCI_RESET_ON_RESUME BIT_ULL(7) 1876 #define XHCI_SW_BW_CHECKING BIT_ULL(8) 1877 #define XHCI_AMD_0x96_HOST BIT_ULL(9) 1878 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) 1879 #define XHCI_LPM_SUPPORT BIT_ULL(11) 1880 #define XHCI_INTEL_HOST BIT_ULL(12) 1881 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13) 1882 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14) 1883 #define XHCI_AVOID_BEI BIT_ULL(15) 1884 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */ 1885 #define XHCI_SLOW_SUSPEND BIT_ULL(17) 1886 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) 1887 /* For controllers with a broken beyond repair streams implementation */ 1888 #define XHCI_BROKEN_STREAMS BIT_ULL(19) 1889 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20) 1890 #define XHCI_MTK_HOST BIT_ULL(21) 1891 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) 1892 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) 1893 #define XHCI_MISSING_CAS BIT_ULL(24) 1894 /* For controller with a broken Port Disable implementation */ 1895 #define XHCI_BROKEN_PORT_PED BIT_ULL(25) 1896 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) 1897 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27) 1898 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) 1899 #define XHCI_HW_LPM_DISABLE BIT_ULL(29) 1900 #define XHCI_SUSPEND_DELAY BIT_ULL(30) 1901 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) 1902 #define XHCI_ZERO_64B_REGS BIT_ULL(32) 1903 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) 1904 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) 1905 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) 1906 #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36) 1907 #define XHCI_SKIP_PHY_INIT BIT_ULL(37) 1908 #define XHCI_DISABLE_SPARSE BIT_ULL(38) 1909 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) 1910 #define XHCI_NO_SOFT_RETRY BIT_ULL(40) 1911 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) 1912 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) 1913 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) 1914 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) 1915 #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) 1916 #define XHCI_ZHAOXIN_HOST BIT_ULL(46) 1917 #define XHCI_WRITE_64_HI_LO BIT_ULL(47) 1918 1919 unsigned int num_active_eps; 1920 unsigned int limit_active_eps; 1921 struct xhci_port *hw_ports; 1922 struct xhci_hub usb2_rhub; 1923 struct xhci_hub usb3_rhub; 1924 /* support xHCI 1.0 spec USB2 hardware LPM */ 1925 unsigned hw_lpm_support:1; 1926 /* Broken Suspend flag for SNPS Suspend resume issue */ 1927 unsigned broken_suspend:1; 1928 /* Indicates that omitting hcd is supported if root hub has no ports */ 1929 unsigned allow_single_roothub:1; 1930 /* cached usb2 extened protocol capabilites */ 1931 u32 *ext_caps; 1932 unsigned int num_ext_caps; 1933 /* cached extended protocol port capabilities */ 1934 struct xhci_port_cap *port_caps; 1935 unsigned int num_port_caps; 1936 /* Compliance Mode Recovery Data */ 1937 struct timer_list comp_mode_recovery_timer; 1938 u32 port_status_u0; 1939 u16 test_mode; 1940 /* Compliance Mode Timer Triggered every 2 seconds */ 1941 #define COMP_MODE_RCVRY_MSECS 2000 1942 1943 struct dentry *debugfs_root; 1944 struct dentry *debugfs_slots; 1945 struct list_head regset_list; 1946 1947 void *dbc; 1948 /* platform-specific data -- must come last */ 1949 unsigned long priv[] __aligned(sizeof(s64)); 1950 }; 1951 1952 /* Platform specific overrides to generic XHCI hc_driver ops */ 1953 struct xhci_driver_overrides { 1954 size_t extra_priv_size; 1955 int (*reset)(struct usb_hcd *hcd); 1956 int (*start)(struct usb_hcd *hcd); 1957 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1958 struct usb_host_endpoint *ep); 1959 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1960 struct usb_host_endpoint *ep); 1961 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *); 1962 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *); 1963 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev, 1964 struct usb_tt *tt, gfp_t mem_flags); 1965 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1966 u16 wIndex, char *buf, u16 wLength); 1967 }; 1968 1969 #define XHCI_CFC_DELAY 10 1970 1971 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1972 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1973 { 1974 struct usb_hcd *primary_hcd; 1975 1976 if (usb_hcd_is_primary_hcd(hcd)) 1977 primary_hcd = hcd; 1978 else 1979 primary_hcd = hcd->primary_hcd; 1980 1981 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1982 } 1983 1984 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1985 { 1986 return xhci->main_hcd; 1987 } 1988 1989 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci) 1990 { 1991 if (xhci->shared_hcd) 1992 return xhci->shared_hcd; 1993 1994 if (!xhci->usb2_rhub.num_ports) 1995 return xhci->main_hcd; 1996 1997 return NULL; 1998 } 1999 2000 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd) 2001 { 2002 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 2003 2004 return hcd == xhci_get_usb3_hcd(xhci); 2005 } 2006 2007 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci) 2008 { 2009 return xhci->allow_single_roothub && 2010 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); 2011 } 2012 2013 #define xhci_dbg(xhci, fmt, args...) \ 2014 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 2015 #define xhci_err(xhci, fmt, args...) \ 2016 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 2017 #define xhci_warn(xhci, fmt, args...) \ 2018 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 2019 #define xhci_warn_ratelimited(xhci, fmt, args...) \ 2020 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 2021 #define xhci_info(xhci, fmt, args...) \ 2022 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 2023 2024 /* 2025 * Registers should always be accessed with double word or quad word accesses. 2026 * 2027 * Some xHCI implementations may support 64-bit address pointers. Registers 2028 * with 64-bit address pointers should be written to with dword accesses by 2029 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 2030 * xHCI implementations that do not support 64-bit address pointers will ignore 2031 * the high dword, and write order is irrelevant. 2032 */ 2033 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 2034 __le64 __iomem *regs) 2035 { 2036 return lo_hi_readq(regs); 2037 } 2038 static inline void xhci_write_64(struct xhci_hcd *xhci, 2039 const u64 val, __le64 __iomem *regs) 2040 { 2041 lo_hi_writeq(val, regs); 2042 } 2043 2044 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 2045 { 2046 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 2047 } 2048 2049 /* xHCI debugging */ 2050 char *xhci_get_slot_state(struct xhci_hcd *xhci, 2051 struct xhci_container_ctx *ctx); 2052 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 2053 const char *fmt, ...); 2054 2055 /* xHCI memory management */ 2056 void xhci_mem_cleanup(struct xhci_hcd *xhci); 2057 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 2058 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 2059 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 2060 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 2061 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 2062 struct usb_device *udev); 2063 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 2064 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 2065 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 2066 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 2067 struct xhci_virt_device *virt_dev, 2068 int old_active_eps); 2069 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 2070 void xhci_update_bw_info(struct xhci_hcd *xhci, 2071 struct xhci_container_ctx *in_ctx, 2072 struct xhci_input_control_ctx *ctrl_ctx, 2073 struct xhci_virt_device *virt_dev); 2074 void xhci_endpoint_copy(struct xhci_hcd *xhci, 2075 struct xhci_container_ctx *in_ctx, 2076 struct xhci_container_ctx *out_ctx, 2077 unsigned int ep_index); 2078 void xhci_slot_copy(struct xhci_hcd *xhci, 2079 struct xhci_container_ctx *in_ctx, 2080 struct xhci_container_ctx *out_ctx); 2081 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 2082 struct usb_device *udev, struct usb_host_endpoint *ep, 2083 gfp_t mem_flags); 2084 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, 2085 unsigned int num_segs, unsigned int cycle_state, 2086 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); 2087 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 2088 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 2089 unsigned int num_trbs, gfp_t flags); 2090 int xhci_alloc_erst(struct xhci_hcd *xhci, 2091 struct xhci_ring *evt_ring, 2092 struct xhci_erst *erst, 2093 gfp_t flags); 2094 void xhci_initialize_ring_info(struct xhci_ring *ring, 2095 unsigned int cycle_state); 2096 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 2097 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 2098 struct xhci_virt_device *virt_dev, 2099 unsigned int ep_index); 2100 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 2101 unsigned int num_stream_ctxs, 2102 unsigned int num_streams, 2103 unsigned int max_packet, gfp_t flags); 2104 void xhci_free_stream_info(struct xhci_hcd *xhci, 2105 struct xhci_stream_info *stream_info); 2106 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 2107 struct xhci_ep_ctx *ep_ctx, 2108 struct xhci_stream_info *stream_info); 2109 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 2110 struct xhci_virt_ep *ep); 2111 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 2112 struct xhci_virt_device *virt_dev, bool drop_control_ep); 2113 struct xhci_ring *xhci_dma_to_transfer_ring( 2114 struct xhci_virt_ep *ep, 2115 u64 address); 2116 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 2117 bool allocate_completion, gfp_t mem_flags); 2118 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, 2119 bool allocate_completion, gfp_t mem_flags); 2120 void xhci_urb_free_priv(struct urb_priv *urb_priv); 2121 void xhci_free_command(struct xhci_hcd *xhci, 2122 struct xhci_command *command); 2123 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 2124 int type, gfp_t flags); 2125 void xhci_free_container_ctx(struct xhci_hcd *xhci, 2126 struct xhci_container_ctx *ctx); 2127 2128 /* xHCI host controller glue */ 2129 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 2130 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us); 2131 void xhci_quiesce(struct xhci_hcd *xhci); 2132 int xhci_halt(struct xhci_hcd *xhci); 2133 int xhci_start(struct xhci_hcd *xhci); 2134 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us); 2135 int xhci_run(struct usb_hcd *hcd); 2136 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 2137 void xhci_shutdown(struct usb_hcd *hcd); 2138 void xhci_stop(struct usb_hcd *hcd); 2139 void xhci_init_driver(struct hc_driver *drv, 2140 const struct xhci_driver_overrides *over); 2141 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 2142 struct usb_host_endpoint *ep); 2143 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 2144 struct usb_host_endpoint *ep); 2145 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 2146 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 2147 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 2148 struct usb_tt *tt, gfp_t mem_flags); 2149 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); 2150 int xhci_ext_cap_init(struct xhci_hcd *xhci); 2151 2152 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 2153 int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg); 2154 2155 irqreturn_t xhci_irq(struct usb_hcd *hcd); 2156 irqreturn_t xhci_msi_irq(int irq, void *hcd); 2157 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 2158 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 2159 struct xhci_virt_device *virt_dev, 2160 struct usb_device *hdev, 2161 struct usb_tt *tt, gfp_t mem_flags); 2162 2163 /* xHCI ring, segment, TRB, and TD functions */ 2164 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 2165 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 2166 struct xhci_segment *start_seg, union xhci_trb *start_trb, 2167 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); 2168 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 2169 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 2170 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 2171 u32 trb_type, u32 slot_id); 2172 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2173 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 2174 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 2175 u32 field1, u32 field2, u32 field3, u32 field4); 2176 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 2177 int slot_id, unsigned int ep_index, int suspend); 2178 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2179 int slot_id, unsigned int ep_index); 2180 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2181 int slot_id, unsigned int ep_index); 2182 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2183 int slot_id, unsigned int ep_index); 2184 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 2185 struct urb *urb, int slot_id, unsigned int ep_index); 2186 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 2187 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 2188 bool command_must_succeed); 2189 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 2190 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 2191 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 2192 int slot_id, unsigned int ep_index, 2193 enum xhci_ep_reset_type reset_type); 2194 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2195 u32 slot_id); 2196 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id, 2197 unsigned int ep_index, unsigned int stream_id, 2198 struct xhci_td *td); 2199 void xhci_stop_endpoint_command_watchdog(struct timer_list *t); 2200 void xhci_handle_command_timeout(struct work_struct *work); 2201 2202 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 2203 unsigned int ep_index, unsigned int stream_id); 2204 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 2205 unsigned int slot_id, 2206 unsigned int ep_index); 2207 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 2208 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); 2209 unsigned int count_trbs(u64 addr, u64 len); 2210 2211 /* xHCI roothub code */ 2212 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 2213 u32 link_state); 2214 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 2215 u32 port_bit); 2216 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 2217 char *buf, u16 wLength); 2218 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 2219 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 2220 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd); 2221 2222 void xhci_hc_died(struct xhci_hcd *xhci); 2223 2224 #ifdef CONFIG_PM 2225 int xhci_bus_suspend(struct usb_hcd *hcd); 2226 int xhci_bus_resume(struct usb_hcd *hcd); 2227 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd); 2228 #else 2229 #define xhci_bus_suspend NULL 2230 #define xhci_bus_resume NULL 2231 #define xhci_get_resuming_ports NULL 2232 #endif /* CONFIG_PM */ 2233 2234 u32 xhci_port_state_to_neutral(u32 state); 2235 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 2236 u16 port); 2237 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 2238 2239 /* xHCI contexts */ 2240 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 2241 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 2242 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 2243 2244 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 2245 unsigned int slot_id, unsigned int ep_index, 2246 unsigned int stream_id); 2247 2248 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 2249 struct urb *urb) 2250 { 2251 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 2252 xhci_get_endpoint_index(&urb->ep->desc), 2253 urb->stream_id); 2254 } 2255 2256 /* 2257 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass 2258 * them anyways as we where unable to find a device that matches the 2259 * constraints. 2260 */ 2261 static inline bool xhci_urb_suitable_for_idt(struct urb *urb) 2262 { 2263 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && 2264 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && 2265 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && 2266 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && 2267 !urb->num_sgs) 2268 return true; 2269 2270 return false; 2271 } 2272 2273 static inline char *xhci_slot_state_string(u32 state) 2274 { 2275 switch (state) { 2276 case SLOT_STATE_ENABLED: 2277 return "enabled/disabled"; 2278 case SLOT_STATE_DEFAULT: 2279 return "default"; 2280 case SLOT_STATE_ADDRESSED: 2281 return "addressed"; 2282 case SLOT_STATE_CONFIGURED: 2283 return "configured"; 2284 default: 2285 return "reserved"; 2286 } 2287 } 2288 2289 static inline const char *xhci_decode_trb(char *str, size_t size, 2290 u32 field0, u32 field1, u32 field2, u32 field3) 2291 { 2292 int type = TRB_FIELD_TO_TYPE(field3); 2293 2294 switch (type) { 2295 case TRB_LINK: 2296 snprintf(str, size, 2297 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2298 field1, field0, GET_INTR_TARGET(field2), 2299 xhci_trb_type_string(type), 2300 field3 & TRB_IOC ? 'I' : 'i', 2301 field3 & TRB_CHAIN ? 'C' : 'c', 2302 field3 & TRB_TC ? 'T' : 't', 2303 field3 & TRB_CYCLE ? 'C' : 'c'); 2304 break; 2305 case TRB_TRANSFER: 2306 case TRB_COMPLETION: 2307 case TRB_PORT_STATUS: 2308 case TRB_BANDWIDTH_EVENT: 2309 case TRB_DOORBELL: 2310 case TRB_HC_EVENT: 2311 case TRB_DEV_NOTE: 2312 case TRB_MFINDEX_WRAP: 2313 snprintf(str, size, 2314 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2315 field1, field0, 2316 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2317 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2318 /* Macro decrements 1, maybe it shouldn't?!? */ 2319 TRB_TO_EP_INDEX(field3) + 1, 2320 xhci_trb_type_string(type), 2321 field3 & EVENT_DATA ? 'E' : 'e', 2322 field3 & TRB_CYCLE ? 'C' : 'c'); 2323 2324 break; 2325 case TRB_SETUP: 2326 snprintf(str, size, 2327 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2328 field0 & 0xff, 2329 (field0 & 0xff00) >> 8, 2330 (field0 & 0xff000000) >> 24, 2331 (field0 & 0xff0000) >> 16, 2332 (field1 & 0xff00) >> 8, 2333 field1 & 0xff, 2334 (field1 & 0xff000000) >> 16 | 2335 (field1 & 0xff0000) >> 16, 2336 TRB_LEN(field2), GET_TD_SIZE(field2), 2337 GET_INTR_TARGET(field2), 2338 xhci_trb_type_string(type), 2339 field3 & TRB_IDT ? 'I' : 'i', 2340 field3 & TRB_IOC ? 'I' : 'i', 2341 field3 & TRB_CYCLE ? 'C' : 'c'); 2342 break; 2343 case TRB_DATA: 2344 snprintf(str, size, 2345 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2346 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2347 GET_INTR_TARGET(field2), 2348 xhci_trb_type_string(type), 2349 field3 & TRB_IDT ? 'I' : 'i', 2350 field3 & TRB_IOC ? 'I' : 'i', 2351 field3 & TRB_CHAIN ? 'C' : 'c', 2352 field3 & TRB_NO_SNOOP ? 'S' : 's', 2353 field3 & TRB_ISP ? 'I' : 'i', 2354 field3 & TRB_ENT ? 'E' : 'e', 2355 field3 & TRB_CYCLE ? 'C' : 'c'); 2356 break; 2357 case TRB_STATUS: 2358 snprintf(str, size, 2359 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2360 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2361 GET_INTR_TARGET(field2), 2362 xhci_trb_type_string(type), 2363 field3 & TRB_IOC ? 'I' : 'i', 2364 field3 & TRB_CHAIN ? 'C' : 'c', 2365 field3 & TRB_ENT ? 'E' : 'e', 2366 field3 & TRB_CYCLE ? 'C' : 'c'); 2367 break; 2368 case TRB_NORMAL: 2369 case TRB_ISOC: 2370 case TRB_EVENT_DATA: 2371 case TRB_TR_NOOP: 2372 snprintf(str, size, 2373 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2374 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2375 GET_INTR_TARGET(field2), 2376 xhci_trb_type_string(type), 2377 field3 & TRB_BEI ? 'B' : 'b', 2378 field3 & TRB_IDT ? 'I' : 'i', 2379 field3 & TRB_IOC ? 'I' : 'i', 2380 field3 & TRB_CHAIN ? 'C' : 'c', 2381 field3 & TRB_NO_SNOOP ? 'S' : 's', 2382 field3 & TRB_ISP ? 'I' : 'i', 2383 field3 & TRB_ENT ? 'E' : 'e', 2384 field3 & TRB_CYCLE ? 'C' : 'c'); 2385 break; 2386 2387 case TRB_CMD_NOOP: 2388 case TRB_ENABLE_SLOT: 2389 snprintf(str, size, 2390 "%s: flags %c", 2391 xhci_trb_type_string(type), 2392 field3 & TRB_CYCLE ? 'C' : 'c'); 2393 break; 2394 case TRB_DISABLE_SLOT: 2395 case TRB_NEG_BANDWIDTH: 2396 snprintf(str, size, 2397 "%s: slot %d flags %c", 2398 xhci_trb_type_string(type), 2399 TRB_TO_SLOT_ID(field3), 2400 field3 & TRB_CYCLE ? 'C' : 'c'); 2401 break; 2402 case TRB_ADDR_DEV: 2403 snprintf(str, size, 2404 "%s: ctx %08x%08x slot %d flags %c:%c", 2405 xhci_trb_type_string(type), 2406 field1, field0, 2407 TRB_TO_SLOT_ID(field3), 2408 field3 & TRB_BSR ? 'B' : 'b', 2409 field3 & TRB_CYCLE ? 'C' : 'c'); 2410 break; 2411 case TRB_CONFIG_EP: 2412 snprintf(str, size, 2413 "%s: ctx %08x%08x slot %d flags %c:%c", 2414 xhci_trb_type_string(type), 2415 field1, field0, 2416 TRB_TO_SLOT_ID(field3), 2417 field3 & TRB_DC ? 'D' : 'd', 2418 field3 & TRB_CYCLE ? 'C' : 'c'); 2419 break; 2420 case TRB_EVAL_CONTEXT: 2421 snprintf(str, size, 2422 "%s: ctx %08x%08x slot %d flags %c", 2423 xhci_trb_type_string(type), 2424 field1, field0, 2425 TRB_TO_SLOT_ID(field3), 2426 field3 & TRB_CYCLE ? 'C' : 'c'); 2427 break; 2428 case TRB_RESET_EP: 2429 snprintf(str, size, 2430 "%s: ctx %08x%08x slot %d ep %d flags %c:%c", 2431 xhci_trb_type_string(type), 2432 field1, field0, 2433 TRB_TO_SLOT_ID(field3), 2434 /* Macro decrements 1, maybe it shouldn't?!? */ 2435 TRB_TO_EP_INDEX(field3) + 1, 2436 field3 & TRB_TSP ? 'T' : 't', 2437 field3 & TRB_CYCLE ? 'C' : 'c'); 2438 break; 2439 case TRB_STOP_RING: 2440 snprintf(str, size, 2441 "%s: slot %d sp %d ep %d flags %c", 2442 xhci_trb_type_string(type), 2443 TRB_TO_SLOT_ID(field3), 2444 TRB_TO_SUSPEND_PORT(field3), 2445 /* Macro decrements 1, maybe it shouldn't?!? */ 2446 TRB_TO_EP_INDEX(field3) + 1, 2447 field3 & TRB_CYCLE ? 'C' : 'c'); 2448 break; 2449 case TRB_SET_DEQ: 2450 snprintf(str, size, 2451 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2452 xhci_trb_type_string(type), 2453 field1, field0, 2454 TRB_TO_STREAM_ID(field2), 2455 TRB_TO_SLOT_ID(field3), 2456 /* Macro decrements 1, maybe it shouldn't?!? */ 2457 TRB_TO_EP_INDEX(field3) + 1, 2458 field3 & TRB_CYCLE ? 'C' : 'c'); 2459 break; 2460 case TRB_RESET_DEV: 2461 snprintf(str, size, 2462 "%s: slot %d flags %c", 2463 xhci_trb_type_string(type), 2464 TRB_TO_SLOT_ID(field3), 2465 field3 & TRB_CYCLE ? 'C' : 'c'); 2466 break; 2467 case TRB_FORCE_EVENT: 2468 snprintf(str, size, 2469 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2470 xhci_trb_type_string(type), 2471 field1, field0, 2472 TRB_TO_VF_INTR_TARGET(field2), 2473 TRB_TO_VF_ID(field3), 2474 field3 & TRB_CYCLE ? 'C' : 'c'); 2475 break; 2476 case TRB_SET_LT: 2477 snprintf(str, size, 2478 "%s: belt %d flags %c", 2479 xhci_trb_type_string(type), 2480 TRB_TO_BELT(field3), 2481 field3 & TRB_CYCLE ? 'C' : 'c'); 2482 break; 2483 case TRB_GET_BW: 2484 snprintf(str, size, 2485 "%s: ctx %08x%08x slot %d speed %d flags %c", 2486 xhci_trb_type_string(type), 2487 field1, field0, 2488 TRB_TO_SLOT_ID(field3), 2489 TRB_TO_DEV_SPEED(field3), 2490 field3 & TRB_CYCLE ? 'C' : 'c'); 2491 break; 2492 case TRB_FORCE_HEADER: 2493 snprintf(str, size, 2494 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2495 xhci_trb_type_string(type), 2496 field2, field1, field0 & 0xffffffe0, 2497 TRB_TO_PACKET_TYPE(field0), 2498 TRB_TO_ROOTHUB_PORT(field3), 2499 field3 & TRB_CYCLE ? 'C' : 'c'); 2500 break; 2501 default: 2502 snprintf(str, size, 2503 "type '%s' -> raw %08x %08x %08x %08x", 2504 xhci_trb_type_string(type), 2505 field0, field1, field2, field3); 2506 } 2507 2508 return str; 2509 } 2510 2511 static inline const char *xhci_decode_ctrl_ctx(char *str, 2512 unsigned long drop, unsigned long add) 2513 { 2514 unsigned int bit; 2515 int ret = 0; 2516 2517 str[0] = '\0'; 2518 2519 if (drop) { 2520 ret = sprintf(str, "Drop:"); 2521 for_each_set_bit(bit, &drop, 32) 2522 ret += sprintf(str + ret, " %d%s", 2523 bit / 2, 2524 bit % 2 ? "in":"out"); 2525 ret += sprintf(str + ret, ", "); 2526 } 2527 2528 if (add) { 2529 ret += sprintf(str + ret, "Add:%s%s", 2530 (add & SLOT_FLAG) ? " slot":"", 2531 (add & EP0_FLAG) ? " ep0":""); 2532 add &= ~(SLOT_FLAG | EP0_FLAG); 2533 for_each_set_bit(bit, &add, 32) 2534 ret += sprintf(str + ret, " %d%s", 2535 bit / 2, 2536 bit % 2 ? "in":"out"); 2537 } 2538 return str; 2539 } 2540 2541 static inline const char *xhci_decode_slot_context(char *str, 2542 u32 info, u32 info2, u32 tt_info, u32 state) 2543 { 2544 u32 speed; 2545 u32 hub; 2546 u32 mtt; 2547 int ret = 0; 2548 2549 speed = info & DEV_SPEED; 2550 hub = info & DEV_HUB; 2551 mtt = info & DEV_MTT; 2552 2553 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2554 info & ROUTE_STRING_MASK, 2555 ({ char *s; 2556 switch (speed) { 2557 case SLOT_SPEED_FS: 2558 s = "full-speed"; 2559 break; 2560 case SLOT_SPEED_LS: 2561 s = "low-speed"; 2562 break; 2563 case SLOT_SPEED_HS: 2564 s = "high-speed"; 2565 break; 2566 case SLOT_SPEED_SS: 2567 s = "super-speed"; 2568 break; 2569 case SLOT_SPEED_SSP: 2570 s = "super-speed plus"; 2571 break; 2572 default: 2573 s = "UNKNOWN speed"; 2574 } s; }), 2575 mtt ? " multi-TT" : "", 2576 hub ? " Hub" : "", 2577 (info & LAST_CTX_MASK) >> 27, 2578 info2 & MAX_EXIT, 2579 DEVINFO_TO_ROOT_HUB_PORT(info2), 2580 DEVINFO_TO_MAX_PORTS(info2)); 2581 2582 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2583 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2584 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2585 state & DEV_ADDR_MASK, 2586 xhci_slot_state_string(GET_SLOT_STATE(state))); 2587 2588 return str; 2589 } 2590 2591 2592 static inline const char *xhci_portsc_link_state_string(u32 portsc) 2593 { 2594 switch (portsc & PORT_PLS_MASK) { 2595 case XDEV_U0: 2596 return "U0"; 2597 case XDEV_U1: 2598 return "U1"; 2599 case XDEV_U2: 2600 return "U2"; 2601 case XDEV_U3: 2602 return "U3"; 2603 case XDEV_DISABLED: 2604 return "Disabled"; 2605 case XDEV_RXDETECT: 2606 return "RxDetect"; 2607 case XDEV_INACTIVE: 2608 return "Inactive"; 2609 case XDEV_POLLING: 2610 return "Polling"; 2611 case XDEV_RECOVERY: 2612 return "Recovery"; 2613 case XDEV_HOT_RESET: 2614 return "Hot Reset"; 2615 case XDEV_COMP_MODE: 2616 return "Compliance mode"; 2617 case XDEV_TEST_MODE: 2618 return "Test mode"; 2619 case XDEV_RESUME: 2620 return "Resume"; 2621 default: 2622 break; 2623 } 2624 return "Unknown"; 2625 } 2626 2627 static inline const char *xhci_decode_portsc(char *str, u32 portsc) 2628 { 2629 int ret; 2630 2631 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ", 2632 portsc & PORT_POWER ? "Powered" : "Powered-off", 2633 portsc & PORT_CONNECT ? "Connected" : "Not-connected", 2634 portsc & PORT_PE ? "Enabled" : "Disabled", 2635 xhci_portsc_link_state_string(portsc), 2636 DEV_PORT_SPEED(portsc)); 2637 2638 if (portsc & PORT_OC) 2639 ret += sprintf(str + ret, "OverCurrent "); 2640 if (portsc & PORT_RESET) 2641 ret += sprintf(str + ret, "In-Reset "); 2642 2643 ret += sprintf(str + ret, "Change: "); 2644 if (portsc & PORT_CSC) 2645 ret += sprintf(str + ret, "CSC "); 2646 if (portsc & PORT_PEC) 2647 ret += sprintf(str + ret, "PEC "); 2648 if (portsc & PORT_WRC) 2649 ret += sprintf(str + ret, "WRC "); 2650 if (portsc & PORT_OCC) 2651 ret += sprintf(str + ret, "OCC "); 2652 if (portsc & PORT_RC) 2653 ret += sprintf(str + ret, "PRC "); 2654 if (portsc & PORT_PLC) 2655 ret += sprintf(str + ret, "PLC "); 2656 if (portsc & PORT_CEC) 2657 ret += sprintf(str + ret, "CEC "); 2658 if (portsc & PORT_CAS) 2659 ret += sprintf(str + ret, "CAS "); 2660 2661 ret += sprintf(str + ret, "Wake: "); 2662 if (portsc & PORT_WKCONN_E) 2663 ret += sprintf(str + ret, "WCE "); 2664 if (portsc & PORT_WKDISC_E) 2665 ret += sprintf(str + ret, "WDE "); 2666 if (portsc & PORT_WKOC_E) 2667 ret += sprintf(str + ret, "WOE "); 2668 2669 return str; 2670 } 2671 2672 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts) 2673 { 2674 int ret = 0; 2675 2676 ret = sprintf(str, " 0x%08x", usbsts); 2677 2678 if (usbsts == ~(u32)0) 2679 return str; 2680 2681 if (usbsts & STS_HALT) 2682 ret += sprintf(str + ret, " HCHalted"); 2683 if (usbsts & STS_FATAL) 2684 ret += sprintf(str + ret, " HSE"); 2685 if (usbsts & STS_EINT) 2686 ret += sprintf(str + ret, " EINT"); 2687 if (usbsts & STS_PORT) 2688 ret += sprintf(str + ret, " PCD"); 2689 if (usbsts & STS_SAVE) 2690 ret += sprintf(str + ret, " SSS"); 2691 if (usbsts & STS_RESTORE) 2692 ret += sprintf(str + ret, " RSS"); 2693 if (usbsts & STS_SRE) 2694 ret += sprintf(str + ret, " SRE"); 2695 if (usbsts & STS_CNR) 2696 ret += sprintf(str + ret, " CNR"); 2697 if (usbsts & STS_HCE) 2698 ret += sprintf(str + ret, " HCE"); 2699 2700 return str; 2701 } 2702 2703 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell) 2704 { 2705 u8 ep; 2706 u16 stream; 2707 int ret; 2708 2709 ep = (doorbell & 0xff); 2710 stream = doorbell >> 16; 2711 2712 if (slot == 0) { 2713 sprintf(str, "Command Ring %d", doorbell); 2714 return str; 2715 } 2716 ret = sprintf(str, "Slot %d ", slot); 2717 if (ep > 0 && ep < 32) 2718 ret = sprintf(str + ret, "ep%d%s", 2719 ep / 2, 2720 ep % 2 ? "in" : "out"); 2721 else if (ep == 0 || ep < 248) 2722 ret = sprintf(str + ret, "Reserved %d", ep); 2723 else 2724 ret = sprintf(str + ret, "Vendor Defined %d", ep); 2725 if (stream) 2726 ret = sprintf(str + ret, " Stream %d", stream); 2727 2728 return str; 2729 } 2730 2731 static inline const char *xhci_ep_state_string(u8 state) 2732 { 2733 switch (state) { 2734 case EP_STATE_DISABLED: 2735 return "disabled"; 2736 case EP_STATE_RUNNING: 2737 return "running"; 2738 case EP_STATE_HALTED: 2739 return "halted"; 2740 case EP_STATE_STOPPED: 2741 return "stopped"; 2742 case EP_STATE_ERROR: 2743 return "error"; 2744 default: 2745 return "INVALID"; 2746 } 2747 } 2748 2749 static inline const char *xhci_ep_type_string(u8 type) 2750 { 2751 switch (type) { 2752 case ISOC_OUT_EP: 2753 return "Isoc OUT"; 2754 case BULK_OUT_EP: 2755 return "Bulk OUT"; 2756 case INT_OUT_EP: 2757 return "Int OUT"; 2758 case CTRL_EP: 2759 return "Ctrl"; 2760 case ISOC_IN_EP: 2761 return "Isoc IN"; 2762 case BULK_IN_EP: 2763 return "Bulk IN"; 2764 case INT_IN_EP: 2765 return "Int IN"; 2766 default: 2767 return "INVALID"; 2768 } 2769 } 2770 2771 static inline const char *xhci_decode_ep_context(char *str, u32 info, 2772 u32 info2, u64 deq, u32 tx_info) 2773 { 2774 int ret; 2775 2776 u32 esit; 2777 u16 maxp; 2778 u16 avg; 2779 2780 u8 max_pstr; 2781 u8 ep_state; 2782 u8 interval; 2783 u8 ep_type; 2784 u8 burst; 2785 u8 cerr; 2786 u8 mult; 2787 2788 bool lsa; 2789 bool hid; 2790 2791 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2792 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2793 2794 ep_state = info & EP_STATE_MASK; 2795 max_pstr = CTX_TO_EP_MAXPSTREAMS(info); 2796 interval = CTX_TO_EP_INTERVAL(info); 2797 mult = CTX_TO_EP_MULT(info) + 1; 2798 lsa = !!(info & EP_HAS_LSA); 2799 2800 cerr = (info2 & (3 << 1)) >> 1; 2801 ep_type = CTX_TO_EP_TYPE(info2); 2802 hid = !!(info2 & (1 << 7)); 2803 burst = CTX_TO_MAX_BURST(info2); 2804 maxp = MAX_PACKET_DECODED(info2); 2805 2806 avg = EP_AVG_TRB_LENGTH(tx_info); 2807 2808 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2809 xhci_ep_state_string(ep_state), mult, 2810 max_pstr, lsa ? "LSA " : ""); 2811 2812 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2813 (1 << interval) * 125, esit, cerr); 2814 2815 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2816 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2817 burst, maxp, deq); 2818 2819 ret += sprintf(str + ret, "avg trb len %d", avg); 2820 2821 return str; 2822 } 2823 2824 #endif /* __LINUX_XHCI_HCD_H */ 2825