1 /* 2 * xHCI host controller driver PCI Bus Glue. 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 27 #include "xhci.h" 28 #include "xhci-trace.h" 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 34 35 #define PCI_VENDOR_ID_ETRON 0x1b6f 36 #define PCI_DEVICE_ID_EJ168 0x7023 37 38 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 40 41 static const char hcd_name[] = "xhci_hcd"; 42 43 /* called after powerup, by probe or system-pm "wakeup" */ 44 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 45 { 46 /* 47 * TODO: Implement finding debug ports later. 48 * TODO: see if there are any quirks that need to be added to handle 49 * new extended capabilities. 50 */ 51 52 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 53 if (!pci_set_mwi(pdev)) 54 xhci_dbg(xhci, "MWI active\n"); 55 56 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 57 return 0; 58 } 59 60 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 61 { 62 struct pci_dev *pdev = to_pci_dev(dev); 63 64 /* Look for vendor-specific quirks */ 65 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 66 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 67 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 68 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 69 pdev->revision == 0x0) { 70 xhci->quirks |= XHCI_RESET_EP_QUIRK; 71 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 72 "QUIRK: Fresco Logic xHC needs configure" 73 " endpoint cmd after reset endpoint"); 74 } 75 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 76 pdev->revision == 0x4) { 77 xhci->quirks |= XHCI_SLOW_SUSPEND; 78 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 79 "QUIRK: Fresco Logic xHC revision %u" 80 "must be suspended extra slowly", 81 pdev->revision); 82 } 83 /* Fresco Logic confirms: all revisions of this chip do not 84 * support MSI, even though some of them claim to in their PCI 85 * capabilities. 86 */ 87 xhci->quirks |= XHCI_BROKEN_MSI; 88 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 89 "QUIRK: Fresco Logic revision %u " 90 "has broken MSI implementation", 91 pdev->revision); 92 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 93 } 94 95 if (pdev->vendor == PCI_VENDOR_ID_NEC) 96 xhci->quirks |= XHCI_NEC_HOST; 97 98 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 99 xhci->quirks |= XHCI_AMD_0x96_HOST; 100 101 /* AMD PLL quirk */ 102 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 103 xhci->quirks |= XHCI_AMD_PLL_FIX; 104 105 if (pdev->vendor == PCI_VENDOR_ID_AMD) 106 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 107 108 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 109 xhci->quirks |= XHCI_LPM_SUPPORT; 110 xhci->quirks |= XHCI_INTEL_HOST; 111 } 112 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 113 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 114 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 115 xhci->limit_active_eps = 64; 116 xhci->quirks |= XHCI_SW_BW_CHECKING; 117 /* 118 * PPT desktop boards DH77EB and DH77DF will power back on after 119 * a few seconds of being shutdown. The fix for this is to 120 * switch the ports from xHCI to EHCI on shutdown. We can't use 121 * DMI information to find those particular boards (since each 122 * vendor will change the board name), so we have to key off all 123 * PPT chipsets. 124 */ 125 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 126 xhci->quirks |= XHCI_AVOID_BEI; 127 } 128 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 129 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI || 130 pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI)) { 131 /* Workaround for occasional spurious wakeups from S5 (or 132 * any other sleep) on Haswell machines with LPT and LPT-LP 133 * with the new Intel BIOS 134 */ 135 /* Limit the quirk to only known vendors, as this triggers 136 * yet another BIOS bug on some other machines 137 * https://bugzilla.kernel.org/show_bug.cgi?id=66171 138 */ 139 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) 140 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 141 } 142 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 143 pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) { 144 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 145 } 146 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 147 pdev->device == PCI_DEVICE_ID_EJ168) { 148 xhci->quirks |= XHCI_RESET_ON_RESUME; 149 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 150 xhci->quirks |= XHCI_BROKEN_STREAMS; 151 } 152 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 153 pdev->device == 0x0015) 154 xhci->quirks |= XHCI_RESET_ON_RESUME; 155 if (pdev->vendor == PCI_VENDOR_ID_VIA) 156 xhci->quirks |= XHCI_RESET_ON_RESUME; 157 158 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 159 if (pdev->vendor == PCI_VENDOR_ID_VIA && 160 pdev->device == 0x3432) 161 xhci->quirks |= XHCI_BROKEN_STREAMS; 162 163 if (xhci->quirks & XHCI_RESET_ON_RESUME) 164 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 165 "QUIRK: Resetting on resume"); 166 } 167 168 /* called during probe() after chip reset completes */ 169 static int xhci_pci_setup(struct usb_hcd *hcd) 170 { 171 struct xhci_hcd *xhci; 172 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 173 int retval; 174 175 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 176 if (retval) 177 return retval; 178 179 xhci = hcd_to_xhci(hcd); 180 if (!usb_hcd_is_primary_hcd(hcd)) 181 return 0; 182 183 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 184 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 185 186 /* Find any debug ports */ 187 retval = xhci_pci_reinit(xhci, pdev); 188 if (!retval) 189 return retval; 190 191 kfree(xhci); 192 return retval; 193 } 194 195 /* 196 * We need to register our own PCI probe function (instead of the USB core's 197 * function) in order to create a second roothub under xHCI. 198 */ 199 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 200 { 201 int retval; 202 struct xhci_hcd *xhci; 203 struct hc_driver *driver; 204 struct usb_hcd *hcd; 205 206 driver = (struct hc_driver *)id->driver_data; 207 208 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 209 pm_runtime_get_noresume(&dev->dev); 210 211 /* Register the USB 2.0 roothub. 212 * FIXME: USB core must know to register the USB 2.0 roothub first. 213 * This is sort of silly, because we could just set the HCD driver flags 214 * to say USB 2.0, but I'm not sure what the implications would be in 215 * the other parts of the HCD code. 216 */ 217 retval = usb_hcd_pci_probe(dev, id); 218 219 if (retval) 220 goto put_runtime_pm; 221 222 /* USB 2.0 roothub is stored in the PCI device now. */ 223 hcd = dev_get_drvdata(&dev->dev); 224 xhci = hcd_to_xhci(hcd); 225 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 226 pci_name(dev), hcd); 227 if (!xhci->shared_hcd) { 228 retval = -ENOMEM; 229 goto dealloc_usb2_hcd; 230 } 231 232 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset) 233 * is called by usb_add_hcd(). 234 */ 235 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci; 236 237 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 238 IRQF_SHARED); 239 if (retval) 240 goto put_usb3_hcd; 241 /* Roothub already marked as USB 3.0 speed */ 242 243 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 244 HCC_MAX_PSA(xhci->hcc_params) >= 4) 245 xhci->shared_hcd->can_do_streams = 1; 246 247 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 248 pm_runtime_put_noidle(&dev->dev); 249 250 return 0; 251 252 put_usb3_hcd: 253 usb_put_hcd(xhci->shared_hcd); 254 dealloc_usb2_hcd: 255 usb_hcd_pci_remove(dev); 256 put_runtime_pm: 257 pm_runtime_put_noidle(&dev->dev); 258 return retval; 259 } 260 261 static void xhci_pci_remove(struct pci_dev *dev) 262 { 263 struct xhci_hcd *xhci; 264 265 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 266 if (xhci->shared_hcd) { 267 usb_remove_hcd(xhci->shared_hcd); 268 usb_put_hcd(xhci->shared_hcd); 269 } 270 usb_hcd_pci_remove(dev); 271 272 /* Workaround for spurious wakeups at shutdown with HSW */ 273 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 274 pci_set_power_state(dev, PCI_D3hot); 275 276 kfree(xhci); 277 } 278 279 #ifdef CONFIG_PM 280 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 281 { 282 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 283 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 284 285 /* 286 * Systems with the TI redriver that loses port status change events 287 * need to have the registers polled during D3, so avoid D3cold. 288 */ 289 if (xhci_compliance_mode_recovery_timer_quirk_check()) 290 pdev->no_d3cold = true; 291 292 return xhci_suspend(xhci); 293 } 294 295 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 296 { 297 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 298 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 299 int retval = 0; 300 301 /* The BIOS on systems with the Intel Panther Point chipset may or may 302 * not support xHCI natively. That means that during system resume, it 303 * may switch the ports back to EHCI so that users can use their 304 * keyboard to select a kernel from GRUB after resume from hibernate. 305 * 306 * The BIOS is supposed to remember whether the OS had xHCI ports 307 * enabled before resume, and switch the ports back to xHCI when the 308 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 309 * writers. 310 * 311 * Unconditionally switch the ports back to xHCI after a system resume. 312 * It should not matter whether the EHCI or xHCI controller is 313 * resumed first. It's enough to do the switchover in xHCI because 314 * USB core won't notice anything as the hub driver doesn't start 315 * running again until after all the devices (including both EHCI and 316 * xHCI host controllers) have been resumed. 317 */ 318 319 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 320 usb_enable_intel_xhci_ports(pdev); 321 322 retval = xhci_resume(xhci, hibernated); 323 return retval; 324 } 325 #endif /* CONFIG_PM */ 326 327 static const struct hc_driver xhci_pci_hc_driver = { 328 .description = hcd_name, 329 .product_desc = "xHCI Host Controller", 330 .hcd_priv_size = sizeof(struct xhci_hcd *), 331 332 /* 333 * generic hardware linkage 334 */ 335 .irq = xhci_irq, 336 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, 337 338 /* 339 * basic lifecycle operations 340 */ 341 .reset = xhci_pci_setup, 342 .start = xhci_run, 343 #ifdef CONFIG_PM 344 .pci_suspend = xhci_pci_suspend, 345 .pci_resume = xhci_pci_resume, 346 #endif 347 .stop = xhci_stop, 348 .shutdown = xhci_shutdown, 349 350 /* 351 * managing i/o requests and associated device resources 352 */ 353 .urb_enqueue = xhci_urb_enqueue, 354 .urb_dequeue = xhci_urb_dequeue, 355 .alloc_dev = xhci_alloc_dev, 356 .free_dev = xhci_free_dev, 357 .alloc_streams = xhci_alloc_streams, 358 .free_streams = xhci_free_streams, 359 .add_endpoint = xhci_add_endpoint, 360 .drop_endpoint = xhci_drop_endpoint, 361 .endpoint_reset = xhci_endpoint_reset, 362 .check_bandwidth = xhci_check_bandwidth, 363 .reset_bandwidth = xhci_reset_bandwidth, 364 .address_device = xhci_address_device, 365 .enable_device = xhci_enable_device, 366 .update_hub_device = xhci_update_hub_device, 367 .reset_device = xhci_discover_or_reset_device, 368 369 /* 370 * scheduling support 371 */ 372 .get_frame_number = xhci_get_frame, 373 374 /* Root hub support */ 375 .hub_control = xhci_hub_control, 376 .hub_status_data = xhci_hub_status_data, 377 .bus_suspend = xhci_bus_suspend, 378 .bus_resume = xhci_bus_resume, 379 /* 380 * call back when device connected and addressed 381 */ 382 .update_device = xhci_update_device, 383 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, 384 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, 385 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, 386 .find_raw_port_number = xhci_find_raw_port_number, 387 }; 388 389 /*-------------------------------------------------------------------------*/ 390 391 /* PCI driver selection metadata; PCI hotplugging uses this */ 392 static const struct pci_device_id pci_ids[] = { { 393 /* handle any USB 3.0 xHCI controller */ 394 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 395 .driver_data = (unsigned long) &xhci_pci_hc_driver, 396 }, 397 { /* end: all zeroes */ } 398 }; 399 MODULE_DEVICE_TABLE(pci, pci_ids); 400 401 /* pci driver glue; this is a "new style" PCI driver module */ 402 static struct pci_driver xhci_pci_driver = { 403 .name = (char *) hcd_name, 404 .id_table = pci_ids, 405 406 .probe = xhci_pci_probe, 407 .remove = xhci_pci_remove, 408 /* suspend and resume implemented later */ 409 410 .shutdown = usb_hcd_pci_shutdown, 411 #ifdef CONFIG_PM 412 .driver = { 413 .pm = &usb_hcd_pci_pm_ops 414 }, 415 #endif 416 }; 417 418 int __init xhci_register_pci(void) 419 { 420 return pci_register_driver(&xhci_pci_driver); 421 } 422 423 void xhci_unregister_pci(void) 424 { 425 pci_unregister_driver(&xhci_pci_driver); 426 } 427