1 #ifndef __LINUX_UHCI_HCD_H 2 #define __LINUX_UHCI_HCD_H 3 4 #include <linux/list.h> 5 #include <linux/usb.h> 6 7 #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT) 8 #define PIPE_DEVEP_MASK 0x0007ff00 9 10 11 /* 12 * Universal Host Controller Interface data structures and defines 13 */ 14 15 /* Command register */ 16 #define USBCMD 0 17 #define USBCMD_RS 0x0001 /* Run/Stop */ 18 #define USBCMD_HCRESET 0x0002 /* Host reset */ 19 #define USBCMD_GRESET 0x0004 /* Global reset */ 20 #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 21 #define USBCMD_FGR 0x0010 /* Force Global Resume */ 22 #define USBCMD_SWDBG 0x0020 /* SW Debug mode */ 23 #define USBCMD_CF 0x0040 /* Config Flag (sw only) */ 24 #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ 25 26 /* Status register */ 27 #define USBSTS 2 28 #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ 29 #define USBSTS_ERROR 0x0002 /* Interrupt due to error */ 30 #define USBSTS_RD 0x0004 /* Resume Detect */ 31 #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */ 32 #define USBSTS_HCPE 0x0010 /* Host Controller Process Error: 33 * the schedule is buggy */ 34 #define USBSTS_HCH 0x0020 /* HC Halted */ 35 36 /* Interrupt enable register */ 37 #define USBINTR 4 38 #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ 39 #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 40 #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ 41 #define USBINTR_SP 0x0008 /* Short packet interrupt enable */ 42 43 #define USBFRNUM 6 44 #define USBFLBASEADD 8 45 #define USBSOF 12 46 #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */ 47 48 /* USB port status and control registers */ 49 #define USBPORTSC1 16 50 #define USBPORTSC2 18 51 #define USBPORTSC_CCS 0x0001 /* Current Connect Status 52 * ("device present") */ 53 #define USBPORTSC_CSC 0x0002 /* Connect Status Change */ 54 #define USBPORTSC_PE 0x0004 /* Port Enable */ 55 #define USBPORTSC_PEC 0x0008 /* Port Enable Change */ 56 #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */ 57 #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */ 58 #define USBPORTSC_RD 0x0040 /* Resume Detect */ 59 #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */ 60 #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ 61 #define USBPORTSC_PR 0x0200 /* Port Reset */ 62 /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */ 63 #define USBPORTSC_OC 0x0400 /* Over Current condition */ 64 #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */ 65 #define USBPORTSC_SUSP 0x1000 /* Suspend */ 66 #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */ 67 #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */ 68 #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */ 69 70 /* Legacy support register */ 71 #define USBLEGSUP 0xc0 72 #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ 73 #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ 74 #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ 75 76 #define UHCI_PTR_BITS __constant_cpu_to_le32(0x000F) 77 #define UHCI_PTR_TERM __constant_cpu_to_le32(0x0001) 78 #define UHCI_PTR_QH __constant_cpu_to_le32(0x0002) 79 #define UHCI_PTR_DEPTH __constant_cpu_to_le32(0x0004) 80 #define UHCI_PTR_BREADTH __constant_cpu_to_le32(0x0000) 81 82 #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ 83 #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ 84 #define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames 85 * can be scheduled */ 86 87 88 /* 89 * Queue Headers 90 */ 91 92 /* 93 * One role of a QH is to hold a queue of TDs for some endpoint. One QH goes 94 * with each endpoint, and qh->element (updated by the HC) is either: 95 * - the next unprocessed TD in the endpoint's queue, or 96 * - UHCI_PTR_TERM (when there's no more traffic for this endpoint). 97 * 98 * The other role of a QH is to serve as a "skeleton" framelist entry, so we 99 * can easily splice a QH for some endpoint into the schedule at the right 100 * place. Then qh->element is UHCI_PTR_TERM. 101 * 102 * In the schedule, qh->link maintains a list of QHs seen by the HC: 103 * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ... 104 * 105 * qh->node is the software equivalent of qh->link. The differences 106 * are that the software list is doubly-linked and QHs in the UNLINKING 107 * state are on the software list but not the hardware schedule. 108 * 109 * For bookkeeping purposes we maintain QHs even for Isochronous endpoints, 110 * but they never get added to the hardware schedule. 111 */ 112 #define QH_STATE_IDLE 1 /* QH is not being used */ 113 #define QH_STATE_UNLINKING 2 /* QH has been removed from the 114 * schedule but the hardware may 115 * still be using it */ 116 #define QH_STATE_ACTIVE 3 /* QH is on the schedule */ 117 118 struct uhci_qh { 119 /* Hardware fields */ 120 __le32 link; /* Next QH in the schedule */ 121 __le32 element; /* Queue element (TD) pointer */ 122 123 /* Software fields */ 124 dma_addr_t dma_handle; 125 126 struct list_head node; /* Node in the list of QHs */ 127 struct usb_host_endpoint *hep; /* Endpoint information */ 128 struct usb_device *udev; 129 struct list_head queue; /* Queue of urbps for this QH */ 130 struct uhci_qh *skel; /* Skeleton for this QH */ 131 struct uhci_td *dummy_td; /* Dummy TD to end the queue */ 132 struct uhci_td *post_td; /* Last TD completed */ 133 134 unsigned int unlink_frame; /* When the QH was unlinked */ 135 int state; /* QH_STATE_xxx; see above */ 136 int type; /* Queue type (control, bulk, etc) */ 137 138 unsigned int initial_toggle:1; /* Endpoint's current toggle value */ 139 unsigned int needs_fixup:1; /* Must fix the TD toggle values */ 140 unsigned int is_stopped:1; /* Queue was stopped by error/unlink */ 141 } __attribute__((aligned(16))); 142 143 /* 144 * We need a special accessor for the element pointer because it is 145 * subject to asynchronous updates by the controller. 146 */ 147 static inline __le32 qh_element(struct uhci_qh *qh) { 148 __le32 element = qh->element; 149 150 barrier(); 151 return element; 152 } 153 154 155 /* 156 * Transfer Descriptors 157 */ 158 159 /* 160 * for TD <status>: 161 */ 162 #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ 163 #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ 164 #define TD_CTRL_C_ERR_SHIFT 27 165 #define TD_CTRL_LS (1 << 26) /* Low Speed Device */ 166 #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ 167 #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ 168 #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ 169 #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ 170 #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ 171 #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ 172 #define TD_CTRL_NAK (1 << 19) /* NAK Received */ 173 #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ 174 #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ 175 #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */ 176 177 #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ 178 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | \ 179 TD_CTRL_BITSTUFF) 180 181 #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT) 182 #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000) 183 #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \ 184 TD_CTRL_ACTLEN_MASK) /* 1-based */ 185 186 /* 187 * for TD <info>: (a.k.a. Token) 188 */ 189 #define td_token(td) le32_to_cpu((td)->token) 190 #define TD_TOKEN_DEVADDR_SHIFT 8 191 #define TD_TOKEN_TOGGLE_SHIFT 19 192 #define TD_TOKEN_TOGGLE (1 << 19) 193 #define TD_TOKEN_EXPLEN_SHIFT 21 194 #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */ 195 #define TD_TOKEN_PID_MASK 0xFF 196 197 #define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \ 198 TD_TOKEN_EXPLEN_SHIFT) 199 200 #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \ 201 1) & TD_TOKEN_EXPLEN_MASK) 202 #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1) 203 #define uhci_endpoint(token) (((token) >> 15) & 0xf) 204 #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f) 205 #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff) 206 #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK) 207 #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN) 208 #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN) 209 210 /* 211 * The documentation says "4 words for hardware, 4 words for software". 212 * 213 * That's silly, the hardware doesn't care. The hardware only cares that 214 * the hardware words are 16-byte aligned, and we can have any amount of 215 * sw space after the TD entry. 216 * 217 * td->link points to either another TD (not necessarily for the same urb or 218 * even the same endpoint), or nothing (PTR_TERM), or a QH. 219 */ 220 struct uhci_td { 221 /* Hardware fields */ 222 __le32 link; 223 __le32 status; 224 __le32 token; 225 __le32 buffer; 226 227 /* Software fields */ 228 dma_addr_t dma_handle; 229 230 struct list_head list; 231 struct list_head remove_list; 232 233 int frame; /* for iso: what frame? */ 234 struct list_head fl_list; 235 } __attribute__((aligned(16))); 236 237 /* 238 * We need a special accessor for the control/status word because it is 239 * subject to asynchronous updates by the controller. 240 */ 241 static inline u32 td_status(struct uhci_td *td) { 242 __le32 status = td->status; 243 244 barrier(); 245 return le32_to_cpu(status); 246 } 247 248 249 /* 250 * Skeleton Queue Headers 251 */ 252 253 /* 254 * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for 255 * automatic queuing. To make it easy to insert entries into the schedule, 256 * we have a skeleton of QHs for each predefined Interrupt latency, 257 * low-speed control, full-speed control, bulk, and terminating QH 258 * (see explanation for the terminating QH below). 259 * 260 * When we want to add a new QH, we add it to the end of the list for the 261 * skeleton QH. For instance, the schedule list can look like this: 262 * 263 * skel int128 QH 264 * dev 1 interrupt QH 265 * dev 5 interrupt QH 266 * skel int64 QH 267 * skel int32 QH 268 * ... 269 * skel int1 QH 270 * skel low-speed control QH 271 * dev 5 control QH 272 * skel full-speed control QH 273 * skel bulk QH 274 * dev 1 bulk QH 275 * dev 2 bulk QH 276 * skel terminating QH 277 * 278 * The terminating QH is used for 2 reasons: 279 * - To place a terminating TD which is used to workaround a PIIX bug 280 * (see Intel errata for explanation), and 281 * - To loop back to the full-speed control queue for full-speed bandwidth 282 * reclamation. 283 * 284 * There's a special skeleton QH for Isochronous QHs. It never appears 285 * on the schedule, and Isochronous TDs go on the schedule before the 286 * the skeleton QHs. The hardware accesses them directly rather than 287 * through their QH, which is used only for bookkeeping purposes. 288 * While the UHCI spec doesn't forbid the use of QHs for Isochronous, 289 * it doesn't use them either. And the spec says that queues never 290 * advance on an error completion status, which makes them totally 291 * unsuitable for Isochronous transfers. 292 */ 293 294 #define UHCI_NUM_SKELQH 14 295 #define skel_unlink_qh skelqh[0] 296 #define skel_iso_qh skelqh[1] 297 #define skel_int128_qh skelqh[2] 298 #define skel_int64_qh skelqh[3] 299 #define skel_int32_qh skelqh[4] 300 #define skel_int16_qh skelqh[5] 301 #define skel_int8_qh skelqh[6] 302 #define skel_int4_qh skelqh[7] 303 #define skel_int2_qh skelqh[8] 304 #define skel_int1_qh skelqh[9] 305 #define skel_ls_control_qh skelqh[10] 306 #define skel_fs_control_qh skelqh[11] 307 #define skel_bulk_qh skelqh[12] 308 #define skel_term_qh skelqh[13] 309 310 /* 311 * Search tree for determining where <interval> fits in the skelqh[] 312 * skeleton. 313 * 314 * An interrupt request should be placed into the slowest skelqh[] 315 * which meets the interval/period/frequency requirement. 316 * An interrupt request is allowed to be faster than <interval> but not slower. 317 * 318 * For a given <interval>, this function returns the appropriate/matching 319 * skelqh[] index value. 320 */ 321 static inline int __interval_to_skel(int interval) 322 { 323 if (interval < 16) { 324 if (interval < 4) { 325 if (interval < 2) 326 return 9; /* int1 for 0-1 ms */ 327 return 8; /* int2 for 2-3 ms */ 328 } 329 if (interval < 8) 330 return 7; /* int4 for 4-7 ms */ 331 return 6; /* int8 for 8-15 ms */ 332 } 333 if (interval < 64) { 334 if (interval < 32) 335 return 5; /* int16 for 16-31 ms */ 336 return 4; /* int32 for 32-63 ms */ 337 } 338 if (interval < 128) 339 return 3; /* int64 for 64-127 ms */ 340 return 2; /* int128 for 128-255 ms (Max.) */ 341 } 342 343 344 /* 345 * The UHCI controller and root hub 346 */ 347 348 /* 349 * States for the root hub: 350 * 351 * To prevent "bouncing" in the presence of electrical noise, 352 * when there are no devices attached we delay for 1 second in the 353 * RUNNING_NODEVS state before switching to the AUTO_STOPPED state. 354 * 355 * (Note that the AUTO_STOPPED state won't be necessary once the hub 356 * driver learns to autosuspend.) 357 */ 358 enum uhci_rh_state { 359 /* In the following states the HC must be halted. 360 * These two must come first. */ 361 UHCI_RH_RESET, 362 UHCI_RH_SUSPENDED, 363 364 UHCI_RH_AUTO_STOPPED, 365 UHCI_RH_RESUMING, 366 367 /* In this state the HC changes from running to halted, 368 * so it can legally appear either way. */ 369 UHCI_RH_SUSPENDING, 370 371 /* In the following states it's an error if the HC is halted. 372 * These two must come last. */ 373 UHCI_RH_RUNNING, /* The normal state */ 374 UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */ 375 }; 376 377 /* 378 * The full UHCI controller information: 379 */ 380 struct uhci_hcd { 381 382 /* debugfs */ 383 struct dentry *dentry; 384 385 /* Grabbed from PCI */ 386 unsigned long io_addr; 387 388 struct dma_pool *qh_pool; 389 struct dma_pool *td_pool; 390 391 struct uhci_td *term_td; /* Terminating TD, see UHCI bug */ 392 struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QHs */ 393 struct uhci_qh *next_qh; /* Next QH to scan */ 394 395 spinlock_t lock; 396 397 dma_addr_t frame_dma_handle; /* Hardware frame list */ 398 __le32 *frame; 399 void **frame_cpu; /* CPU's frame list */ 400 401 int fsbr; /* Full-speed bandwidth reclamation */ 402 unsigned long fsbrtimeout; /* FSBR delay */ 403 404 enum uhci_rh_state rh_state; 405 unsigned long auto_stop_time; /* When to AUTO_STOP */ 406 407 unsigned int frame_number; /* As of last check */ 408 unsigned int is_stopped; 409 #define UHCI_IS_STOPPED 9999 /* Larger than a frame # */ 410 411 unsigned int scan_in_progress:1; /* Schedule scan is running */ 412 unsigned int need_rescan:1; /* Redo the schedule scan */ 413 unsigned int hc_inaccessible:1; /* HC is suspended or dead */ 414 unsigned int working_RD:1; /* Suspended root hub doesn't 415 need to be polled */ 416 unsigned int is_initialized:1; /* Data structure is usable */ 417 418 /* Support for port suspend/resume/reset */ 419 unsigned long port_c_suspend; /* Bit-arrays of ports */ 420 unsigned long resuming_ports; 421 unsigned long ports_timeout; /* Time to stop signalling */ 422 423 /* List of TDs that are done, but waiting to be freed (race) */ 424 struct list_head td_remove_list; 425 unsigned int td_remove_age; /* Age in frames */ 426 427 struct list_head idle_qh_list; /* Where the idle QHs live */ 428 429 int rh_numports; /* Number of root-hub ports */ 430 431 wait_queue_head_t waitqh; /* endpoint_disable waiters */ 432 int num_waiting; /* Number of waiters */ 433 }; 434 435 /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */ 436 static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd) 437 { 438 return (struct uhci_hcd *) (hcd->hcd_priv); 439 } 440 static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci) 441 { 442 return container_of((void *) uhci, struct usb_hcd, hcd_priv); 443 } 444 445 #define uhci_dev(u) (uhci_to_hcd(u)->self.controller) 446 447 448 /* 449 * Private per-URB data 450 */ 451 struct urb_priv { 452 struct list_head node; /* Node in the QH's urbp list */ 453 454 struct urb *urb; 455 456 struct uhci_qh *qh; /* QH for this URB */ 457 struct list_head td_list; 458 459 unsigned fsbr : 1; /* URB turned on FSBR */ 460 }; 461 462 463 /* 464 * Locking in uhci.c 465 * 466 * Almost everything relating to the hardware schedule and processing 467 * of URBs is protected by uhci->lock. urb->status is protected by 468 * urb->lock; that's the one exception. 469 * 470 * To prevent deadlocks, never lock uhci->lock while holding urb->lock. 471 * The safe order of locking is: 472 * 473 * #1 uhci->lock 474 * #2 urb->lock 475 */ 476 477 478 /* Some special IDs */ 479 480 #define PCI_VENDOR_ID_GENESYS 0x17a0 481 #define PCI_DEVICE_ID_GL880S_UHCI 0x8083 482 483 #endif 484