1 #ifndef __LINUX_UHCI_HCD_H 2 #define __LINUX_UHCI_HCD_H 3 4 #include <linux/list.h> 5 #include <linux/usb.h> 6 7 #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT) 8 #define PIPE_DEVEP_MASK 0x0007ff00 9 10 /* 11 * Universal Host Controller Interface data structures and defines 12 */ 13 14 /* Command register */ 15 #define USBCMD 0 16 #define USBCMD_RS 0x0001 /* Run/Stop */ 17 #define USBCMD_HCRESET 0x0002 /* Host reset */ 18 #define USBCMD_GRESET 0x0004 /* Global reset */ 19 #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 20 #define USBCMD_FGR 0x0010 /* Force Global Resume */ 21 #define USBCMD_SWDBG 0x0020 /* SW Debug mode */ 22 #define USBCMD_CF 0x0040 /* Config Flag (sw only) */ 23 #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ 24 25 /* Status register */ 26 #define USBSTS 2 27 #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ 28 #define USBSTS_ERROR 0x0002 /* Interrupt due to error */ 29 #define USBSTS_RD 0x0004 /* Resume Detect */ 30 #define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */ 31 #define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */ 32 #define USBSTS_HCH 0x0020 /* HC Halted */ 33 34 /* Interrupt enable register */ 35 #define USBINTR 4 36 #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ 37 #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 38 #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ 39 #define USBINTR_SP 0x0008 /* Short packet interrupt enable */ 40 41 #define USBFRNUM 6 42 #define USBFLBASEADD 8 43 #define USBSOF 12 44 45 /* USB port status and control registers */ 46 #define USBPORTSC1 16 47 #define USBPORTSC2 18 48 #define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */ 49 #define USBPORTSC_CSC 0x0002 /* Connect Status Change */ 50 #define USBPORTSC_PE 0x0004 /* Port Enable */ 51 #define USBPORTSC_PEC 0x0008 /* Port Enable Change */ 52 #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */ 53 #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */ 54 #define USBPORTSC_RD 0x0040 /* Resume Detect */ 55 #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */ 56 #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ 57 #define USBPORTSC_PR 0x0200 /* Port Reset */ 58 /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */ 59 #define USBPORTSC_OC 0x0400 /* Over Current condition */ 60 #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */ 61 #define USBPORTSC_SUSP 0x1000 /* Suspend */ 62 #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */ 63 #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */ 64 #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */ 65 66 /* Legacy support register */ 67 #define USBLEGSUP 0xc0 68 #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ 69 70 #define UHCI_NULL_DATA_SIZE 0x7FF /* for UHCI controller TD */ 71 72 #define UHCI_PTR_BITS cpu_to_le32(0x000F) 73 #define UHCI_PTR_TERM cpu_to_le32(0x0001) 74 #define UHCI_PTR_QH cpu_to_le32(0x0002) 75 #define UHCI_PTR_DEPTH cpu_to_le32(0x0004) 76 #define UHCI_PTR_BREADTH cpu_to_le32(0x0000) 77 78 #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ 79 #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ 80 #define CAN_SCHEDULE_FRAMES 1000 /* how far future frames can be scheduled */ 81 82 struct uhci_frame_list { 83 __le32 frame[UHCI_NUMFRAMES]; 84 85 void *frame_cpu[UHCI_NUMFRAMES]; 86 87 dma_addr_t dma_handle; 88 }; 89 90 struct urb_priv; 91 92 /* 93 * One role of a QH is to hold a queue of TDs for some endpoint. Each QH is 94 * used with one URB, and qh->element (updated by the HC) is either: 95 * - the next unprocessed TD for the URB, or 96 * - UHCI_PTR_TERM (when there's no more traffic for this endpoint), or 97 * - the QH for the next URB queued to the same endpoint. 98 * 99 * The other role of a QH is to serve as a "skeleton" framelist entry, so we 100 * can easily splice a QH for some endpoint into the schedule at the right 101 * place. Then qh->element is UHCI_PTR_TERM. 102 * 103 * In the frame list, qh->link maintains a list of QHs seen by the HC: 104 * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ... 105 */ 106 struct uhci_qh { 107 /* Hardware fields */ 108 __le32 link; /* Next queue */ 109 __le32 element; /* Queue element pointer */ 110 111 /* Software fields */ 112 dma_addr_t dma_handle; 113 114 struct usb_device *dev; 115 struct urb_priv *urbp; 116 117 struct list_head list; /* P: uhci->frame_list_lock */ 118 struct list_head remove_list; /* P: uhci->remove_list_lock */ 119 } __attribute__((aligned(16))); 120 121 /* 122 * We need a special accessor for the element pointer because it is 123 * subject to asynchronous updates by the controller 124 */ 125 static __le32 inline qh_element(struct uhci_qh *qh) { 126 __le32 element = qh->element; 127 128 barrier(); 129 return element; 130 } 131 132 /* 133 * for TD <status>: 134 */ 135 #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ 136 #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ 137 #define TD_CTRL_C_ERR_SHIFT 27 138 #define TD_CTRL_LS (1 << 26) /* Low Speed Device */ 139 #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ 140 #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ 141 #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ 142 #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ 143 #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ 144 #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ 145 #define TD_CTRL_NAK (1 << 19) /* NAK Received */ 146 #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ 147 #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ 148 #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */ 149 150 #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ 151 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF) 152 153 #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT) 154 #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000) 155 #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & TD_CTRL_ACTLEN_MASK) /* 1-based */ 156 157 /* 158 * for TD <info>: (a.k.a. Token) 159 */ 160 #define td_token(td) le32_to_cpu((td)->token) 161 #define TD_TOKEN_DEVADDR_SHIFT 8 162 #define TD_TOKEN_TOGGLE_SHIFT 19 163 #define TD_TOKEN_TOGGLE (1 << 19) 164 #define TD_TOKEN_EXPLEN_SHIFT 21 165 #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n - 1 */ 166 #define TD_TOKEN_PID_MASK 0xFF 167 168 #define uhci_explen(len) ((len) << TD_TOKEN_EXPLEN_SHIFT) 169 170 #define uhci_expected_length(token) ((((token) >> 21) + 1) & TD_TOKEN_EXPLEN_MASK) 171 #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1) 172 #define uhci_endpoint(token) (((token) >> 15) & 0xf) 173 #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f) 174 #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff) 175 #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK) 176 #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN) 177 #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN) 178 179 /* 180 * The documentation says "4 words for hardware, 4 words for software". 181 * 182 * That's silly, the hardware doesn't care. The hardware only cares that 183 * the hardware words are 16-byte aligned, and we can have any amount of 184 * sw space after the TD entry as far as I can tell. 185 * 186 * But let's just go with the documentation, at least for 32-bit machines. 187 * On 64-bit machines we probably want to take advantage of the fact that 188 * hw doesn't really care about the size of the sw-only area. 189 * 190 * Alas, not anymore, we have more than 4 words for software, woops. 191 * Everything still works tho, surprise! -jerdfelt 192 * 193 * td->link points to either another TD (not necessarily for the same urb or 194 * even the same endpoint), or nothing (PTR_TERM), or a QH (for queued urbs) 195 */ 196 struct uhci_td { 197 /* Hardware fields */ 198 __le32 link; 199 __le32 status; 200 __le32 token; 201 __le32 buffer; 202 203 /* Software fields */ 204 dma_addr_t dma_handle; 205 206 struct usb_device *dev; 207 struct urb *urb; 208 209 struct list_head list; /* P: urb->lock */ 210 struct list_head remove_list; /* P: uhci->td_remove_list_lock */ 211 212 int frame; /* for iso: what frame? */ 213 struct list_head fl_list; /* P: uhci->frame_list_lock */ 214 } __attribute__((aligned(16))); 215 216 /* 217 * We need a special accessor for the control/status word because it is 218 * subject to asynchronous updates by the controller 219 */ 220 static u32 inline td_status(struct uhci_td *td) { 221 __le32 status = td->status; 222 223 barrier(); 224 return le32_to_cpu(status); 225 } 226 227 228 /* 229 * The UHCI driver places Interrupt, Control and Bulk into QH's both 230 * to group together TD's for one transfer, and also to faciliate queuing 231 * of URB's. To make it easy to insert entries into the schedule, we have 232 * a skeleton of QH's for each predefined Interrupt latency, low-speed 233 * control, full-speed control and terminating QH (see explanation for 234 * the terminating QH below). 235 * 236 * When we want to add a new QH, we add it to the end of the list for the 237 * skeleton QH. 238 * 239 * For instance, the queue can look like this: 240 * 241 * skel int128 QH 242 * dev 1 interrupt QH 243 * dev 5 interrupt QH 244 * skel int64 QH 245 * skel int32 QH 246 * ... 247 * skel int1 QH 248 * skel low-speed control QH 249 * dev 5 control QH 250 * skel full-speed control QH 251 * skel bulk QH 252 * dev 1 bulk QH 253 * dev 2 bulk QH 254 * skel terminating QH 255 * 256 * The terminating QH is used for 2 reasons: 257 * - To place a terminating TD which is used to workaround a PIIX bug 258 * (see Intel errata for explanation) 259 * - To loop back to the full-speed control queue for full-speed bandwidth 260 * reclamation 261 * 262 * Isochronous transfers are stored before the start of the skeleton 263 * schedule and don't use QH's. While the UHCI spec doesn't forbid the 264 * use of QH's for Isochronous, it doesn't use them either. Since we don't 265 * need to use them either, we follow the spec diagrams in hope that it'll 266 * be more compatible with future UHCI implementations. 267 */ 268 269 #define UHCI_NUM_SKELQH 12 270 #define skel_int128_qh skelqh[0] 271 #define skel_int64_qh skelqh[1] 272 #define skel_int32_qh skelqh[2] 273 #define skel_int16_qh skelqh[3] 274 #define skel_int8_qh skelqh[4] 275 #define skel_int4_qh skelqh[5] 276 #define skel_int2_qh skelqh[6] 277 #define skel_int1_qh skelqh[7] 278 #define skel_ls_control_qh skelqh[8] 279 #define skel_fs_control_qh skelqh[9] 280 #define skel_bulk_qh skelqh[10] 281 #define skel_term_qh skelqh[11] 282 283 /* 284 * Search tree for determining where <interval> fits in the skelqh[] 285 * skeleton. 286 * 287 * An interrupt request should be placed into the slowest skelqh[] 288 * which meets the interval/period/frequency requirement. 289 * An interrupt request is allowed to be faster than <interval> but not slower. 290 * 291 * For a given <interval>, this function returns the appropriate/matching 292 * skelqh[] index value. 293 */ 294 static inline int __interval_to_skel(int interval) 295 { 296 if (interval < 16) { 297 if (interval < 4) { 298 if (interval < 2) 299 return 7; /* int1 for 0-1 ms */ 300 return 6; /* int2 for 2-3 ms */ 301 } 302 if (interval < 8) 303 return 5; /* int4 for 4-7 ms */ 304 return 4; /* int8 for 8-15 ms */ 305 } 306 if (interval < 64) { 307 if (interval < 32) 308 return 3; /* int16 for 16-31 ms */ 309 return 2; /* int32 for 32-63 ms */ 310 } 311 if (interval < 128) 312 return 1; /* int64 for 64-127 ms */ 313 return 0; /* int128 for 128-255 ms (Max.) */ 314 } 315 316 /* 317 * Device states for the host controller. 318 * 319 * To prevent "bouncing" in the presence of electrical noise, 320 * we insist on a 1-second "grace" period, before switching to 321 * the RUNNING or SUSPENDED states, during which the state is 322 * not allowed to change. 323 * 324 * The resume process is divided into substates in order to avoid 325 * potentially length delays during the timer handler. 326 * 327 * States in which the host controller is halted must have values <= 0. 328 */ 329 enum uhci_state { 330 UHCI_RESET, 331 UHCI_RUNNING_GRACE, /* Before RUNNING */ 332 UHCI_RUNNING, /* The normal state */ 333 UHCI_SUSPENDING_GRACE, /* Before SUSPENDED */ 334 UHCI_SUSPENDED = -10, /* When no devices are attached */ 335 UHCI_RESUMING_1, 336 UHCI_RESUMING_2 337 }; 338 339 /* 340 * This describes the full uhci information. 341 * 342 * Note how the "proper" USB information is just 343 * a subset of what the full implementation needs. 344 */ 345 struct uhci_hcd { 346 347 /* debugfs */ 348 struct dentry *dentry; 349 350 /* Grabbed from PCI */ 351 unsigned long io_addr; 352 353 struct dma_pool *qh_pool; 354 struct dma_pool *td_pool; 355 356 struct usb_bus *bus; 357 358 struct uhci_td *term_td; /* Terminating TD, see UHCI bug */ 359 struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QH's */ 360 361 spinlock_t lock; 362 struct uhci_frame_list *fl; /* P: uhci->lock */ 363 int fsbr; /* Full-speed bandwidth reclamation */ 364 unsigned long fsbrtimeout; /* FSBR delay */ 365 366 enum uhci_state state; /* FIXME: needs a spinlock */ 367 unsigned long state_end; /* Time of next transition */ 368 unsigned int frame_number; /* As of last check */ 369 unsigned int is_stopped; 370 #define UHCI_IS_STOPPED 9999 /* Larger than a frame # */ 371 372 unsigned int scan_in_progress:1; /* Schedule scan is running */ 373 unsigned int need_rescan:1; /* Redo the schedule scan */ 374 unsigned int resume_detect:1; /* Need a Global Resume */ 375 376 /* Support for port suspend/resume/reset */ 377 unsigned long port_c_suspend; /* Bit-arrays of ports */ 378 unsigned long suspended_ports; 379 unsigned long resuming_ports; 380 unsigned long ports_timeout; /* Time to stop signalling */ 381 382 /* Main list of URB's currently controlled by this HC */ 383 struct list_head urb_list; /* P: uhci->lock */ 384 385 /* List of QH's that are done, but waiting to be unlinked (race) */ 386 struct list_head qh_remove_list; /* P: uhci->lock */ 387 unsigned int qh_remove_age; /* Age in frames */ 388 389 /* List of TD's that are done, but waiting to be freed (race) */ 390 struct list_head td_remove_list; /* P: uhci->lock */ 391 unsigned int td_remove_age; /* Age in frames */ 392 393 /* List of asynchronously unlinked URB's */ 394 struct list_head urb_remove_list; /* P: uhci->lock */ 395 unsigned int urb_remove_age; /* Age in frames */ 396 397 /* List of URB's awaiting completion callback */ 398 struct list_head complete_list; /* P: uhci->lock */ 399 400 int rh_numports; 401 402 struct timer_list stall_timer; 403 404 wait_queue_head_t waitqh; /* endpoint_disable waiters */ 405 }; 406 407 /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */ 408 static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd) 409 { 410 return (struct uhci_hcd *) (hcd->hcd_priv); 411 } 412 static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci) 413 { 414 return container_of((void *) uhci, struct usb_hcd, hcd_priv); 415 } 416 417 #define uhci_dev(u) (uhci_to_hcd(u)->self.controller) 418 419 struct urb_priv { 420 struct list_head urb_list; 421 422 struct urb *urb; 423 424 struct uhci_qh *qh; /* QH for this URB */ 425 struct list_head td_list; /* P: urb->lock */ 426 427 unsigned fsbr : 1; /* URB turned on FSBR */ 428 unsigned fsbr_timeout : 1; /* URB timed out on FSBR */ 429 unsigned queued : 1; /* QH was queued (not linked in) */ 430 unsigned short_control_packet : 1; /* If we get a short packet during */ 431 /* a control transfer, retrigger */ 432 /* the status phase */ 433 434 unsigned long inserttime; /* In jiffies */ 435 unsigned long fsbrtime; /* In jiffies */ 436 437 struct list_head queue_list; /* P: uhci->frame_list_lock */ 438 }; 439 440 /* 441 * Locking in uhci.c 442 * 443 * Almost everything relating to the hardware schedule and processing 444 * of URBs is protected by uhci->lock. urb->status is protected by 445 * urb->lock; that's the one exception. 446 * 447 * To prevent deadlocks, never lock uhci->lock while holding urb->lock. 448 * The safe order of locking is: 449 * 450 * #1 uhci->lock 451 * #2 urb->lock 452 */ 453 454 #endif 455