1 /* 2 * Universal Host Controller Interface driver for USB. 3 * 4 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 5 * 6 * (C) Copyright 1999 Linus Torvalds 7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com 8 * (C) Copyright 1999 Randy Dunlap 9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de 10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de 11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch 12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at 13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface 14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). 15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) 16 * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu 17 * 18 * Intel documents this fairly well, and as far as I know there 19 * are no royalties or anything like that, but even so there are 20 * people who decided that they want to do the same thing in a 21 * completely different way. 22 * 23 * WARNING! The USB documentation is downright evil. Most of it 24 * is just crap, written by a committee. You're better off ignoring 25 * most of it, the important stuff is: 26 * - the low-level protocol (fairly simple but lots of small details) 27 * - working around the horridness of the rest 28 */ 29 30 #include <linux/config.h> 31 #ifdef CONFIG_USB_DEBUG 32 #define DEBUG 33 #else 34 #undef DEBUG 35 #endif 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/kernel.h> 39 #include <linux/init.h> 40 #include <linux/delay.h> 41 #include <linux/ioport.h> 42 #include <linux/sched.h> 43 #include <linux/slab.h> 44 #include <linux/smp_lock.h> 45 #include <linux/errno.h> 46 #include <linux/unistd.h> 47 #include <linux/interrupt.h> 48 #include <linux/spinlock.h> 49 #include <linux/debugfs.h> 50 #include <linux/pm.h> 51 #include <linux/dmapool.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/usb.h> 54 #include <linux/bitops.h> 55 56 #include <asm/uaccess.h> 57 #include <asm/io.h> 58 #include <asm/irq.h> 59 #include <asm/system.h> 60 61 #include "../core/hcd.h" 62 #include "uhci-hcd.h" 63 64 /* 65 * Version Information 66 */ 67 #define DRIVER_VERSION "v2.2" 68 #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \ 69 Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \ 70 Alan Stern" 71 #define DRIVER_DESC "USB Universal Host Controller Interface driver" 72 73 /* 74 * debug = 0, no debugging messages 75 * debug = 1, dump failed URB's except for stalls 76 * debug = 2, dump all failed URB's (including stalls) 77 * show all queues in /debug/uhci/[pci_addr] 78 * debug = 3, show all TD's in URB's when dumping 79 */ 80 #ifdef DEBUG 81 static int debug = 1; 82 #else 83 static int debug = 0; 84 #endif 85 module_param(debug, int, S_IRUGO | S_IWUSR); 86 MODULE_PARM_DESC(debug, "Debug level"); 87 static char *errbuf; 88 #define ERRBUF_LEN (32 * 1024) 89 90 static kmem_cache_t *uhci_up_cachep; /* urb_priv */ 91 92 static void uhci_get_current_frame_number(struct uhci_hcd *uhci); 93 static void hc_state_transitions(struct uhci_hcd *uhci); 94 95 /* If a transfer is still active after this much time, turn off FSBR */ 96 #define IDLE_TIMEOUT msecs_to_jiffies(50) 97 #define FSBR_DELAY msecs_to_jiffies(50) 98 99 /* When we timeout an idle transfer for FSBR, we'll switch it over to */ 100 /* depth first traversal. We'll do it in groups of this number of TD's */ 101 /* to make sure it doesn't hog all of the bandwidth */ 102 #define DEPTH_INTERVAL 5 103 104 #include "uhci-hub.c" 105 #include "uhci-debug.c" 106 #include "uhci-q.c" 107 108 static int init_stall_timer(struct usb_hcd *hcd); 109 110 static void stall_callback(unsigned long ptr) 111 { 112 struct usb_hcd *hcd = (struct usb_hcd *)ptr; 113 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 114 struct urb_priv *up; 115 unsigned long flags; 116 117 spin_lock_irqsave(&uhci->lock, flags); 118 uhci_scan_schedule(uhci, NULL); 119 120 list_for_each_entry(up, &uhci->urb_list, urb_list) { 121 struct urb *u = up->urb; 122 123 spin_lock(&u->lock); 124 125 /* Check if the FSBR timed out */ 126 if (up->fsbr && !up->fsbr_timeout && time_after_eq(jiffies, up->fsbrtime + IDLE_TIMEOUT)) 127 uhci_fsbr_timeout(uhci, u); 128 129 spin_unlock(&u->lock); 130 } 131 132 /* Really disable FSBR */ 133 if (!uhci->fsbr && uhci->fsbrtimeout && time_after_eq(jiffies, uhci->fsbrtimeout)) { 134 uhci->fsbrtimeout = 0; 135 uhci->skel_term_qh->link = UHCI_PTR_TERM; 136 } 137 138 /* Poll for and perform state transitions */ 139 hc_state_transitions(uhci); 140 if (unlikely(uhci->suspended_ports && uhci->state != UHCI_SUSPENDED)) 141 uhci_check_ports(uhci); 142 143 init_stall_timer(hcd); 144 spin_unlock_irqrestore(&uhci->lock, flags); 145 } 146 147 static int init_stall_timer(struct usb_hcd *hcd) 148 { 149 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 150 151 init_timer(&uhci->stall_timer); 152 uhci->stall_timer.function = stall_callback; 153 uhci->stall_timer.data = (unsigned long)hcd; 154 uhci->stall_timer.expires = jiffies + msecs_to_jiffies(100); 155 add_timer(&uhci->stall_timer); 156 157 return 0; 158 } 159 160 static irqreturn_t uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs) 161 { 162 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 163 unsigned long io_addr = uhci->io_addr; 164 unsigned short status; 165 166 /* 167 * Read the interrupt status, and write it back to clear the 168 * interrupt cause. Contrary to the UHCI specification, the 169 * "HC Halted" status bit is persistent: it is RO, not R/WC. 170 */ 171 status = inw(io_addr + USBSTS); 172 if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ 173 return IRQ_NONE; 174 outw(status, io_addr + USBSTS); /* Clear it */ 175 176 if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { 177 if (status & USBSTS_HSE) 178 dev_err(uhci_dev(uhci), "host system error, " 179 "PCI problems?\n"); 180 if (status & USBSTS_HCPE) 181 dev_err(uhci_dev(uhci), "host controller process " 182 "error, something bad happened!\n"); 183 if ((status & USBSTS_HCH) && uhci->state > 0) { 184 dev_err(uhci_dev(uhci), "host controller halted, " 185 "very bad!\n"); 186 /* FIXME: Reset the controller, fix the offending TD */ 187 } 188 } 189 190 if (status & USBSTS_RD) 191 uhci->resume_detect = 1; 192 193 spin_lock(&uhci->lock); 194 uhci_scan_schedule(uhci, regs); 195 spin_unlock(&uhci->lock); 196 197 return IRQ_HANDLED; 198 } 199 200 static void reset_hc(struct uhci_hcd *uhci) 201 { 202 unsigned long io_addr = uhci->io_addr; 203 204 /* Turn off PIRQ, SMI, and all interrupts. This also turns off 205 * the BIOS's USB Legacy Support. 206 */ 207 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0); 208 outw(0, uhci->io_addr + USBINTR); 209 210 /* Global reset for 50ms */ 211 uhci->state = UHCI_RESET; 212 outw(USBCMD_GRESET, io_addr + USBCMD); 213 msleep(50); 214 outw(0, io_addr + USBCMD); 215 216 /* Another 10ms delay */ 217 msleep(10); 218 uhci->resume_detect = 0; 219 uhci->is_stopped = UHCI_IS_STOPPED; 220 } 221 222 static void suspend_hc(struct uhci_hcd *uhci) 223 { 224 unsigned long io_addr = uhci->io_addr; 225 226 dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); 227 uhci->state = UHCI_SUSPENDED; 228 uhci->resume_detect = 0; 229 outw(USBCMD_EGSM, io_addr + USBCMD); 230 231 /* FIXME: Wait for the controller to actually stop */ 232 uhci_get_current_frame_number(uhci); 233 uhci->is_stopped = UHCI_IS_STOPPED; 234 235 uhci_scan_schedule(uhci, NULL); 236 } 237 238 static void wakeup_hc(struct uhci_hcd *uhci) 239 { 240 unsigned long io_addr = uhci->io_addr; 241 242 switch (uhci->state) { 243 case UHCI_SUSPENDED: /* Start the resume */ 244 dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); 245 246 /* Global resume for >= 20ms */ 247 outw(USBCMD_FGR | USBCMD_EGSM, io_addr + USBCMD); 248 uhci->state = UHCI_RESUMING_1; 249 uhci->state_end = jiffies + msecs_to_jiffies(20); 250 uhci->is_stopped = 0; 251 break; 252 253 case UHCI_RESUMING_1: /* End global resume */ 254 uhci->state = UHCI_RESUMING_2; 255 outw(0, io_addr + USBCMD); 256 /* Falls through */ 257 258 case UHCI_RESUMING_2: /* Wait for EOP to be sent */ 259 if (inw(io_addr + USBCMD) & USBCMD_FGR) 260 break; 261 262 /* Run for at least 1 second, and 263 * mark it configured with a 64-byte max packet */ 264 uhci->state = UHCI_RUNNING_GRACE; 265 uhci->state_end = jiffies + HZ; 266 outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, 267 io_addr + USBCMD); 268 break; 269 270 case UHCI_RUNNING_GRACE: /* Now allowed to suspend */ 271 uhci->state = UHCI_RUNNING; 272 break; 273 274 default: 275 break; 276 } 277 } 278 279 static int ports_active(struct uhci_hcd *uhci) 280 { 281 unsigned long io_addr = uhci->io_addr; 282 int connection = 0; 283 int i; 284 285 for (i = 0; i < uhci->rh_numports; i++) 286 connection |= (inw(io_addr + USBPORTSC1 + i * 2) & USBPORTSC_CCS); 287 288 return connection; 289 } 290 291 static int suspend_allowed(struct uhci_hcd *uhci) 292 { 293 unsigned long io_addr = uhci->io_addr; 294 int i; 295 296 if (to_pci_dev(uhci_dev(uhci))->vendor != PCI_VENDOR_ID_INTEL) 297 return 1; 298 299 /* Some of Intel's USB controllers have a bug that causes false 300 * resume indications if any port has an over current condition. 301 * To prevent problems, we will not allow a global suspend if 302 * any ports are OC. 303 * 304 * Some motherboards using Intel's chipsets (but not using all 305 * the USB ports) appear to hardwire the over current inputs active 306 * to disable the USB ports. 307 */ 308 309 /* check for over current condition on any port */ 310 for (i = 0; i < uhci->rh_numports; i++) { 311 if (inw(io_addr + USBPORTSC1 + i * 2) & USBPORTSC_OC) 312 return 0; 313 } 314 315 return 1; 316 } 317 318 static void hc_state_transitions(struct uhci_hcd *uhci) 319 { 320 switch (uhci->state) { 321 case UHCI_RUNNING: 322 323 /* global suspend if nothing connected for 1 second */ 324 if (!ports_active(uhci) && suspend_allowed(uhci)) { 325 uhci->state = UHCI_SUSPENDING_GRACE; 326 uhci->state_end = jiffies + HZ; 327 } 328 break; 329 330 case UHCI_SUSPENDING_GRACE: 331 if (ports_active(uhci)) 332 uhci->state = UHCI_RUNNING; 333 else if (time_after_eq(jiffies, uhci->state_end)) 334 suspend_hc(uhci); 335 break; 336 337 case UHCI_SUSPENDED: 338 339 /* wakeup if requested by a device */ 340 if (uhci->resume_detect) 341 wakeup_hc(uhci); 342 break; 343 344 case UHCI_RESUMING_1: 345 case UHCI_RESUMING_2: 346 case UHCI_RUNNING_GRACE: 347 if (time_after_eq(jiffies, uhci->state_end)) 348 wakeup_hc(uhci); 349 break; 350 351 default: 352 break; 353 } 354 } 355 356 /* 357 * Store the current frame number in uhci->frame_number if the controller 358 * is runnning 359 */ 360 static void uhci_get_current_frame_number(struct uhci_hcd *uhci) 361 { 362 if (!uhci->is_stopped) 363 uhci->frame_number = inw(uhci->io_addr + USBFRNUM); 364 } 365 366 static int start_hc(struct uhci_hcd *uhci) 367 { 368 unsigned long io_addr = uhci->io_addr; 369 int timeout = 10; 370 371 /* 372 * Reset the HC - this will force us to get a 373 * new notification of any already connected 374 * ports due to the virtual disconnect that it 375 * implies. 376 */ 377 outw(USBCMD_HCRESET, io_addr + USBCMD); 378 while (inw(io_addr + USBCMD) & USBCMD_HCRESET) { 379 if (--timeout < 0) { 380 dev_err(uhci_dev(uhci), "USBCMD_HCRESET timed out!\n"); 381 return -ETIMEDOUT; 382 } 383 msleep(1); 384 } 385 386 /* Mark controller as running before we enable interrupts */ 387 uhci_to_hcd(uhci)->state = HC_STATE_RUNNING; 388 389 /* Turn on PIRQ and all interrupts */ 390 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 391 USBLEGSUP_DEFAULT); 392 outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP, 393 io_addr + USBINTR); 394 395 /* Start at frame 0 */ 396 outw(0, io_addr + USBFRNUM); 397 outl(uhci->fl->dma_handle, io_addr + USBFLBASEADD); 398 399 /* Run and mark it configured with a 64-byte max packet */ 400 uhci->state = UHCI_RUNNING_GRACE; 401 uhci->state_end = jiffies + HZ; 402 outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, io_addr + USBCMD); 403 uhci->is_stopped = 0; 404 405 return 0; 406 } 407 408 /* 409 * De-allocate all resources 410 */ 411 static void release_uhci(struct uhci_hcd *uhci) 412 { 413 int i; 414 415 for (i = 0; i < UHCI_NUM_SKELQH; i++) 416 if (uhci->skelqh[i]) { 417 uhci_free_qh(uhci, uhci->skelqh[i]); 418 uhci->skelqh[i] = NULL; 419 } 420 421 if (uhci->term_td) { 422 uhci_free_td(uhci, uhci->term_td); 423 uhci->term_td = NULL; 424 } 425 426 if (uhci->qh_pool) { 427 dma_pool_destroy(uhci->qh_pool); 428 uhci->qh_pool = NULL; 429 } 430 431 if (uhci->td_pool) { 432 dma_pool_destroy(uhci->td_pool); 433 uhci->td_pool = NULL; 434 } 435 436 if (uhci->fl) { 437 dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl), 438 uhci->fl, uhci->fl->dma_handle); 439 uhci->fl = NULL; 440 } 441 442 if (uhci->dentry) { 443 debugfs_remove(uhci->dentry); 444 uhci->dentry = NULL; 445 } 446 } 447 448 static int uhci_reset(struct usb_hcd *hcd) 449 { 450 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 451 452 uhci->io_addr = (unsigned long) hcd->rsrc_start; 453 454 /* Kick BIOS off this hardware and reset, so we won't get 455 * interrupts from any previous setup. 456 */ 457 reset_hc(uhci); 458 return 0; 459 } 460 461 /* 462 * Allocate a frame list, and then setup the skeleton 463 * 464 * The hardware doesn't really know any difference 465 * in the queues, but the order does matter for the 466 * protocols higher up. The order is: 467 * 468 * - any isochronous events handled before any 469 * of the queues. We don't do that here, because 470 * we'll create the actual TD entries on demand. 471 * - The first queue is the interrupt queue. 472 * - The second queue is the control queue, split into low- and full-speed 473 * - The third queue is bulk queue. 474 * - The fourth queue is the bandwidth reclamation queue, which loops back 475 * to the full-speed control queue. 476 */ 477 static int uhci_start(struct usb_hcd *hcd) 478 { 479 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 480 int retval = -EBUSY; 481 int i, port; 482 unsigned io_size; 483 dma_addr_t dma_handle; 484 struct usb_device *udev; 485 struct dentry *dentry; 486 487 io_size = (unsigned) hcd->rsrc_len; 488 489 dentry = debugfs_create_file(hcd->self.bus_name, S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, uhci, &uhci_debug_operations); 490 if (!dentry) { 491 dev_err(uhci_dev(uhci), "couldn't create uhci debugfs entry\n"); 492 retval = -ENOMEM; 493 goto err_create_debug_entry; 494 } 495 uhci->dentry = dentry; 496 497 uhci->fsbr = 0; 498 uhci->fsbrtimeout = 0; 499 500 spin_lock_init(&uhci->lock); 501 INIT_LIST_HEAD(&uhci->qh_remove_list); 502 503 INIT_LIST_HEAD(&uhci->td_remove_list); 504 505 INIT_LIST_HEAD(&uhci->urb_remove_list); 506 507 INIT_LIST_HEAD(&uhci->urb_list); 508 509 INIT_LIST_HEAD(&uhci->complete_list); 510 511 init_waitqueue_head(&uhci->waitqh); 512 513 uhci->fl = dma_alloc_coherent(uhci_dev(uhci), sizeof(*uhci->fl), 514 &dma_handle, 0); 515 if (!uhci->fl) { 516 dev_err(uhci_dev(uhci), "unable to allocate " 517 "consistent memory for frame list\n"); 518 goto err_alloc_fl; 519 } 520 521 memset((void *)uhci->fl, 0, sizeof(*uhci->fl)); 522 523 uhci->fl->dma_handle = dma_handle; 524 525 uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), 526 sizeof(struct uhci_td), 16, 0); 527 if (!uhci->td_pool) { 528 dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); 529 goto err_create_td_pool; 530 } 531 532 uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), 533 sizeof(struct uhci_qh), 16, 0); 534 if (!uhci->qh_pool) { 535 dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); 536 goto err_create_qh_pool; 537 } 538 539 /* Initialize the root hub */ 540 541 /* UHCI specs says devices must have 2 ports, but goes on to say */ 542 /* they may have more but give no way to determine how many they */ 543 /* have. However, according to the UHCI spec, Bit 7 is always set */ 544 /* to 1. So we try to use this to our advantage */ 545 for (port = 0; port < (io_size - 0x10) / 2; port++) { 546 unsigned int portstatus; 547 548 portstatus = inw(uhci->io_addr + 0x10 + (port * 2)); 549 if (!(portstatus & 0x0080)) 550 break; 551 } 552 if (debug) 553 dev_info(uhci_dev(uhci), "detected %d ports\n", port); 554 555 /* This is experimental so anything less than 2 or greater than 8 is */ 556 /* something weird and we'll ignore it */ 557 if (port < 2 || port > UHCI_RH_MAXCHILD) { 558 dev_info(uhci_dev(uhci), "port count misdetected? " 559 "forcing to 2 ports\n"); 560 port = 2; 561 } 562 563 uhci->rh_numports = port; 564 565 udev = usb_alloc_dev(NULL, &hcd->self, 0); 566 if (!udev) { 567 dev_err(uhci_dev(uhci), "unable to allocate root hub\n"); 568 goto err_alloc_root_hub; 569 } 570 571 uhci->term_td = uhci_alloc_td(uhci, udev); 572 if (!uhci->term_td) { 573 dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); 574 goto err_alloc_term_td; 575 } 576 577 for (i = 0; i < UHCI_NUM_SKELQH; i++) { 578 uhci->skelqh[i] = uhci_alloc_qh(uhci, udev); 579 if (!uhci->skelqh[i]) { 580 dev_err(uhci_dev(uhci), "unable to allocate QH\n"); 581 goto err_alloc_skelqh; 582 } 583 } 584 585 /* 586 * 8 Interrupt queues; link all higher int queues to int1, 587 * then link int1 to control and control to bulk 588 */ 589 uhci->skel_int128_qh->link = 590 uhci->skel_int64_qh->link = 591 uhci->skel_int32_qh->link = 592 uhci->skel_int16_qh->link = 593 uhci->skel_int8_qh->link = 594 uhci->skel_int4_qh->link = 595 uhci->skel_int2_qh->link = 596 cpu_to_le32(uhci->skel_int1_qh->dma_handle) | UHCI_PTR_QH; 597 uhci->skel_int1_qh->link = cpu_to_le32(uhci->skel_ls_control_qh->dma_handle) | UHCI_PTR_QH; 598 599 uhci->skel_ls_control_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH; 600 uhci->skel_fs_control_qh->link = cpu_to_le32(uhci->skel_bulk_qh->dma_handle) | UHCI_PTR_QH; 601 uhci->skel_bulk_qh->link = cpu_to_le32(uhci->skel_term_qh->dma_handle) | UHCI_PTR_QH; 602 603 /* This dummy TD is to work around a bug in Intel PIIX controllers */ 604 uhci_fill_td(uhci->term_td, 0, (UHCI_NULL_DATA_SIZE << 21) | 605 (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); 606 uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle); 607 608 uhci->skel_term_qh->link = UHCI_PTR_TERM; 609 uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle); 610 611 /* 612 * Fill the frame list: make all entries point to the proper 613 * interrupt queue. 614 * 615 * The interrupt queues will be interleaved as evenly as possible. 616 * There's not much to be done about period-1 interrupts; they have 617 * to occur in every frame. But we can schedule period-2 interrupts 618 * in odd-numbered frames, period-4 interrupts in frames congruent 619 * to 2 (mod 4), and so on. This way each frame only has two 620 * interrupt QHs, which will help spread out bandwidth utilization. 621 */ 622 for (i = 0; i < UHCI_NUMFRAMES; i++) { 623 int irq; 624 625 /* 626 * ffs (Find First bit Set) does exactly what we need: 627 * 1,3,5,... => ffs = 0 => use skel_int2_qh = skelqh[6], 628 * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[5], etc. 629 * ffs > 6 => not on any high-period queue, so use 630 * skel_int1_qh = skelqh[7]. 631 * Add UHCI_NUMFRAMES to insure at least one bit is set. 632 */ 633 irq = 6 - (int) __ffs(i + UHCI_NUMFRAMES); 634 if (irq < 0) 635 irq = 7; 636 637 /* Only place we don't use the frame list routines */ 638 uhci->fl->frame[i] = UHCI_PTR_QH | 639 cpu_to_le32(uhci->skelqh[irq]->dma_handle); 640 } 641 642 /* 643 * Some architectures require a full mb() to enforce completion of 644 * the memory writes above before the I/O transfers in start_hc(). 645 */ 646 mb(); 647 if ((retval = start_hc(uhci)) != 0) 648 goto err_alloc_skelqh; 649 650 init_stall_timer(hcd); 651 652 udev->speed = USB_SPEED_FULL; 653 654 if (usb_hcd_register_root_hub(udev, hcd) != 0) { 655 dev_err(uhci_dev(uhci), "unable to start root hub\n"); 656 retval = -ENOMEM; 657 goto err_start_root_hub; 658 } 659 660 return 0; 661 662 /* 663 * error exits: 664 */ 665 err_start_root_hub: 666 reset_hc(uhci); 667 668 del_timer_sync(&uhci->stall_timer); 669 670 err_alloc_skelqh: 671 for (i = 0; i < UHCI_NUM_SKELQH; i++) 672 if (uhci->skelqh[i]) { 673 uhci_free_qh(uhci, uhci->skelqh[i]); 674 uhci->skelqh[i] = NULL; 675 } 676 677 uhci_free_td(uhci, uhci->term_td); 678 uhci->term_td = NULL; 679 680 err_alloc_term_td: 681 usb_put_dev(udev); 682 683 err_alloc_root_hub: 684 dma_pool_destroy(uhci->qh_pool); 685 uhci->qh_pool = NULL; 686 687 err_create_qh_pool: 688 dma_pool_destroy(uhci->td_pool); 689 uhci->td_pool = NULL; 690 691 err_create_td_pool: 692 dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl), 693 uhci->fl, uhci->fl->dma_handle); 694 uhci->fl = NULL; 695 696 err_alloc_fl: 697 debugfs_remove(uhci->dentry); 698 uhci->dentry = NULL; 699 700 err_create_debug_entry: 701 return retval; 702 } 703 704 static void uhci_stop(struct usb_hcd *hcd) 705 { 706 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 707 708 del_timer_sync(&uhci->stall_timer); 709 reset_hc(uhci); 710 711 spin_lock_irq(&uhci->lock); 712 uhci_scan_schedule(uhci, NULL); 713 spin_unlock_irq(&uhci->lock); 714 715 release_uhci(uhci); 716 } 717 718 #ifdef CONFIG_PM 719 static int uhci_suspend(struct usb_hcd *hcd, u32 state) 720 { 721 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 722 723 spin_lock_irq(&uhci->lock); 724 725 /* Don't try to suspend broken motherboards, reset instead */ 726 if (suspend_allowed(uhci)) 727 suspend_hc(uhci); 728 else { 729 spin_unlock_irq(&uhci->lock); 730 reset_hc(uhci); 731 spin_lock_irq(&uhci->lock); 732 uhci_scan_schedule(uhci, NULL); 733 } 734 735 spin_unlock_irq(&uhci->lock); 736 return 0; 737 } 738 739 static int uhci_resume(struct usb_hcd *hcd) 740 { 741 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 742 int rc; 743 744 pci_set_master(to_pci_dev(uhci_dev(uhci))); 745 746 spin_lock_irq(&uhci->lock); 747 748 if (uhci->state == UHCI_SUSPENDED) { 749 750 /* 751 * Some systems don't maintain the UHCI register values 752 * during a PM suspend/resume cycle, so reinitialize 753 * the Frame Number, Framelist Base Address, Interrupt 754 * Enable, and Legacy Support registers. 755 */ 756 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 757 0); 758 outw(uhci->frame_number, uhci->io_addr + USBFRNUM); 759 outl(uhci->fl->dma_handle, uhci->io_addr + USBFLBASEADD); 760 outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | 761 USBINTR_SP, uhci->io_addr + USBINTR); 762 uhci->resume_detect = 1; 763 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 764 USBLEGSUP_DEFAULT); 765 } else { 766 spin_unlock_irq(&uhci->lock); 767 reset_hc(uhci); 768 if ((rc = start_hc(uhci)) != 0) 769 return rc; 770 spin_lock_irq(&uhci->lock); 771 } 772 hcd->state = HC_STATE_RUNNING; 773 774 spin_unlock_irq(&uhci->lock); 775 return 0; 776 } 777 #endif 778 779 /* Wait until all the URBs for a particular device/endpoint are gone */ 780 static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, 781 struct usb_host_endpoint *ep) 782 { 783 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 784 785 wait_event_interruptible(uhci->waitqh, list_empty(&ep->urb_list)); 786 } 787 788 static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) 789 { 790 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 791 int frame_number; 792 unsigned long flags; 793 794 /* Minimize latency by avoiding the spinlock */ 795 local_irq_save(flags); 796 rmb(); 797 frame_number = (uhci->is_stopped ? uhci->frame_number : 798 inw(uhci->io_addr + USBFRNUM)); 799 local_irq_restore(flags); 800 return frame_number; 801 } 802 803 static const char hcd_name[] = "uhci_hcd"; 804 805 static const struct hc_driver uhci_driver = { 806 .description = hcd_name, 807 .product_desc = "UHCI Host Controller", 808 .hcd_priv_size = sizeof(struct uhci_hcd), 809 810 /* Generic hardware linkage */ 811 .irq = uhci_irq, 812 .flags = HCD_USB11, 813 814 /* Basic lifecycle operations */ 815 .reset = uhci_reset, 816 .start = uhci_start, 817 #ifdef CONFIG_PM 818 .suspend = uhci_suspend, 819 .resume = uhci_resume, 820 #endif 821 .stop = uhci_stop, 822 823 .urb_enqueue = uhci_urb_enqueue, 824 .urb_dequeue = uhci_urb_dequeue, 825 826 .endpoint_disable = uhci_hcd_endpoint_disable, 827 .get_frame_number = uhci_hcd_get_frame_number, 828 829 .hub_status_data = uhci_hub_status_data, 830 .hub_control = uhci_hub_control, 831 }; 832 833 static const struct pci_device_id uhci_pci_ids[] = { { 834 /* handle any USB UHCI controller */ 835 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x00), ~0), 836 .driver_data = (unsigned long) &uhci_driver, 837 }, { /* end: all zeroes */ } 838 }; 839 840 MODULE_DEVICE_TABLE(pci, uhci_pci_ids); 841 842 static struct pci_driver uhci_pci_driver = { 843 .name = (char *)hcd_name, 844 .id_table = uhci_pci_ids, 845 846 .probe = usb_hcd_pci_probe, 847 .remove = usb_hcd_pci_remove, 848 849 #ifdef CONFIG_PM 850 .suspend = usb_hcd_pci_suspend, 851 .resume = usb_hcd_pci_resume, 852 #endif /* PM */ 853 }; 854 855 static int __init uhci_hcd_init(void) 856 { 857 int retval = -ENOMEM; 858 859 printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "\n"); 860 861 if (usb_disabled()) 862 return -ENODEV; 863 864 if (debug) { 865 errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); 866 if (!errbuf) 867 goto errbuf_failed; 868 } 869 870 uhci_debugfs_root = debugfs_create_dir("uhci", NULL); 871 if (!uhci_debugfs_root) 872 goto debug_failed; 873 874 uhci_up_cachep = kmem_cache_create("uhci_urb_priv", 875 sizeof(struct urb_priv), 0, 0, NULL, NULL); 876 if (!uhci_up_cachep) 877 goto up_failed; 878 879 retval = pci_register_driver(&uhci_pci_driver); 880 if (retval) 881 goto init_failed; 882 883 return 0; 884 885 init_failed: 886 if (kmem_cache_destroy(uhci_up_cachep)) 887 warn("not all urb_priv's were freed!"); 888 889 up_failed: 890 debugfs_remove(uhci_debugfs_root); 891 892 debug_failed: 893 if (errbuf) 894 kfree(errbuf); 895 896 errbuf_failed: 897 898 return retval; 899 } 900 901 static void __exit uhci_hcd_cleanup(void) 902 { 903 pci_unregister_driver(&uhci_pci_driver); 904 905 if (kmem_cache_destroy(uhci_up_cachep)) 906 warn("not all urb_priv's were freed!"); 907 908 debugfs_remove(uhci_debugfs_root); 909 910 if (errbuf) 911 kfree(errbuf); 912 } 913 914 module_init(uhci_hcd_init); 915 module_exit(uhci_hcd_cleanup); 916 917 MODULE_AUTHOR(DRIVER_AUTHOR); 918 MODULE_DESCRIPTION(DRIVER_DESC); 919 MODULE_LICENSE("GPL"); 920