1 /* 2 * This file contains code to reset and initialize USB host controllers. 3 * Some of it includes work-arounds for PCI hardware and BIOS quirks. 4 * It may need to run early during booting -- before USB would normally 5 * initialize -- to ensure that Linux doesn't use any legacy modes. 6 * 7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 8 * (and others) 9 */ 10 11 #include <linux/types.h> 12 #include <linux/kernel.h> 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/acpi.h> 17 #include "pci-quirks.h" 18 19 20 #define UHCI_USBLEGSUP 0xc0 /* legacy support */ 21 #define UHCI_USBCMD 0 /* command register */ 22 #define UHCI_USBINTR 4 /* interrupt register */ 23 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ 24 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ 25 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ 26 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ 27 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 28 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ 29 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 30 31 #define OHCI_CONTROL 0x04 32 #define OHCI_CMDSTATUS 0x08 33 #define OHCI_INTRSTATUS 0x0c 34 #define OHCI_INTRENABLE 0x10 35 #define OHCI_INTRDISABLE 0x14 36 #define OHCI_OCR (1 << 3) /* ownership change request */ 37 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 38 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 39 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 40 41 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ 42 #define EHCI_USBCMD 0 /* command register */ 43 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 44 #define EHCI_USBSTS 4 /* status register */ 45 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ 46 #define EHCI_USBINTR 8 /* interrupt register */ 47 #define EHCI_CONFIGFLAG 0x40 /* configured flag register */ 48 #define EHCI_USBLEGSUP 0 /* legacy support register */ 49 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ 50 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ 51 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 52 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 53 54 55 /* 56 * Make sure the controller is completely inactive, unable to 57 * generate interrupts or do DMA. 58 */ 59 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) 60 { 61 /* Turn off PIRQ enable and SMI enable. (This also turns off the 62 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. 63 */ 64 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); 65 66 /* Reset the HC - this will force us to get a 67 * new notification of any already connected 68 * ports due to the virtual disconnect that it 69 * implies. 70 */ 71 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); 72 mb(); 73 udelay(5); 74 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) 75 dev_warn(&pdev->dev, "HCRESET not completed yet!\n"); 76 77 /* Just to be safe, disable interrupt requests and 78 * make sure the controller is stopped. 79 */ 80 outw(0, base + UHCI_USBINTR); 81 outw(0, base + UHCI_USBCMD); 82 } 83 EXPORT_SYMBOL_GPL(uhci_reset_hc); 84 85 /* 86 * Initialize a controller that was newly discovered or has just been 87 * resumed. In either case we can't be sure of its previous state. 88 * 89 * Returns: 1 if the controller was reset, 0 otherwise. 90 */ 91 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) 92 { 93 u16 legsup; 94 unsigned int cmd, intr; 95 96 /* 97 * When restarting a suspended controller, we expect all the 98 * settings to be the same as we left them: 99 * 100 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; 101 * Controller is stopped and configured with EGSM set; 102 * No interrupts enabled except possibly Resume Detect. 103 * 104 * If any of these conditions are violated we do a complete reset. 105 */ 106 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup); 107 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { 108 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n", 109 __FUNCTION__, legsup); 110 goto reset_needed; 111 } 112 113 cmd = inw(base + UHCI_USBCMD); 114 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) || 115 !(cmd & UHCI_USBCMD_EGSM)) { 116 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n", 117 __FUNCTION__, cmd); 118 goto reset_needed; 119 } 120 121 intr = inw(base + UHCI_USBINTR); 122 if (intr & (~UHCI_USBINTR_RESUME)) { 123 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n", 124 __FUNCTION__, intr); 125 goto reset_needed; 126 } 127 return 0; 128 129 reset_needed: 130 dev_dbg(&pdev->dev, "Performing full reset\n"); 131 uhci_reset_hc(pdev, base); 132 return 1; 133 } 134 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); 135 136 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) 137 { 138 u16 cmd; 139 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask); 140 } 141 142 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO) 143 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY) 144 145 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev) 146 { 147 unsigned long base = 0; 148 int i; 149 150 if (!pio_enabled(pdev)) 151 return; 152 153 for (i = 0; i < PCI_ROM_RESOURCE; i++) 154 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { 155 base = pci_resource_start(pdev, i); 156 break; 157 } 158 159 if (base) 160 uhci_check_and_reset_hc(pdev, base); 161 } 162 163 static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx) 164 { 165 return pci_resource_start(pdev, idx) && mmio_enabled(pdev); 166 } 167 168 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) 169 { 170 void __iomem *base; 171 172 if (!mmio_resource_enabled(pdev, 0)) 173 return; 174 175 base = ioremap_nocache(pci_resource_start(pdev, 0), 176 pci_resource_len(pdev, 0)); 177 if (base == NULL) return; 178 179 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 180 #ifndef __hppa__ 181 { 182 u32 control = readl(base + OHCI_CONTROL); 183 if (control & OHCI_CTRL_IR) { 184 int wait_time = 500; /* arbitrary; 5 seconds */ 185 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); 186 writel(OHCI_OCR, base + OHCI_CMDSTATUS); 187 while (wait_time > 0 && 188 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 189 wait_time -= 10; 190 msleep(10); 191 } 192 if (wait_time <= 0) 193 printk(KERN_WARNING "%s %s: BIOS handoff " 194 "failed (BIOS bug ?) %08x\n", 195 pdev->dev.bus_id, "OHCI", 196 readl(base + OHCI_CONTROL)); 197 198 /* reset controller, preserving RWC */ 199 writel(control & OHCI_CTRL_RWC, base + OHCI_CONTROL); 200 } 201 } 202 #endif 203 204 /* 205 * disable interrupts 206 */ 207 writel(~(u32)0, base + OHCI_INTRDISABLE); 208 writel(~(u32)0, base + OHCI_INTRSTATUS); 209 210 iounmap(base); 211 } 212 213 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev) 214 { 215 int wait_time, delta; 216 void __iomem *base, *op_reg_base; 217 u32 hcc_params, val; 218 u8 offset, cap_length; 219 int count = 256/4; 220 int tried_handoff = 0; 221 222 if (!mmio_resource_enabled(pdev, 0)) 223 return; 224 225 base = ioremap_nocache(pci_resource_start(pdev, 0), 226 pci_resource_len(pdev, 0)); 227 if (base == NULL) return; 228 229 cap_length = readb(base); 230 op_reg_base = base + cap_length; 231 232 /* EHCI 0.96 and later may have "extended capabilities" 233 * spec section 5.1 explains the bios handoff, e.g. for 234 * booting from USB disk or using a usb keyboard 235 */ 236 hcc_params = readl(base + EHCI_HCC_PARAMS); 237 offset = (hcc_params >> 8) & 0xff; 238 while (offset && count--) { 239 u32 cap; 240 int msec; 241 242 pci_read_config_dword(pdev, offset, &cap); 243 switch (cap & 0xff) { 244 case 1: /* BIOS/SMM/... handoff support */ 245 if ((cap & EHCI_USBLEGSUP_BIOS)) { 246 pr_debug("%s %s: BIOS handoff\n", 247 pdev->dev.bus_id, "EHCI"); 248 249 #if 0 250 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on, 251 * but that seems dubious in general (the BIOS left it off intentionally) 252 * and is known to prevent some systems from booting. so we won't do this 253 * unless maybe we can determine when we're on a system that needs SMI forced. 254 */ 255 /* BIOS workaround (?): be sure the 256 * pre-Linux code receives the SMI 257 */ 258 pci_read_config_dword(pdev, 259 offset + EHCI_USBLEGCTLSTS, 260 &val); 261 pci_write_config_dword(pdev, 262 offset + EHCI_USBLEGCTLSTS, 263 val | EHCI_USBLEGCTLSTS_SOOE); 264 #endif 265 266 /* some systems get upset if this semaphore is 267 * set for any other reason than forcing a BIOS 268 * handoff.. 269 */ 270 pci_write_config_byte(pdev, offset + 3, 1); 271 } 272 273 /* if boot firmware now owns EHCI, spin till 274 * it hands it over. 275 */ 276 msec = 5000; 277 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) { 278 tried_handoff = 1; 279 msleep(10); 280 msec -= 10; 281 pci_read_config_dword(pdev, offset, &cap); 282 } 283 284 if (cap & EHCI_USBLEGSUP_BIOS) { 285 /* well, possibly buggy BIOS... try to shut 286 * it down, and hope nothing goes too wrong 287 */ 288 printk(KERN_WARNING "%s %s: BIOS handoff " 289 "failed (BIOS bug ?) %08x\n", 290 pdev->dev.bus_id, "EHCI", cap); 291 pci_write_config_byte(pdev, offset + 2, 0); 292 } 293 294 /* just in case, always disable EHCI SMIs */ 295 pci_write_config_dword(pdev, 296 offset + EHCI_USBLEGCTLSTS, 297 0); 298 299 /* If the BIOS ever owned the controller then we 300 * can't expect any power sessions to remain intact. 301 */ 302 if (tried_handoff) 303 writel(0, op_reg_base + EHCI_CONFIGFLAG); 304 break; 305 case 0: /* illegal reserved capability */ 306 cap = 0; 307 /* FALLTHROUGH */ 308 default: 309 printk(KERN_WARNING "%s %s: unrecognized " 310 "capability %02x\n", 311 pdev->dev.bus_id, "EHCI", 312 cap & 0xff); 313 break; 314 } 315 offset = (cap >> 8) & 0xff; 316 } 317 if (!count) 318 printk(KERN_DEBUG "%s %s: capability loop?\n", 319 pdev->dev.bus_id, "EHCI"); 320 321 /* 322 * halt EHCI & disable its interrupts in any case 323 */ 324 val = readl(op_reg_base + EHCI_USBSTS); 325 if ((val & EHCI_USBSTS_HALTED) == 0) { 326 val = readl(op_reg_base + EHCI_USBCMD); 327 val &= ~EHCI_USBCMD_RUN; 328 writel(val, op_reg_base + EHCI_USBCMD); 329 330 wait_time = 2000; 331 delta = 100; 332 do { 333 writel(0x3f, op_reg_base + EHCI_USBSTS); 334 udelay(delta); 335 wait_time -= delta; 336 val = readl(op_reg_base + EHCI_USBSTS); 337 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { 338 break; 339 } 340 } while (wait_time > 0); 341 } 342 writel(0, op_reg_base + EHCI_USBINTR); 343 writel(0x3f, op_reg_base + EHCI_USBSTS); 344 345 iounmap(base); 346 347 return; 348 } 349 350 351 352 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev) 353 { 354 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI) 355 quirk_usb_handoff_uhci(pdev); 356 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI) 357 quirk_usb_handoff_ohci(pdev); 358 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI) 359 quirk_usb_disable_ehci(pdev); 360 } 361 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff); 362