1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* statistics can be kept for for tuning/monitoring */ 25 struct ehci_stats { 26 /* irq usage */ 27 unsigned long normal; 28 unsigned long error; 29 unsigned long reclaim; 30 unsigned long lost_iaa; 31 32 /* termination of urbs from core */ 33 unsigned long complete; 34 unsigned long unlink; 35 }; 36 37 /* ehci_hcd->lock guards shared data against other CPUs: 38 * ehci_hcd: async, reclaim, periodic (and shadow), ... 39 * usb_host_endpoint: hcpriv 40 * ehci_qh: qh_next, qtd_list 41 * ehci_qtd: qtd_list 42 * 43 * Also, hold this lock when talking to HC registers or 44 * when updating hw_* fields in shared qh/qtd/... structures. 45 */ 46 47 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 48 49 struct ehci_hcd { /* one per controller */ 50 spinlock_t lock; 51 52 /* async schedule support */ 53 struct ehci_qh *async; 54 struct ehci_qh *reclaim; 55 unsigned reclaim_ready : 1; 56 unsigned scanning : 1; 57 58 /* periodic schedule support */ 59 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 60 unsigned periodic_size; 61 __le32 *periodic; /* hw periodic table */ 62 dma_addr_t periodic_dma; 63 unsigned i_thresh; /* uframes HC might cache */ 64 65 union ehci_shadow *pshadow; /* mirror hw periodic table */ 66 int next_uframe; /* scan periodic, start here */ 67 unsigned periodic_sched; /* periodic activity count */ 68 69 /* per root hub port */ 70 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 71 72 /* per-HC memory pools (could be per-bus, but ...) */ 73 struct dma_pool *qh_pool; /* qh per active urb */ 74 struct dma_pool *qtd_pool; /* one or more per qh */ 75 struct dma_pool *itd_pool; /* itd per iso urb */ 76 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 77 78 struct timer_list watchdog; 79 struct notifier_block reboot_notifier; 80 unsigned long actions; 81 unsigned stamp; 82 unsigned long next_statechange; 83 u32 command; 84 85 unsigned is_tdi_rh_tt:1; /* TDI roothub with TT */ 86 87 /* glue to PCI and HCD framework */ 88 struct ehci_caps __iomem *caps; 89 struct ehci_regs __iomem *regs; 90 __u32 hcs_params; /* cached register copy */ 91 92 /* irq statistics */ 93 #ifdef EHCI_STATS 94 struct ehci_stats stats; 95 # define COUNT(x) do { (x)++; } while (0) 96 #else 97 # define COUNT(x) do {} while (0) 98 #endif 99 }; 100 101 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 102 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 103 { 104 return (struct ehci_hcd *) (hcd->hcd_priv); 105 } 106 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 107 { 108 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 109 } 110 111 112 enum ehci_timer_action { 113 TIMER_IO_WATCHDOG, 114 TIMER_IAA_WATCHDOG, 115 TIMER_ASYNC_SHRINK, 116 TIMER_ASYNC_OFF, 117 }; 118 119 static inline void 120 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 121 { 122 clear_bit (action, &ehci->actions); 123 } 124 125 static inline void 126 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action) 127 { 128 if (!test_and_set_bit (action, &ehci->actions)) { 129 unsigned long t; 130 131 switch (action) { 132 case TIMER_IAA_WATCHDOG: 133 t = EHCI_IAA_JIFFIES; 134 break; 135 case TIMER_IO_WATCHDOG: 136 t = EHCI_IO_JIFFIES; 137 break; 138 case TIMER_ASYNC_OFF: 139 t = EHCI_ASYNC_JIFFIES; 140 break; 141 // case TIMER_ASYNC_SHRINK: 142 default: 143 t = EHCI_SHRINK_JIFFIES; 144 break; 145 } 146 t += jiffies; 147 // all timings except IAA watchdog can be overridden. 148 // async queue SHRINK often precedes IAA. while it's ready 149 // to go OFF neither can matter, and afterwards the IO 150 // watchdog stops unless there's still periodic traffic. 151 if (action != TIMER_IAA_WATCHDOG 152 && t > ehci->watchdog.expires 153 && timer_pending (&ehci->watchdog)) 154 return; 155 mod_timer (&ehci->watchdog, t); 156 } 157 } 158 159 /*-------------------------------------------------------------------------*/ 160 161 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ 162 163 /* Section 2.2 Host Controller Capability Registers */ 164 struct ehci_caps { 165 /* these fields are specified as 8 and 16 bit registers, 166 * but some hosts can't perform 8 or 16 bit PCI accesses. 167 */ 168 u32 hc_capbase; 169 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ 170 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ 171 u32 hcs_params; /* HCSPARAMS - offset 0x4 */ 172 #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ 173 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ 174 #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ 175 #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ 176 #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ 177 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 178 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ 179 180 u32 hcc_params; /* HCCPARAMS - offset 0x8 */ 181 #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ 182 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ 183 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ 184 #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ 185 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ 186 #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ 187 u8 portroute [8]; /* nibbles for routing - offset 0xC */ 188 } __attribute__ ((packed)); 189 190 191 /* Section 2.3 Host Controller Operational Registers */ 192 struct ehci_regs { 193 194 /* USBCMD: offset 0x00 */ 195 u32 command; 196 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ 197 #define CMD_PARK (1<<11) /* enable "park" on async qh */ 198 #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ 199 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ 200 #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ 201 #define CMD_ASE (1<<5) /* async schedule enable */ 202 #define CMD_PSE (1<<4) /* periodic schedule enable */ 203 /* 3:2 is periodic frame list size */ 204 #define CMD_RESET (1<<1) /* reset HC not bus */ 205 #define CMD_RUN (1<<0) /* start/stop HC */ 206 207 /* USBSTS: offset 0x04 */ 208 u32 status; 209 #define STS_ASS (1<<15) /* Async Schedule Status */ 210 #define STS_PSS (1<<14) /* Periodic Schedule Status */ 211 #define STS_RECL (1<<13) /* Reclamation */ 212 #define STS_HALT (1<<12) /* Not running (any reason) */ 213 /* some bits reserved */ 214 /* these STS_* flags are also intr_enable bits (USBINTR) */ 215 #define STS_IAA (1<<5) /* Interrupted on async advance */ 216 #define STS_FATAL (1<<4) /* such as some PCI access errors */ 217 #define STS_FLR (1<<3) /* frame list rolled over */ 218 #define STS_PCD (1<<2) /* port change detect */ 219 #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ 220 #define STS_INT (1<<0) /* "normal" completion (short, ...) */ 221 222 /* USBINTR: offset 0x08 */ 223 u32 intr_enable; 224 225 /* FRINDEX: offset 0x0C */ 226 u32 frame_index; /* current microframe number */ 227 /* CTRLDSSEGMENT: offset 0x10 */ 228 u32 segment; /* address bits 63:32 if needed */ 229 /* PERIODICLISTBASE: offset 0x14 */ 230 u32 frame_list; /* points to periodic list */ 231 /* ASYNCLISTADDR: offset 0x18 */ 232 u32 async_next; /* address of next async queue head */ 233 234 u32 reserved [9]; 235 236 /* CONFIGFLAG: offset 0x40 */ 237 u32 configured_flag; 238 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ 239 240 /* PORTSC: offset 0x44 */ 241 u32 port_status [0]; /* up to N_PORTS */ 242 /* 31:23 reserved */ 243 #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ 244 #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ 245 #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ 246 /* 19:16 for port testing */ 247 #define PORT_LED_OFF (0<<14) 248 #define PORT_LED_AMBER (1<<14) 249 #define PORT_LED_GREEN (2<<14) 250 #define PORT_LED_MASK (3<<14) 251 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ 252 #define PORT_POWER (1<<12) /* true: has power (see PPC) */ 253 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */ 254 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */ 255 /* 9 reserved */ 256 #define PORT_RESET (1<<8) /* reset port */ 257 #define PORT_SUSPEND (1<<7) /* suspend port */ 258 #define PORT_RESUME (1<<6) /* resume it */ 259 #define PORT_OCC (1<<5) /* over current change */ 260 #define PORT_OC (1<<4) /* over current active */ 261 #define PORT_PEC (1<<3) /* port enable change */ 262 #define PORT_PE (1<<2) /* port enable */ 263 #define PORT_CSC (1<<1) /* connect status change */ 264 #define PORT_CONNECT (1<<0) /* device connected */ 265 } __attribute__ ((packed)); 266 267 /* Appendix C, Debug port ... intended for use with special "debug devices" 268 * that can help if there's no serial console. (nonstandard enumeration.) 269 */ 270 struct ehci_dbg_port { 271 u32 control; 272 #define DBGP_OWNER (1<<30) 273 #define DBGP_ENABLED (1<<28) 274 #define DBGP_DONE (1<<16) 275 #define DBGP_INUSE (1<<10) 276 #define DBGP_ERRCODE(x) (((x)>>7)&0x0f) 277 # define DBGP_ERR_BAD 1 278 # define DBGP_ERR_SIGNAL 2 279 #define DBGP_ERROR (1<<6) 280 #define DBGP_GO (1<<5) 281 #define DBGP_OUT (1<<4) 282 #define DBGP_LEN(x) (((x)>>0)&0x0f) 283 u32 pids; 284 #define DBGP_PID_GET(x) (((x)>>16)&0xff) 285 #define DBGP_PID_SET(data,tok) (((data)<<8)|(tok)); 286 u32 data03; 287 u32 data47; 288 u32 address; 289 #define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep)); 290 } __attribute__ ((packed)); 291 292 /*-------------------------------------------------------------------------*/ 293 294 #define QTD_NEXT(dma) cpu_to_le32((u32)dma) 295 296 /* 297 * EHCI Specification 0.95 Section 3.5 298 * QTD: describe data transfer components (buffer, direction, ...) 299 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 300 * 301 * These are associated only with "QH" (Queue Head) structures, 302 * used with control, bulk, and interrupt transfers. 303 */ 304 struct ehci_qtd { 305 /* first part defined by EHCI spec */ 306 __le32 hw_next; /* see EHCI 3.5.1 */ 307 __le32 hw_alt_next; /* see EHCI 3.5.2 */ 308 __le32 hw_token; /* see EHCI 3.5.3 */ 309 #define QTD_TOGGLE (1 << 31) /* data toggle */ 310 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 311 #define QTD_IOC (1 << 15) /* interrupt on complete */ 312 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 313 #define QTD_PID(tok) (((tok)>>8) & 0x3) 314 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 315 #define QTD_STS_HALT (1 << 6) /* halted on error */ 316 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 317 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 318 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 319 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 320 #define QTD_STS_STS (1 << 1) /* split transaction state */ 321 #define QTD_STS_PING (1 << 0) /* issue PING? */ 322 __le32 hw_buf [5]; /* see EHCI 3.5.4 */ 323 __le32 hw_buf_hi [5]; /* Appendix B */ 324 325 /* the rest is HCD-private */ 326 dma_addr_t qtd_dma; /* qtd address */ 327 struct list_head qtd_list; /* sw qtd list */ 328 struct urb *urb; /* qtd's urb */ 329 size_t length; /* length of buffer */ 330 } __attribute__ ((aligned (32))); 331 332 /* mask NakCnt+T in qh->hw_alt_next */ 333 #define QTD_MASK __constant_cpu_to_le32 (~0x1f) 334 335 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 336 337 /*-------------------------------------------------------------------------*/ 338 339 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 340 #define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1)) 341 342 /* values for that type tag */ 343 #define Q_TYPE_ITD __constant_cpu_to_le32 (0 << 1) 344 #define Q_TYPE_QH __constant_cpu_to_le32 (1 << 1) 345 #define Q_TYPE_SITD __constant_cpu_to_le32 (2 << 1) 346 #define Q_TYPE_FSTN __constant_cpu_to_le32 (3 << 1) 347 348 /* next async queue entry, or pointer to interrupt/periodic QH */ 349 #define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH) 350 351 /* for periodic/async schedules and qtd lists, mark end of list */ 352 #define EHCI_LIST_END __constant_cpu_to_le32(1) /* "null pointer" to hw */ 353 354 /* 355 * Entries in periodic shadow table are pointers to one of four kinds 356 * of data structure. That's dictated by the hardware; a type tag is 357 * encoded in the low bits of the hardware's periodic schedule. Use 358 * Q_NEXT_TYPE to get the tag. 359 * 360 * For entries in the async schedule, the type tag always says "qh". 361 */ 362 union ehci_shadow { 363 struct ehci_qh *qh; /* Q_TYPE_QH */ 364 struct ehci_itd *itd; /* Q_TYPE_ITD */ 365 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 366 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 367 u32 *hw_next; /* (all types) */ 368 void *ptr; 369 }; 370 371 /*-------------------------------------------------------------------------*/ 372 373 /* 374 * EHCI Specification 0.95 Section 3.6 375 * QH: describes control/bulk/interrupt endpoints 376 * See Fig 3-7 "Queue Head Structure Layout". 377 * 378 * These appear in both the async and (for interrupt) periodic schedules. 379 */ 380 381 struct ehci_qh { 382 /* first part defined by EHCI spec */ 383 __le32 hw_next; /* see EHCI 3.6.1 */ 384 __le32 hw_info1; /* see EHCI 3.6.2 */ 385 #define QH_HEAD 0x00008000 386 __le32 hw_info2; /* see EHCI 3.6.2 */ 387 __le32 hw_current; /* qtd list - see EHCI 3.6.4 */ 388 389 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 390 __le32 hw_qtd_next; 391 __le32 hw_alt_next; 392 __le32 hw_token; 393 __le32 hw_buf [5]; 394 __le32 hw_buf_hi [5]; 395 396 /* the rest is HCD-private */ 397 dma_addr_t qh_dma; /* address of qh */ 398 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 399 struct list_head qtd_list; /* sw qtd list */ 400 struct ehci_qtd *dummy; 401 struct ehci_qh *reclaim; /* next to reclaim */ 402 403 struct ehci_hcd *ehci; 404 struct kref kref; 405 unsigned stamp; 406 407 u8 qh_state; 408 #define QH_STATE_LINKED 1 /* HC sees this */ 409 #define QH_STATE_UNLINK 2 /* HC may still see this */ 410 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 411 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 412 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 413 414 /* periodic schedule info */ 415 u8 usecs; /* intr bandwidth */ 416 u8 gap_uf; /* uframes split/csplit gap */ 417 u8 c_usecs; /* ... split completion bw */ 418 unsigned short period; /* polling interval */ 419 unsigned short start; /* where polling starts */ 420 #define NO_FRAME ((unsigned short)~0) /* pick new start */ 421 struct usb_device *dev; /* access to TT */ 422 } __attribute__ ((aligned (32))); 423 424 /*-------------------------------------------------------------------------*/ 425 426 /* description of one iso transaction (up to 3 KB data if highspeed) */ 427 struct ehci_iso_packet { 428 /* These will be copied to iTD when scheduling */ 429 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 430 __le32 transaction; /* itd->hw_transaction[i] |= */ 431 u8 cross; /* buf crosses pages */ 432 /* for full speed OUT splits */ 433 u32 buf1; 434 }; 435 436 /* temporary schedule data for packets from iso urbs (both speeds) 437 * each packet is one logical usb transaction to the device (not TT), 438 * beginning at stream->next_uframe 439 */ 440 struct ehci_iso_sched { 441 struct list_head td_list; 442 unsigned span; 443 struct ehci_iso_packet packet [0]; 444 }; 445 446 /* 447 * ehci_iso_stream - groups all (s)itds for this endpoint. 448 * acts like a qh would, if EHCI had them for ISO. 449 */ 450 struct ehci_iso_stream { 451 /* first two fields match QH, but info1 == 0 */ 452 __le32 hw_next; 453 __le32 hw_info1; 454 455 u32 refcount; 456 u8 bEndpointAddress; 457 u8 highspeed; 458 u16 depth; /* depth in uframes */ 459 struct list_head td_list; /* queued itds/sitds */ 460 struct list_head free_list; /* list of unused itds/sitds */ 461 struct usb_device *udev; 462 struct usb_host_endpoint *ep; 463 464 /* output of (re)scheduling */ 465 unsigned long start; /* jiffies */ 466 unsigned long rescheduled; 467 int next_uframe; 468 __le32 splits; 469 470 /* the rest is derived from the endpoint descriptor, 471 * trusting urb->interval == f(epdesc->bInterval) and 472 * including the extra info for hw_bufp[0..2] 473 */ 474 u8 interval; 475 u8 usecs, c_usecs; 476 u16 maxp; 477 u16 raw_mask; 478 unsigned bandwidth; 479 480 /* This is used to initialize iTD's hw_bufp fields */ 481 __le32 buf0; 482 __le32 buf1; 483 __le32 buf2; 484 485 /* this is used to initialize sITD's tt info */ 486 __le32 address; 487 }; 488 489 /*-------------------------------------------------------------------------*/ 490 491 /* 492 * EHCI Specification 0.95 Section 3.3 493 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 494 * 495 * Schedule records for high speed iso xfers 496 */ 497 struct ehci_itd { 498 /* first part defined by EHCI spec */ 499 __le32 hw_next; /* see EHCI 3.3.1 */ 500 __le32 hw_transaction [8]; /* see EHCI 3.3.2 */ 501 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 502 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 503 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 504 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 505 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 506 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 507 508 #define ITD_ACTIVE __constant_cpu_to_le32(EHCI_ISOC_ACTIVE) 509 510 __le32 hw_bufp [7]; /* see EHCI 3.3.3 */ 511 __le32 hw_bufp_hi [7]; /* Appendix B */ 512 513 /* the rest is HCD-private */ 514 dma_addr_t itd_dma; /* for this itd */ 515 union ehci_shadow itd_next; /* ptr to periodic q entry */ 516 517 struct urb *urb; 518 struct ehci_iso_stream *stream; /* endpoint's queue */ 519 struct list_head itd_list; /* list of stream's itds */ 520 521 /* any/all hw_transactions here may be used by that urb */ 522 unsigned frame; /* where scheduled */ 523 unsigned pg; 524 unsigned index[8]; /* in urb->iso_frame_desc */ 525 u8 usecs[8]; 526 } __attribute__ ((aligned (32))); 527 528 /*-------------------------------------------------------------------------*/ 529 530 /* 531 * EHCI Specification 0.95 Section 3.4 532 * siTD, aka split-transaction isochronous Transfer Descriptor 533 * ... describe full speed iso xfers through TT in hubs 534 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 535 */ 536 struct ehci_sitd { 537 /* first part defined by EHCI spec */ 538 __le32 hw_next; 539 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 540 __le32 hw_fullspeed_ep; /* EHCI table 3-9 */ 541 __le32 hw_uframe; /* EHCI table 3-10 */ 542 __le32 hw_results; /* EHCI table 3-11 */ 543 #define SITD_IOC (1 << 31) /* interrupt on completion */ 544 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 545 #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 546 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 547 #define SITD_STS_ERR (1 << 6) /* error from TT */ 548 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 549 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 550 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 551 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 552 #define SITD_STS_STS (1 << 1) /* split transaction state */ 553 554 #define SITD_ACTIVE __constant_cpu_to_le32(SITD_STS_ACTIVE) 555 556 __le32 hw_buf [2]; /* EHCI table 3-12 */ 557 __le32 hw_backpointer; /* EHCI table 3-13 */ 558 __le32 hw_buf_hi [2]; /* Appendix B */ 559 560 /* the rest is HCD-private */ 561 dma_addr_t sitd_dma; 562 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 563 564 struct urb *urb; 565 struct ehci_iso_stream *stream; /* endpoint's queue */ 566 struct list_head sitd_list; /* list of stream's sitds */ 567 unsigned frame; 568 unsigned index; 569 } __attribute__ ((aligned (32))); 570 571 /*-------------------------------------------------------------------------*/ 572 573 /* 574 * EHCI Specification 0.96 Section 3.7 575 * Periodic Frame Span Traversal Node (FSTN) 576 * 577 * Manages split interrupt transactions (using TT) that span frame boundaries 578 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 579 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 580 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 581 */ 582 struct ehci_fstn { 583 __le32 hw_next; /* any periodic q entry */ 584 __le32 hw_prev; /* qh or EHCI_LIST_END */ 585 586 /* the rest is HCD-private */ 587 dma_addr_t fstn_dma; 588 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 589 } __attribute__ ((aligned (32))); 590 591 /*-------------------------------------------------------------------------*/ 592 593 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 594 595 /* 596 * Some EHCI controllers have a Transaction Translator built into the 597 * root hub. This is a non-standard feature. Each controller will need 598 * to add code to the following inline functions, and call them as 599 * needed (mostly in root hub code). 600 */ 601 602 #define ehci_is_TDI(e) ((e)->is_tdi_rh_tt) 603 604 /* Returns the speed of a device attached to a port on the root hub. */ 605 static inline unsigned int 606 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 607 { 608 if (ehci_is_TDI(ehci)) { 609 switch ((portsc>>26)&3) { 610 case 0: 611 return 0; 612 case 1: 613 return (1<<USB_PORT_FEAT_LOWSPEED); 614 case 2: 615 default: 616 return (1<<USB_PORT_FEAT_HIGHSPEED); 617 } 618 } 619 return (1<<USB_PORT_FEAT_HIGHSPEED); 620 } 621 622 #else 623 624 #define ehci_is_TDI(e) (0) 625 626 #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED) 627 #endif 628 629 /*-------------------------------------------------------------------------*/ 630 631 #ifndef DEBUG 632 #define STUB_DEBUG_FILES 633 #endif /* DEBUG */ 634 635 /*-------------------------------------------------------------------------*/ 636 637 #endif /* __LINUX_EHCI_HCD_H */ 638