1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved. 3 * 4 * Inspired by dwc3-of-simple.c 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/io.h> 9 #include <linux/of.h> 10 #include <linux/clk.h> 11 #include <linux/irq.h> 12 #include <linux/of_clk.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/extcon.h> 16 #include <linux/interconnect.h> 17 #include <linux/of_platform.h> 18 #include <linux/platform_device.h> 19 #include <linux/phy/phy.h> 20 #include <linux/usb/of.h> 21 #include <linux/reset.h> 22 #include <linux/iopoll.h> 23 #include <linux/usb/hcd.h> 24 #include <linux/usb.h> 25 #include "core.h" 26 27 /* USB QSCRATCH Hardware registers */ 28 #define QSCRATCH_HS_PHY_CTRL 0x10 29 #define UTMI_OTG_VBUS_VALID BIT(20) 30 #define SW_SESSVLD_SEL BIT(28) 31 32 #define QSCRATCH_SS_PHY_CTRL 0x30 33 #define LANE0_PWR_PRESENT BIT(24) 34 35 #define QSCRATCH_GENERAL_CFG 0x08 36 #define PIPE_UTMI_CLK_SEL BIT(0) 37 #define PIPE3_PHYSTATUS_SW BIT(3) 38 #define PIPE_UTMI_CLK_DIS BIT(8) 39 40 #define PWR_EVNT_IRQ_STAT_REG 0x58 41 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) 42 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) 43 44 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800 45 #define SDM845_QSCRATCH_SIZE 0x400 46 #define SDM845_DWC3_CORE_SIZE 0xcd00 47 48 /* Interconnect path bandwidths in MBps */ 49 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240) 50 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700) 51 #define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000) 52 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500) 53 #define APPS_USB_AVG_BW 0 54 #define APPS_USB_PEAK_BW MBps_to_icc(40) 55 56 struct dwc3_acpi_pdata { 57 u32 qscratch_base_offset; 58 u32 qscratch_base_size; 59 u32 dwc3_core_base_size; 60 int hs_phy_irq_index; 61 int dp_hs_phy_irq_index; 62 int dm_hs_phy_irq_index; 63 int ss_phy_irq_index; 64 bool is_urs; 65 }; 66 67 struct dwc3_qcom { 68 struct device *dev; 69 void __iomem *qscratch_base; 70 struct platform_device *dwc3; 71 struct platform_device *urs_usb; 72 struct clk **clks; 73 int num_clocks; 74 struct reset_control *resets; 75 76 int hs_phy_irq; 77 int dp_hs_phy_irq; 78 int dm_hs_phy_irq; 79 int ss_phy_irq; 80 enum usb_device_speed usb2_speed; 81 82 struct extcon_dev *edev; 83 struct extcon_dev *host_edev; 84 struct notifier_block vbus_nb; 85 struct notifier_block host_nb; 86 87 const struct dwc3_acpi_pdata *acpi_pdata; 88 89 enum usb_dr_mode mode; 90 bool is_suspended; 91 bool pm_suspended; 92 struct icc_path *icc_path_ddr; 93 struct icc_path *icc_path_apps; 94 }; 95 96 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) 97 { 98 u32 reg; 99 100 reg = readl(base + offset); 101 reg |= val; 102 writel(reg, base + offset); 103 104 /* ensure that above write is through */ 105 readl(base + offset); 106 } 107 108 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val) 109 { 110 u32 reg; 111 112 reg = readl(base + offset); 113 reg &= ~val; 114 writel(reg, base + offset); 115 116 /* ensure that above write is through */ 117 readl(base + offset); 118 } 119 120 static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable) 121 { 122 if (enable) { 123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, 124 LANE0_PWR_PRESENT); 125 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, 126 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); 127 } else { 128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, 129 LANE0_PWR_PRESENT); 130 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, 131 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); 132 } 133 } 134 135 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb, 136 unsigned long event, void *ptr) 137 { 138 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb); 139 140 /* enable vbus override for device mode */ 141 dwc3_qcom_vbus_override_enable(qcom, event); 142 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST; 143 144 return NOTIFY_DONE; 145 } 146 147 static int dwc3_qcom_host_notifier(struct notifier_block *nb, 148 unsigned long event, void *ptr) 149 { 150 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb); 151 152 /* disable vbus override in host mode */ 153 dwc3_qcom_vbus_override_enable(qcom, !event); 154 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL; 155 156 return NOTIFY_DONE; 157 } 158 159 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom) 160 { 161 struct device *dev = qcom->dev; 162 struct extcon_dev *host_edev; 163 int ret; 164 165 if (!of_property_read_bool(dev->of_node, "extcon")) 166 return 0; 167 168 qcom->edev = extcon_get_edev_by_phandle(dev, 0); 169 if (IS_ERR(qcom->edev)) 170 return dev_err_probe(dev, PTR_ERR(qcom->edev), 171 "Failed to get extcon\n"); 172 173 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier; 174 175 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1); 176 if (IS_ERR(qcom->host_edev)) 177 qcom->host_edev = NULL; 178 179 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB, 180 &qcom->vbus_nb); 181 if (ret < 0) { 182 dev_err(dev, "VBUS notifier register failed\n"); 183 return ret; 184 } 185 186 if (qcom->host_edev) 187 host_edev = qcom->host_edev; 188 else 189 host_edev = qcom->edev; 190 191 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier; 192 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST, 193 &qcom->host_nb); 194 if (ret < 0) { 195 dev_err(dev, "Host notifier register failed\n"); 196 return ret; 197 } 198 199 /* Update initial VBUS override based on extcon state */ 200 if (extcon_get_state(qcom->edev, EXTCON_USB) || 201 !extcon_get_state(host_edev, EXTCON_USB_HOST)) 202 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev); 203 else 204 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev); 205 206 return 0; 207 } 208 209 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom) 210 { 211 int ret; 212 213 ret = icc_enable(qcom->icc_path_ddr); 214 if (ret) 215 return ret; 216 217 ret = icc_enable(qcom->icc_path_apps); 218 if (ret) 219 icc_disable(qcom->icc_path_ddr); 220 221 return ret; 222 } 223 224 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom) 225 { 226 int ret; 227 228 ret = icc_disable(qcom->icc_path_ddr); 229 if (ret) 230 return ret; 231 232 ret = icc_disable(qcom->icc_path_apps); 233 if (ret) 234 icc_enable(qcom->icc_path_ddr); 235 236 return ret; 237 } 238 239 /** 240 * dwc3_qcom_interconnect_init() - Get interconnect path handles 241 * and set bandwidth. 242 * @qcom: Pointer to the concerned usb core. 243 * 244 */ 245 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom) 246 { 247 enum usb_device_speed max_speed; 248 struct device *dev = qcom->dev; 249 int ret; 250 251 if (has_acpi_companion(dev)) 252 return 0; 253 254 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr"); 255 if (IS_ERR(qcom->icc_path_ddr)) { 256 return dev_err_probe(dev, PTR_ERR(qcom->icc_path_ddr), 257 "failed to get usb-ddr path\n"); 258 } 259 260 qcom->icc_path_apps = of_icc_get(dev, "apps-usb"); 261 if (IS_ERR(qcom->icc_path_apps)) { 262 ret = dev_err_probe(dev, PTR_ERR(qcom->icc_path_apps), 263 "failed to get apps-usb path\n"); 264 goto put_path_ddr; 265 } 266 267 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev); 268 if (max_speed >= USB_SPEED_SUPER || max_speed == USB_SPEED_UNKNOWN) { 269 ret = icc_set_bw(qcom->icc_path_ddr, 270 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW); 271 } else { 272 ret = icc_set_bw(qcom->icc_path_ddr, 273 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW); 274 } 275 if (ret) { 276 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret); 277 goto put_path_apps; 278 } 279 280 ret = icc_set_bw(qcom->icc_path_apps, APPS_USB_AVG_BW, APPS_USB_PEAK_BW); 281 if (ret) { 282 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret); 283 goto put_path_apps; 284 } 285 286 return 0; 287 288 put_path_apps: 289 icc_put(qcom->icc_path_apps); 290 put_path_ddr: 291 icc_put(qcom->icc_path_ddr); 292 return ret; 293 } 294 295 /** 296 * dwc3_qcom_interconnect_exit() - Release interconnect path handles 297 * @qcom: Pointer to the concerned usb core. 298 * 299 * This function is used to release interconnect path handle. 300 */ 301 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom) 302 { 303 icc_put(qcom->icc_path_ddr); 304 icc_put(qcom->icc_path_apps); 305 } 306 307 /* Only usable in contexts where the role can not change. */ 308 static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom) 309 { 310 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); 311 312 return dwc->xhci; 313 } 314 315 static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom) 316 { 317 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); 318 struct usb_device *udev; 319 struct usb_hcd __maybe_unused *hcd; 320 321 /* 322 * FIXME: Fix this layering violation. 323 */ 324 hcd = platform_get_drvdata(dwc->xhci); 325 326 /* 327 * It is possible to query the speed of all children of 328 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code 329 * currently supports only 1 port per controller. So 330 * this is sufficient. 331 */ 332 #ifdef CONFIG_USB 333 udev = usb_hub_find_child(hcd->self.root_hub, 1); 334 #else 335 udev = NULL; 336 #endif 337 if (!udev) 338 return USB_SPEED_UNKNOWN; 339 340 return udev->speed; 341 } 342 343 static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity) 344 { 345 if (!irq) 346 return; 347 348 if (polarity) 349 irq_set_irq_type(irq, polarity); 350 351 enable_irq(irq); 352 enable_irq_wake(irq); 353 } 354 355 static void dwc3_qcom_disable_wakeup_irq(int irq) 356 { 357 if (!irq) 358 return; 359 360 disable_irq_wake(irq); 361 disable_irq_nosync(irq); 362 } 363 364 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) 365 { 366 dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq); 367 368 if (qcom->usb2_speed == USB_SPEED_LOW) { 369 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); 370 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || 371 (qcom->usb2_speed == USB_SPEED_FULL)) { 372 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); 373 } else { 374 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); 375 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); 376 } 377 378 dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq); 379 } 380 381 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) 382 { 383 dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0); 384 385 /* 386 * Configure DP/DM line interrupts based on the USB2 device attached to 387 * the root hub port. When HS/FS device is connected, configure the DP line 388 * as falling edge to detect both disconnect and remote wakeup scenarios. When 389 * LS device is connected, configure DM line as falling edge to detect both 390 * disconnect and remote wakeup. When no device is connected, configure both 391 * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario. 392 */ 393 394 if (qcom->usb2_speed == USB_SPEED_LOW) { 395 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, 396 IRQ_TYPE_EDGE_FALLING); 397 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || 398 (qcom->usb2_speed == USB_SPEED_FULL)) { 399 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, 400 IRQ_TYPE_EDGE_FALLING); 401 } else { 402 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, 403 IRQ_TYPE_EDGE_RISING); 404 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, 405 IRQ_TYPE_EDGE_RISING); 406 } 407 408 dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0); 409 } 410 411 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) 412 { 413 u32 val; 414 int i, ret; 415 416 if (qcom->is_suspended) 417 return 0; 418 419 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); 420 if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) 421 dev_err(qcom->dev, "HS-PHY not in L2\n"); 422 423 for (i = qcom->num_clocks - 1; i >= 0; i--) 424 clk_disable_unprepare(qcom->clks[i]); 425 426 ret = dwc3_qcom_interconnect_disable(qcom); 427 if (ret) 428 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret); 429 430 /* 431 * The role is stable during suspend as role switching is done from a 432 * freezable workqueue. 433 */ 434 if (dwc3_qcom_is_host(qcom) && wakeup) { 435 qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom); 436 dwc3_qcom_enable_interrupts(qcom); 437 } 438 439 qcom->is_suspended = true; 440 441 return 0; 442 } 443 444 static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) 445 { 446 int ret; 447 int i; 448 449 if (!qcom->is_suspended) 450 return 0; 451 452 if (dwc3_qcom_is_host(qcom) && wakeup) 453 dwc3_qcom_disable_interrupts(qcom); 454 455 for (i = 0; i < qcom->num_clocks; i++) { 456 ret = clk_prepare_enable(qcom->clks[i]); 457 if (ret < 0) { 458 while (--i >= 0) 459 clk_disable_unprepare(qcom->clks[i]); 460 return ret; 461 } 462 } 463 464 ret = dwc3_qcom_interconnect_enable(qcom); 465 if (ret) 466 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); 467 468 /* Clear existing events from PHY related to L2 in/out */ 469 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG, 470 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); 471 472 qcom->is_suspended = false; 473 474 return 0; 475 } 476 477 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data) 478 { 479 struct dwc3_qcom *qcom = data; 480 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); 481 482 /* If pm_suspended then let pm_resume take care of resuming h/w */ 483 if (qcom->pm_suspended) 484 return IRQ_HANDLED; 485 486 /* 487 * This is safe as role switching is done from a freezable workqueue 488 * and the wakeup interrupts are disabled as part of resume. 489 */ 490 if (dwc3_qcom_is_host(qcom)) 491 pm_runtime_resume(&dwc->xhci->dev); 492 493 return IRQ_HANDLED; 494 } 495 496 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom) 497 { 498 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ 499 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 500 PIPE_UTMI_CLK_DIS); 501 502 usleep_range(100, 1000); 503 504 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 505 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); 506 507 usleep_range(100, 1000); 508 509 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 510 PIPE_UTMI_CLK_DIS); 511 } 512 513 static int dwc3_qcom_get_irq(struct platform_device *pdev, 514 const char *name, int num) 515 { 516 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 517 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev; 518 struct device_node *np = pdev->dev.of_node; 519 int ret; 520 521 if (np) 522 ret = platform_get_irq_byname_optional(pdev_irq, name); 523 else 524 ret = platform_get_irq_optional(pdev_irq, num); 525 526 return ret; 527 } 528 529 static int dwc3_qcom_setup_irq(struct platform_device *pdev) 530 { 531 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 532 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata; 533 int irq; 534 int ret; 535 536 irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq", 537 pdata ? pdata->hs_phy_irq_index : -1); 538 if (irq > 0) { 539 /* Keep wakeup interrupts disabled until suspend */ 540 irq_set_status_flags(irq, IRQ_NOAUTOEN); 541 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 542 qcom_dwc3_resume_irq, 543 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 544 "qcom_dwc3 HS", qcom); 545 if (ret) { 546 dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret); 547 return ret; 548 } 549 qcom->hs_phy_irq = irq; 550 } 551 552 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq", 553 pdata ? pdata->dp_hs_phy_irq_index : -1); 554 if (irq > 0) { 555 irq_set_status_flags(irq, IRQ_NOAUTOEN); 556 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 557 qcom_dwc3_resume_irq, 558 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 559 "qcom_dwc3 DP_HS", qcom); 560 if (ret) { 561 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret); 562 return ret; 563 } 564 qcom->dp_hs_phy_irq = irq; 565 } 566 567 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq", 568 pdata ? pdata->dm_hs_phy_irq_index : -1); 569 if (irq > 0) { 570 irq_set_status_flags(irq, IRQ_NOAUTOEN); 571 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 572 qcom_dwc3_resume_irq, 573 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 574 "qcom_dwc3 DM_HS", qcom); 575 if (ret) { 576 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret); 577 return ret; 578 } 579 qcom->dm_hs_phy_irq = irq; 580 } 581 582 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq", 583 pdata ? pdata->ss_phy_irq_index : -1); 584 if (irq > 0) { 585 irq_set_status_flags(irq, IRQ_NOAUTOEN); 586 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 587 qcom_dwc3_resume_irq, 588 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 589 "qcom_dwc3 SS", qcom); 590 if (ret) { 591 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret); 592 return ret; 593 } 594 qcom->ss_phy_irq = irq; 595 } 596 597 return 0; 598 } 599 600 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count) 601 { 602 struct device *dev = qcom->dev; 603 struct device_node *np = dev->of_node; 604 int i; 605 606 if (!np || !count) 607 return 0; 608 609 if (count < 0) 610 return count; 611 612 qcom->num_clocks = count; 613 614 qcom->clks = devm_kcalloc(dev, qcom->num_clocks, 615 sizeof(struct clk *), GFP_KERNEL); 616 if (!qcom->clks) 617 return -ENOMEM; 618 619 for (i = 0; i < qcom->num_clocks; i++) { 620 struct clk *clk; 621 int ret; 622 623 clk = of_clk_get(np, i); 624 if (IS_ERR(clk)) { 625 while (--i >= 0) 626 clk_put(qcom->clks[i]); 627 return PTR_ERR(clk); 628 } 629 630 ret = clk_prepare_enable(clk); 631 if (ret < 0) { 632 while (--i >= 0) { 633 clk_disable_unprepare(qcom->clks[i]); 634 clk_put(qcom->clks[i]); 635 } 636 clk_put(clk); 637 638 return ret; 639 } 640 641 qcom->clks[i] = clk; 642 } 643 644 return 0; 645 } 646 647 static const struct property_entry dwc3_qcom_acpi_properties[] = { 648 PROPERTY_ENTRY_STRING("dr_mode", "host"), 649 {} 650 }; 651 652 static const struct software_node dwc3_qcom_swnode = { 653 .properties = dwc3_qcom_acpi_properties, 654 }; 655 656 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev) 657 { 658 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 659 struct device *dev = &pdev->dev; 660 struct resource *res, *child_res = NULL; 661 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : 662 pdev; 663 int irq; 664 int ret; 665 666 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 667 if (!qcom->dwc3) 668 return -ENOMEM; 669 670 qcom->dwc3->dev.parent = dev; 671 qcom->dwc3->dev.type = dev->type; 672 qcom->dwc3->dev.dma_mask = dev->dma_mask; 673 qcom->dwc3->dev.dma_parms = dev->dma_parms; 674 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask; 675 676 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL); 677 if (!child_res) { 678 platform_device_put(qcom->dwc3); 679 return -ENOMEM; 680 } 681 682 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 683 if (!res) { 684 dev_err(&pdev->dev, "failed to get memory resource\n"); 685 ret = -ENODEV; 686 goto out; 687 } 688 689 child_res[0].flags = res->flags; 690 child_res[0].start = res->start; 691 child_res[0].end = child_res[0].start + 692 qcom->acpi_pdata->dwc3_core_base_size; 693 694 irq = platform_get_irq(pdev_irq, 0); 695 if (irq < 0) { 696 ret = irq; 697 goto out; 698 } 699 child_res[1].flags = IORESOURCE_IRQ; 700 child_res[1].start = child_res[1].end = irq; 701 702 ret = platform_device_add_resources(qcom->dwc3, child_res, 2); 703 if (ret) { 704 dev_err(&pdev->dev, "failed to add resources\n"); 705 goto out; 706 } 707 708 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode); 709 if (ret < 0) { 710 dev_err(&pdev->dev, "failed to add properties\n"); 711 goto out; 712 } 713 714 ret = platform_device_add(qcom->dwc3); 715 if (ret) { 716 dev_err(&pdev->dev, "failed to add device\n"); 717 device_remove_software_node(&qcom->dwc3->dev); 718 goto out; 719 } 720 kfree(child_res); 721 return 0; 722 723 out: 724 platform_device_put(qcom->dwc3); 725 kfree(child_res); 726 return ret; 727 } 728 729 static int dwc3_qcom_of_register_core(struct platform_device *pdev) 730 { 731 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 732 struct device_node *np = pdev->dev.of_node, *dwc3_np; 733 struct device *dev = &pdev->dev; 734 int ret; 735 736 dwc3_np = of_get_compatible_child(np, "snps,dwc3"); 737 if (!dwc3_np) { 738 dev_err(dev, "failed to find dwc3 core child\n"); 739 return -ENODEV; 740 } 741 742 ret = of_platform_populate(np, NULL, NULL, dev); 743 if (ret) { 744 dev_err(dev, "failed to register dwc3 core - %d\n", ret); 745 goto node_put; 746 } 747 748 qcom->dwc3 = of_find_device_by_node(dwc3_np); 749 if (!qcom->dwc3) { 750 ret = -ENODEV; 751 dev_err(dev, "failed to get dwc3 platform device\n"); 752 } 753 754 node_put: 755 of_node_put(dwc3_np); 756 757 return ret; 758 } 759 760 static struct platform_device * 761 dwc3_qcom_create_urs_usb_platdev(struct device *dev) 762 { 763 struct fwnode_handle *fwh; 764 struct acpi_device *adev; 765 char name[8]; 766 int ret; 767 int id; 768 769 /* Figure out device id */ 770 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id); 771 if (!ret) 772 return NULL; 773 774 /* Find the child using name */ 775 snprintf(name, sizeof(name), "USB%d", id); 776 fwh = fwnode_get_named_child_node(dev->fwnode, name); 777 if (!fwh) 778 return NULL; 779 780 adev = to_acpi_device_node(fwh); 781 if (!adev) 782 return NULL; 783 784 return acpi_create_platform_device(adev, NULL); 785 } 786 787 static int dwc3_qcom_probe(struct platform_device *pdev) 788 { 789 struct device_node *np = pdev->dev.of_node; 790 struct device *dev = &pdev->dev; 791 struct dwc3_qcom *qcom; 792 struct resource *res, *parent_res = NULL; 793 struct resource local_res; 794 int ret, i; 795 bool ignore_pipe_clk; 796 bool wakeup_source; 797 798 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL); 799 if (!qcom) 800 return -ENOMEM; 801 802 platform_set_drvdata(pdev, qcom); 803 qcom->dev = &pdev->dev; 804 805 if (has_acpi_companion(dev)) { 806 qcom->acpi_pdata = acpi_device_get_match_data(dev); 807 if (!qcom->acpi_pdata) { 808 dev_err(&pdev->dev, "no supporting ACPI device data\n"); 809 return -EINVAL; 810 } 811 } 812 813 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev); 814 if (IS_ERR(qcom->resets)) { 815 return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), 816 "failed to get resets\n"); 817 } 818 819 ret = reset_control_assert(qcom->resets); 820 if (ret) { 821 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret); 822 return ret; 823 } 824 825 usleep_range(10, 1000); 826 827 ret = reset_control_deassert(qcom->resets); 828 if (ret) { 829 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret); 830 goto reset_assert; 831 } 832 833 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np)); 834 if (ret) { 835 dev_err_probe(dev, ret, "failed to get clocks\n"); 836 goto reset_assert; 837 } 838 839 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 840 841 if (np) { 842 parent_res = res; 843 } else { 844 memcpy(&local_res, res, sizeof(struct resource)); 845 parent_res = &local_res; 846 847 parent_res->start = res->start + 848 qcom->acpi_pdata->qscratch_base_offset; 849 parent_res->end = parent_res->start + 850 qcom->acpi_pdata->qscratch_base_size; 851 852 if (qcom->acpi_pdata->is_urs) { 853 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev); 854 if (IS_ERR_OR_NULL(qcom->urs_usb)) { 855 dev_err(dev, "failed to create URS USB platdev\n"); 856 if (!qcom->urs_usb) 857 ret = -ENODEV; 858 else 859 ret = PTR_ERR(qcom->urs_usb); 860 goto clk_disable; 861 } 862 } 863 } 864 865 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res); 866 if (IS_ERR(qcom->qscratch_base)) { 867 ret = PTR_ERR(qcom->qscratch_base); 868 goto clk_disable; 869 } 870 871 ret = dwc3_qcom_setup_irq(pdev); 872 if (ret) { 873 dev_err(dev, "failed to setup IRQs, err=%d\n", ret); 874 goto clk_disable; 875 } 876 877 /* 878 * Disable pipe_clk requirement if specified. Used when dwc3 879 * operates without SSPHY and only HS/FS/LS modes are supported. 880 */ 881 ignore_pipe_clk = device_property_read_bool(dev, 882 "qcom,select-utmi-as-pipe-clk"); 883 if (ignore_pipe_clk) 884 dwc3_qcom_select_utmi_clk(qcom); 885 886 if (np) 887 ret = dwc3_qcom_of_register_core(pdev); 888 else 889 ret = dwc3_qcom_acpi_register_core(pdev); 890 891 if (ret) { 892 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret); 893 goto depopulate; 894 } 895 896 ret = dwc3_qcom_interconnect_init(qcom); 897 if (ret) 898 goto depopulate; 899 900 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev); 901 902 /* enable vbus override for device mode */ 903 if (qcom->mode != USB_DR_MODE_HOST) 904 dwc3_qcom_vbus_override_enable(qcom, true); 905 906 /* register extcon to override sw_vbus on Vbus change later */ 907 ret = dwc3_qcom_register_extcon(qcom); 908 if (ret) 909 goto interconnect_exit; 910 911 wakeup_source = of_property_read_bool(dev->of_node, "wakeup-source"); 912 device_init_wakeup(&pdev->dev, wakeup_source); 913 device_init_wakeup(&qcom->dwc3->dev, wakeup_source); 914 915 qcom->is_suspended = false; 916 pm_runtime_set_active(dev); 917 pm_runtime_enable(dev); 918 pm_runtime_forbid(dev); 919 920 return 0; 921 922 interconnect_exit: 923 dwc3_qcom_interconnect_exit(qcom); 924 depopulate: 925 if (np) 926 of_platform_depopulate(&pdev->dev); 927 else 928 platform_device_put(pdev); 929 clk_disable: 930 for (i = qcom->num_clocks - 1; i >= 0; i--) { 931 clk_disable_unprepare(qcom->clks[i]); 932 clk_put(qcom->clks[i]); 933 } 934 reset_assert: 935 reset_control_assert(qcom->resets); 936 937 return ret; 938 } 939 940 static void dwc3_qcom_remove(struct platform_device *pdev) 941 { 942 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 943 struct device_node *np = pdev->dev.of_node; 944 struct device *dev = &pdev->dev; 945 int i; 946 947 device_remove_software_node(&qcom->dwc3->dev); 948 if (np) 949 of_platform_depopulate(&pdev->dev); 950 else 951 platform_device_put(pdev); 952 953 for (i = qcom->num_clocks - 1; i >= 0; i--) { 954 clk_disable_unprepare(qcom->clks[i]); 955 clk_put(qcom->clks[i]); 956 } 957 qcom->num_clocks = 0; 958 959 dwc3_qcom_interconnect_exit(qcom); 960 reset_control_assert(qcom->resets); 961 962 pm_runtime_allow(dev); 963 pm_runtime_disable(dev); 964 } 965 966 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev) 967 { 968 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 969 bool wakeup = device_may_wakeup(dev); 970 int ret; 971 972 ret = dwc3_qcom_suspend(qcom, wakeup); 973 if (ret) 974 return ret; 975 976 qcom->pm_suspended = true; 977 978 return 0; 979 } 980 981 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev) 982 { 983 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 984 bool wakeup = device_may_wakeup(dev); 985 int ret; 986 987 ret = dwc3_qcom_resume(qcom, wakeup); 988 if (ret) 989 return ret; 990 991 qcom->pm_suspended = false; 992 993 return 0; 994 } 995 996 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev) 997 { 998 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 999 1000 return dwc3_qcom_suspend(qcom, true); 1001 } 1002 1003 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev) 1004 { 1005 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 1006 1007 return dwc3_qcom_resume(qcom, true); 1008 } 1009 1010 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = { 1011 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume) 1012 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume, 1013 NULL) 1014 }; 1015 1016 static const struct of_device_id dwc3_qcom_of_match[] = { 1017 { .compatible = "qcom,dwc3" }, 1018 { } 1019 }; 1020 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match); 1021 1022 #ifdef CONFIG_ACPI 1023 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = { 1024 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, 1025 .qscratch_base_size = SDM845_QSCRATCH_SIZE, 1026 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, 1027 .hs_phy_irq_index = 1, 1028 .dp_hs_phy_irq_index = 4, 1029 .dm_hs_phy_irq_index = 3, 1030 .ss_phy_irq_index = 2 1031 }; 1032 1033 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = { 1034 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, 1035 .qscratch_base_size = SDM845_QSCRATCH_SIZE, 1036 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, 1037 .hs_phy_irq_index = 1, 1038 .dp_hs_phy_irq_index = 4, 1039 .dm_hs_phy_irq_index = 3, 1040 .ss_phy_irq_index = 2, 1041 .is_urs = true, 1042 }; 1043 1044 static const struct acpi_device_id dwc3_qcom_acpi_match[] = { 1045 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata }, 1046 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata }, 1047 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata }, 1048 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata }, 1049 { }, 1050 }; 1051 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match); 1052 #endif 1053 1054 static struct platform_driver dwc3_qcom_driver = { 1055 .probe = dwc3_qcom_probe, 1056 .remove_new = dwc3_qcom_remove, 1057 .driver = { 1058 .name = "dwc3-qcom", 1059 .pm = &dwc3_qcom_dev_pm_ops, 1060 .of_match_table = dwc3_qcom_of_match, 1061 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match), 1062 }, 1063 }; 1064 1065 module_platform_driver(dwc3_qcom_driver); 1066 1067 MODULE_LICENSE("GPL v2"); 1068 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver"); 1069