1 /* 2 * Copyright (C) 2004-2016 Synopsys, Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions, and the following disclaimer, 9 * without modification. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. The names of the above-listed copyright holders may not be used 14 * to endorse or promote products derived from this software without 15 * specific prior written permission. 16 * 17 * ALTERNATIVELY, this software may be distributed under the terms of the 18 * GNU General Public License ("GPL") as published by the Free Software 19 * Foundation; either version 2 of the License, or (at your option) any 20 * later version. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 23 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 24 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 26 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 30 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/of_device.h> 38 39 #include "core.h" 40 41 static const struct dwc2_core_params params_hi6220 = { 42 .otg_cap = 2, /* No HNP/SRP capable */ 43 .dma_desc_enable = 0, 44 .dma_desc_fs_enable = 0, 45 .speed = 0, /* High Speed */ 46 .enable_dynamic_fifo = 1, 47 .en_multiple_tx_fifo = 1, 48 .host_rx_fifo_size = 512, 49 .host_nperio_tx_fifo_size = 512, 50 .host_perio_tx_fifo_size = 512, 51 .max_transfer_size = 65535, 52 .max_packet_count = 511, 53 .host_channels = 16, 54 .phy_type = 1, /* UTMI */ 55 .phy_utmi_width = 8, 56 .phy_ulpi_ddr = 0, /* Single */ 57 .phy_ulpi_ext_vbus = 0, 58 .i2c_enable = 0, 59 .ulpi_fs_ls = 0, 60 .host_support_fs_ls_low_power = 0, 61 .host_ls_low_power_phy_clk = 0, /* 48 MHz */ 62 .ts_dline = 0, 63 .reload_ctl = 0, 64 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 65 GAHBCFG_HBSTLEN_SHIFT, 66 .uframe_sched = 0, 67 .external_id_pin_ctl = -1, 68 .hibernation = -1, 69 }; 70 71 static const struct dwc2_core_params params_bcm2835 = { 72 .otg_cap = 0, /* HNP/SRP capable */ 73 .dma_desc_enable = 0, 74 .dma_desc_fs_enable = 0, 75 .speed = 0, /* High Speed */ 76 .enable_dynamic_fifo = 1, 77 .en_multiple_tx_fifo = 1, 78 .host_rx_fifo_size = 774, /* 774 DWORDs */ 79 .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */ 80 .host_perio_tx_fifo_size = 512, /* 512 DWORDs */ 81 .max_transfer_size = 65535, 82 .max_packet_count = 511, 83 .host_channels = 8, 84 .phy_type = 1, /* UTMI */ 85 .phy_utmi_width = 8, /* 8 bits */ 86 .phy_ulpi_ddr = 0, /* Single */ 87 .phy_ulpi_ext_vbus = 0, 88 .i2c_enable = 0, 89 .ulpi_fs_ls = 0, 90 .host_support_fs_ls_low_power = 0, 91 .host_ls_low_power_phy_clk = 0, /* 48 MHz */ 92 .ts_dline = 0, 93 .reload_ctl = 0, 94 .ahbcfg = 0x10, 95 .uframe_sched = 0, 96 .external_id_pin_ctl = -1, 97 .hibernation = -1, 98 }; 99 100 static const struct dwc2_core_params params_rk3066 = { 101 .otg_cap = 2, /* non-HNP/non-SRP */ 102 .dma_desc_enable = 0, 103 .dma_desc_fs_enable = 0, 104 .speed = -1, 105 .enable_dynamic_fifo = 1, 106 .en_multiple_tx_fifo = -1, 107 .host_rx_fifo_size = 525, /* 525 DWORDs */ 108 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */ 109 .host_perio_tx_fifo_size = 256, /* 256 DWORDs */ 110 .max_transfer_size = -1, 111 .max_packet_count = -1, 112 .host_channels = -1, 113 .phy_type = -1, 114 .phy_utmi_width = -1, 115 .phy_ulpi_ddr = -1, 116 .phy_ulpi_ext_vbus = -1, 117 .i2c_enable = -1, 118 .ulpi_fs_ls = -1, 119 .host_support_fs_ls_low_power = -1, 120 .host_ls_low_power_phy_clk = -1, 121 .ts_dline = -1, 122 .reload_ctl = -1, 123 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 124 GAHBCFG_HBSTLEN_SHIFT, 125 .uframe_sched = -1, 126 .external_id_pin_ctl = -1, 127 .hibernation = -1, 128 }; 129 130 static const struct dwc2_core_params params_ltq = { 131 .otg_cap = 2, /* non-HNP/non-SRP */ 132 .dma_desc_enable = -1, 133 .dma_desc_fs_enable = -1, 134 .speed = -1, 135 .enable_dynamic_fifo = -1, 136 .en_multiple_tx_fifo = -1, 137 .host_rx_fifo_size = 288, /* 288 DWORDs */ 138 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */ 139 .host_perio_tx_fifo_size = 96, /* 96 DWORDs */ 140 .max_transfer_size = 65535, 141 .max_packet_count = 511, 142 .host_channels = -1, 143 .phy_type = -1, 144 .phy_utmi_width = -1, 145 .phy_ulpi_ddr = -1, 146 .phy_ulpi_ext_vbus = -1, 147 .i2c_enable = -1, 148 .ulpi_fs_ls = -1, 149 .host_support_fs_ls_low_power = -1, 150 .host_ls_low_power_phy_clk = -1, 151 .ts_dline = -1, 152 .reload_ctl = -1, 153 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 154 GAHBCFG_HBSTLEN_SHIFT, 155 .uframe_sched = -1, 156 .external_id_pin_ctl = -1, 157 .hibernation = -1, 158 }; 159 160 static const struct dwc2_core_params params_amlogic = { 161 .otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE, 162 .dma_desc_enable = 0, 163 .dma_desc_fs_enable = 0, 164 .speed = DWC2_SPEED_PARAM_HIGH, 165 .enable_dynamic_fifo = 1, 166 .en_multiple_tx_fifo = -1, 167 .host_rx_fifo_size = 512, 168 .host_nperio_tx_fifo_size = 500, 169 .host_perio_tx_fifo_size = 500, 170 .max_transfer_size = -1, 171 .max_packet_count = -1, 172 .host_channels = 16, 173 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, 174 .phy_utmi_width = -1, 175 .phy_ulpi_ddr = -1, 176 .phy_ulpi_ext_vbus = -1, 177 .i2c_enable = -1, 178 .ulpi_fs_ls = -1, 179 .host_support_fs_ls_low_power = -1, 180 .host_ls_low_power_phy_clk = -1, 181 .ts_dline = -1, 182 .reload_ctl = 1, 183 .ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 184 GAHBCFG_HBSTLEN_SHIFT, 185 .uframe_sched = 0, 186 .external_id_pin_ctl = -1, 187 .hibernation = -1, 188 }; 189 190 const struct of_device_id dwc2_of_match_table[] = { 191 { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 }, 192 { .compatible = "hisilicon,hi6220-usb", .data = ¶ms_hi6220 }, 193 { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 }, 194 { .compatible = "lantiq,arx100-usb", .data = ¶ms_ltq }, 195 { .compatible = "lantiq,xrx200-usb", .data = ¶ms_ltq }, 196 { .compatible = "snps,dwc2", .data = NULL }, 197 { .compatible = "samsung,s3c6400-hsotg", .data = NULL}, 198 { .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic }, 199 { .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic }, 200 { .compatible = "amcc,dwc-otg", .data = NULL }, 201 {}, 202 }; 203 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 204 205 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 206 { 207 u8 val; 208 209 switch (hsotg->hw_params.op_mode) { 210 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 211 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 212 break; 213 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 214 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 215 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 216 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 217 break; 218 default: 219 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 220 break; 221 } 222 223 hsotg->params.otg_cap = val; 224 } 225 226 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 227 { 228 int val; 229 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 230 231 val = DWC2_PHY_TYPE_PARAM_FS; 232 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 233 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 234 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 235 val = DWC2_PHY_TYPE_PARAM_UTMI; 236 else 237 val = DWC2_PHY_TYPE_PARAM_ULPI; 238 } 239 240 if (dwc2_is_fs_iot(hsotg)) 241 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 242 243 hsotg->params.phy_type = val; 244 } 245 246 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 247 { 248 int val; 249 250 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 251 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 252 253 if (dwc2_is_fs_iot(hsotg)) 254 val = DWC2_SPEED_PARAM_FULL; 255 256 if (dwc2_is_hs_iot(hsotg)) 257 val = DWC2_SPEED_PARAM_HIGH; 258 259 hsotg->params.speed = val; 260 } 261 262 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 263 { 264 int val; 265 266 val = (hsotg->hw_params.utmi_phy_data_width == 267 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 268 269 hsotg->params.phy_utmi_width = val; 270 } 271 272 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 273 { 274 struct dwc2_core_params *p = &hsotg->params; 275 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE; 276 277 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 278 memcpy(&p->g_tx_fifo_size[1], 279 p_tx_fifo, 280 sizeof(p_tx_fifo)); 281 } 282 283 /** 284 * dwc2_set_default_params() - Set all core parameters to their 285 * auto-detected default values. 286 */ 287 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 288 { 289 struct dwc2_hw_params *hw = &hsotg->hw_params; 290 struct dwc2_core_params *p = &hsotg->params; 291 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 292 293 dwc2_set_param_otg_cap(hsotg); 294 dwc2_set_param_phy_type(hsotg); 295 dwc2_set_param_speed(hsotg); 296 dwc2_set_param_phy_utmi_width(hsotg); 297 p->phy_ulpi_ddr = false; 298 p->phy_ulpi_ext_vbus = false; 299 300 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 301 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 302 p->i2c_enable = hw->i2c_enable; 303 p->ulpi_fs_ls = false; 304 p->ts_dline = false; 305 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 306 p->uframe_sched = true; 307 p->external_id_pin_ctl = false; 308 p->hibernation = false; 309 p->max_packet_count = hw->max_packet_count; 310 p->max_transfer_size = hw->max_transfer_size; 311 p->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT; 312 313 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 314 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 315 p->host_dma = dma_capable; 316 p->dma_desc_enable = false; 317 p->dma_desc_fs_enable = false; 318 p->host_support_fs_ls_low_power = false; 319 p->host_ls_low_power_phy_clk = false; 320 p->host_channels = hw->host_channels; 321 p->host_rx_fifo_size = hw->rx_fifo_size; 322 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 323 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 324 } 325 326 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 327 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 328 p->g_dma = dma_capable; 329 p->g_dma_desc = hw->dma_desc_enable; 330 331 /* 332 * The values for g_rx_fifo_size (2048) and 333 * g_np_tx_fifo_size (1024) come from the legacy s3c 334 * gadget driver. These defaults have been hard-coded 335 * for some time so many platforms depend on these 336 * values. Leave them as defaults for now and only 337 * auto-detect if the hardware does not support the 338 * default. 339 */ 340 p->g_rx_fifo_size = 2048; 341 p->g_np_tx_fifo_size = 1024; 342 dwc2_set_param_tx_fifo_sizes(hsotg); 343 } 344 } 345 346 /** 347 * dwc2_get_device_properties() - Read in device properties. 348 * 349 * Read in the device properties and adjust core parameters if needed. 350 */ 351 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 352 { 353 struct dwc2_core_params *p = &hsotg->params; 354 int num; 355 356 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 357 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 358 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 359 &p->g_rx_fifo_size); 360 361 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 362 &p->g_np_tx_fifo_size); 363 364 num = device_property_read_u32_array(hsotg->dev, 365 "g-tx-fifo-size", 366 NULL, 0); 367 368 if (num > 0) { 369 num = min(num, 15); 370 memset(p->g_tx_fifo_size, 0, 371 sizeof(p->g_tx_fifo_size)); 372 device_property_read_u32_array(hsotg->dev, 373 "g-tx-fifo-size", 374 &p->g_tx_fifo_size[1], 375 num); 376 } 377 } 378 } 379 380 /* 381 * Gets host hardware parameters. Forces host mode if not currently in 382 * host mode. Should be called immediately after a core soft reset in 383 * order to get the reset values. 384 */ 385 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 386 { 387 struct dwc2_hw_params *hw = &hsotg->hw_params; 388 u32 gnptxfsiz; 389 u32 hptxfsiz; 390 bool forced; 391 392 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 393 return; 394 395 forced = dwc2_force_mode_if_needed(hsotg, true); 396 397 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 398 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 399 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 400 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); 401 402 if (forced) 403 dwc2_clear_force_mode(hsotg); 404 405 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 406 FIFOSIZE_DEPTH_SHIFT; 407 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 408 FIFOSIZE_DEPTH_SHIFT; 409 } 410 411 /* 412 * Gets device hardware parameters. Forces device mode if not 413 * currently in device mode. Should be called immediately after a core 414 * soft reset in order to get the reset values. 415 */ 416 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 417 { 418 struct dwc2_hw_params *hw = &hsotg->hw_params; 419 bool forced; 420 u32 gnptxfsiz; 421 422 if (hsotg->dr_mode == USB_DR_MODE_HOST) 423 return; 424 425 forced = dwc2_force_mode_if_needed(hsotg, false); 426 427 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 428 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 429 430 if (forced) 431 dwc2_clear_force_mode(hsotg); 432 433 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 434 FIFOSIZE_DEPTH_SHIFT; 435 } 436 437 /** 438 * During device initialization, read various hardware configuration 439 * registers and interpret the contents. 440 */ 441 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 442 { 443 struct dwc2_hw_params *hw = &hsotg->hw_params; 444 unsigned int width; 445 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 446 u32 grxfsiz; 447 448 /* 449 * Attempt to ensure this device is really a DWC_otg Controller. 450 * Read and verify the GSNPSID register contents. The value should be 451 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", 452 * as in "OTG version 2.xx" or "OTG version 3.xx". 453 */ 454 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); 455 if ((hw->snpsid & 0xfffff000) != 0x4f542000 && 456 (hw->snpsid & 0xfffff000) != 0x4f543000 && 457 (hw->snpsid & 0xffff0000) != 0x55310000 && 458 (hw->snpsid & 0xffff0000) != 0x55320000) { 459 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 460 hw->snpsid); 461 return -ENODEV; 462 } 463 464 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 465 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 466 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 467 468 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); 469 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 470 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); 471 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 472 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 473 474 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); 475 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); 476 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); 477 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); 478 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); 479 480 /* 481 * Host specific hardware parameters. Reading these parameters 482 * requires the controller to be in host mode. The mode will 483 * be forced, if necessary, to read these values. 484 */ 485 dwc2_get_host_hwparams(hsotg); 486 dwc2_get_dev_hwparams(hsotg); 487 488 /* hwcfg1 */ 489 hw->dev_ep_dirs = hwcfg1; 490 491 /* hwcfg2 */ 492 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 493 GHWCFG2_OP_MODE_SHIFT; 494 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 495 GHWCFG2_ARCHITECTURE_SHIFT; 496 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 497 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 498 GHWCFG2_NUM_HOST_CHAN_SHIFT); 499 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 500 GHWCFG2_HS_PHY_TYPE_SHIFT; 501 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 502 GHWCFG2_FS_PHY_TYPE_SHIFT; 503 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 504 GHWCFG2_NUM_DEV_EP_SHIFT; 505 hw->nperio_tx_q_depth = 506 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 507 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 508 hw->host_perio_tx_q_depth = 509 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 510 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 511 hw->dev_token_q_depth = 512 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 513 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 514 515 /* hwcfg3 */ 516 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 517 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 518 hw->max_transfer_size = (1 << (width + 11)) - 1; 519 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 520 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 521 hw->max_packet_count = (1 << (width + 4)) - 1; 522 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 523 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 524 GHWCFG3_DFIFO_DEPTH_SHIFT; 525 526 /* hwcfg4 */ 527 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 528 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 529 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 530 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 531 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 532 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 533 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 534 535 /* fifo sizes */ 536 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 537 GRXFSIZ_DEPTH_SHIFT; 538 539 dev_dbg(hsotg->dev, "Detected values from hardware:\n"); 540 dev_dbg(hsotg->dev, " op_mode=%d\n", 541 hw->op_mode); 542 dev_dbg(hsotg->dev, " arch=%d\n", 543 hw->arch); 544 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", 545 hw->dma_desc_enable); 546 dev_dbg(hsotg->dev, " power_optimized=%d\n", 547 hw->power_optimized); 548 dev_dbg(hsotg->dev, " i2c_enable=%d\n", 549 hw->i2c_enable); 550 dev_dbg(hsotg->dev, " hs_phy_type=%d\n", 551 hw->hs_phy_type); 552 dev_dbg(hsotg->dev, " fs_phy_type=%d\n", 553 hw->fs_phy_type); 554 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n", 555 hw->utmi_phy_data_width); 556 dev_dbg(hsotg->dev, " num_dev_ep=%d\n", 557 hw->num_dev_ep); 558 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", 559 hw->num_dev_perio_in_ep); 560 dev_dbg(hsotg->dev, " host_channels=%d\n", 561 hw->host_channels); 562 dev_dbg(hsotg->dev, " max_transfer_size=%d\n", 563 hw->max_transfer_size); 564 dev_dbg(hsotg->dev, " max_packet_count=%d\n", 565 hw->max_packet_count); 566 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", 567 hw->nperio_tx_q_depth); 568 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", 569 hw->host_perio_tx_q_depth); 570 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", 571 hw->dev_token_q_depth); 572 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", 573 hw->enable_dynamic_fifo); 574 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", 575 hw->en_multiple_tx_fifo); 576 dev_dbg(hsotg->dev, " total_fifo_size=%d\n", 577 hw->total_fifo_size); 578 dev_dbg(hsotg->dev, " rx_fifo_size=%d\n", 579 hw->rx_fifo_size); 580 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", 581 hw->host_nperio_tx_fifo_size); 582 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", 583 hw->host_perio_tx_fifo_size); 584 dev_dbg(hsotg->dev, "\n"); 585 586 return 0; 587 } 588 589 int dwc2_init_params(struct dwc2_hsotg *hsotg) 590 { 591 dwc2_set_default_params(hsotg); 592 dwc2_get_device_properties(hsotg); 593 594 return 0; 595 } 596