xref: /openbmc/linux/drivers/usb/dwc2/params.c (revision d8fae8b936824b3ffe55a0408b84022244603a32)
1323230efSJohn Youn /*
2323230efSJohn Youn  * Copyright (C) 2004-2016 Synopsys, Inc.
3323230efSJohn Youn  *
4323230efSJohn Youn  * Redistribution and use in source and binary forms, with or without
5323230efSJohn Youn  * modification, are permitted provided that the following conditions
6323230efSJohn Youn  * are met:
7323230efSJohn Youn  * 1. Redistributions of source code must retain the above copyright
8323230efSJohn Youn  *    notice, this list of conditions, and the following disclaimer,
9323230efSJohn Youn  *    without modification.
10323230efSJohn Youn  * 2. Redistributions in binary form must reproduce the above copyright
11323230efSJohn Youn  *    notice, this list of conditions and the following disclaimer in the
12323230efSJohn Youn  *    documentation and/or other materials provided with the distribution.
13323230efSJohn Youn  * 3. The names of the above-listed copyright holders may not be used
14323230efSJohn Youn  *    to endorse or promote products derived from this software without
15323230efSJohn Youn  *    specific prior written permission.
16323230efSJohn Youn  *
17323230efSJohn Youn  * ALTERNATIVELY, this software may be distributed under the terms of the
18323230efSJohn Youn  * GNU General Public License ("GPL") as published by the Free Software
19323230efSJohn Youn  * Foundation; either version 2 of the License, or (at your option) any
20323230efSJohn Youn  * later version.
21323230efSJohn Youn  *
22323230efSJohn Youn  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
23323230efSJohn Youn  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
24323230efSJohn Youn  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25323230efSJohn Youn  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
26323230efSJohn Youn  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
27323230efSJohn Youn  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28323230efSJohn Youn  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29323230efSJohn Youn  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
30323230efSJohn Youn  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
31323230efSJohn Youn  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32323230efSJohn Youn  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33323230efSJohn Youn  */
34323230efSJohn Youn 
35323230efSJohn Youn #include <linux/kernel.h>
36323230efSJohn Youn #include <linux/module.h>
37323230efSJohn Youn #include <linux/of_device.h>
38323230efSJohn Youn 
39323230efSJohn Youn #include "core.h"
40323230efSJohn Youn 
417de1debcSJohn Youn static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
427de1debcSJohn Youn {
437de1debcSJohn Youn 	struct dwc2_core_params *p = &hsotg->params;
44323230efSJohn Youn 
457de1debcSJohn Youn 	p->host_rx_fifo_size = 774;
467de1debcSJohn Youn 	p->max_transfer_size = 65535;
477de1debcSJohn Youn 	p->max_packet_count = 511;
487de1debcSJohn Youn 	p->ahbcfg = 0x10;
497de1debcSJohn Youn 	p->uframe_sched = false;
507de1debcSJohn Youn }
51323230efSJohn Youn 
527de1debcSJohn Youn static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
537de1debcSJohn Youn {
547de1debcSJohn Youn 	struct dwc2_core_params *p = &hsotg->params;
55323230efSJohn Youn 
567de1debcSJohn Youn 	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
577de1debcSJohn Youn 	p->speed = DWC2_SPEED_PARAM_HIGH;
587de1debcSJohn Youn 	p->host_rx_fifo_size = 512;
597de1debcSJohn Youn 	p->host_nperio_tx_fifo_size = 512;
607de1debcSJohn Youn 	p->host_perio_tx_fifo_size = 512;
617de1debcSJohn Youn 	p->max_transfer_size = 65535;
627de1debcSJohn Youn 	p->max_packet_count = 511;
637de1debcSJohn Youn 	p->host_channels = 16;
647de1debcSJohn Youn 	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
657de1debcSJohn Youn 	p->phy_utmi_width = 8;
667de1debcSJohn Youn 	p->i2c_enable = false;
677de1debcSJohn Youn 	p->reload_ctl = false;
687de1debcSJohn Youn 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
697de1debcSJohn Youn 		GAHBCFG_HBSTLEN_SHIFT;
707de1debcSJohn Youn 	p->uframe_sched = false;
71ca8b0332SChen Yu 	p->change_speed_quirk = true;
727de1debcSJohn Youn }
73323230efSJohn Youn 
747de1debcSJohn Youn static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
757de1debcSJohn Youn {
767de1debcSJohn Youn 	struct dwc2_core_params *p = &hsotg->params;
777de1debcSJohn Youn 
787de1debcSJohn Youn 	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
797de1debcSJohn Youn 	p->host_rx_fifo_size = 525;
807de1debcSJohn Youn 	p->host_nperio_tx_fifo_size = 128;
817de1debcSJohn Youn 	p->host_perio_tx_fifo_size = 256;
827de1debcSJohn Youn 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
837de1debcSJohn Youn 		GAHBCFG_HBSTLEN_SHIFT;
847de1debcSJohn Youn }
857de1debcSJohn Youn 
867de1debcSJohn Youn static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
877de1debcSJohn Youn {
887de1debcSJohn Youn 	struct dwc2_core_params *p = &hsotg->params;
897de1debcSJohn Youn 
907de1debcSJohn Youn 	p->otg_cap = 2;
917de1debcSJohn Youn 	p->host_rx_fifo_size = 288;
927de1debcSJohn Youn 	p->host_nperio_tx_fifo_size = 128;
937de1debcSJohn Youn 	p->host_perio_tx_fifo_size = 96;
947de1debcSJohn Youn 	p->max_transfer_size = 65535;
957de1debcSJohn Youn 	p->max_packet_count = 511;
967de1debcSJohn Youn 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
977de1debcSJohn Youn 		GAHBCFG_HBSTLEN_SHIFT;
987de1debcSJohn Youn }
997de1debcSJohn Youn 
1007de1debcSJohn Youn static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
1017de1debcSJohn Youn {
1027de1debcSJohn Youn 	struct dwc2_core_params *p = &hsotg->params;
1037de1debcSJohn Youn 
1047de1debcSJohn Youn 	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
1057de1debcSJohn Youn 	p->speed = DWC2_SPEED_PARAM_HIGH;
1067de1debcSJohn Youn 	p->host_rx_fifo_size = 512;
1077de1debcSJohn Youn 	p->host_nperio_tx_fifo_size = 500;
1087de1debcSJohn Youn 	p->host_perio_tx_fifo_size = 500;
1097de1debcSJohn Youn 	p->host_channels = 16;
1107de1debcSJohn Youn 	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
1117de1debcSJohn Youn 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
1127de1debcSJohn Youn 		GAHBCFG_HBSTLEN_SHIFT;
1137de1debcSJohn Youn 	p->uframe_sched = false;
1147de1debcSJohn Youn }
1157de1debcSJohn Youn 
1167de1debcSJohn Youn static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
1177de1debcSJohn Youn {
1187de1debcSJohn Youn 	struct dwc2_core_params *p = &hsotg->params;
1197de1debcSJohn Youn 
1207de1debcSJohn Youn 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
1217de1debcSJohn Youn }
122323230efSJohn Youn 
123e35b1350SBruno Herrera static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
124e35b1350SBruno Herrera {
125e35b1350SBruno Herrera 	struct dwc2_core_params *p = &hsotg->params;
126e35b1350SBruno Herrera 
127e35b1350SBruno Herrera 	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
128e35b1350SBruno Herrera 	p->speed = DWC2_SPEED_PARAM_FULL;
129e35b1350SBruno Herrera 	p->host_rx_fifo_size = 128;
130e35b1350SBruno Herrera 	p->host_nperio_tx_fifo_size = 96;
131e35b1350SBruno Herrera 	p->host_perio_tx_fifo_size = 96;
132e35b1350SBruno Herrera 	p->max_packet_count = 256;
133e35b1350SBruno Herrera 	p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
134e35b1350SBruno Herrera 	p->i2c_enable = false;
135e35b1350SBruno Herrera 	p->uframe_sched = false;
136e35b1350SBruno Herrera 	p->activate_stm_fs_transceiver = true;
137e35b1350SBruno Herrera }
138e35b1350SBruno Herrera 
139*d8fae8b9SAmelie Delaunay static void dwc2_set_stm32f7xx_hsotg_params(struct dwc2_hsotg *hsotg)
140*d8fae8b9SAmelie Delaunay {
141*d8fae8b9SAmelie Delaunay 	struct dwc2_core_params *p = &hsotg->params;
142*d8fae8b9SAmelie Delaunay 
143*d8fae8b9SAmelie Delaunay 	p->host_rx_fifo_size = 622;
144*d8fae8b9SAmelie Delaunay 	p->host_nperio_tx_fifo_size = 128;
145*d8fae8b9SAmelie Delaunay 	p->host_perio_tx_fifo_size = 256;
146*d8fae8b9SAmelie Delaunay }
147*d8fae8b9SAmelie Delaunay 
148323230efSJohn Youn const struct of_device_id dwc2_of_match_table[] = {
1497de1debcSJohn Youn 	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
1507de1debcSJohn Youn 	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
1517de1debcSJohn Youn 	{ .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
1527de1debcSJohn Youn 	{ .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
1537de1debcSJohn Youn 	{ .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
1547de1debcSJohn Youn 	{ .compatible = "snps,dwc2" },
1557de1debcSJohn Youn 	{ .compatible = "samsung,s3c6400-hsotg" },
15655b644fdSMartin Blumenstingl 	{ .compatible = "amlogic,meson8-usb",
15755b644fdSMartin Blumenstingl 	  .data = dwc2_set_amlogic_params },
1587de1debcSJohn Youn 	{ .compatible = "amlogic,meson8b-usb",
1597de1debcSJohn Youn 	  .data = dwc2_set_amlogic_params },
1607de1debcSJohn Youn 	{ .compatible = "amlogic,meson-gxbb-usb",
1617de1debcSJohn Youn 	  .data = dwc2_set_amlogic_params },
1627de1debcSJohn Youn 	{ .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
163e35b1350SBruno Herrera 	{ .compatible = "st,stm32f4x9-fsotg",
164e35b1350SBruno Herrera 	  .data = dwc2_set_stm32f4x9_fsotg_params },
165e35b1350SBruno Herrera 	{ .compatible = "st,stm32f4x9-hsotg" },
166*d8fae8b9SAmelie Delaunay 	{ .compatible = "st,stm32f7xx-hsotg",
167*d8fae8b9SAmelie Delaunay 	  .data = dwc2_set_stm32f7xx_hsotg_params },
168323230efSJohn Youn 	{},
169323230efSJohn Youn };
170323230efSJohn Youn MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
171323230efSJohn Youn 
172245977c9SJohn Youn static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
17305ee799fSJohn Youn {
174245977c9SJohn Youn 	u8 val;
17505ee799fSJohn Youn 
176323230efSJohn Youn 	switch (hsotg->hw_params.op_mode) {
177323230efSJohn Youn 	case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
178323230efSJohn Youn 		val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
179323230efSJohn Youn 		break;
180323230efSJohn Youn 	case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
181323230efSJohn Youn 	case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
182323230efSJohn Youn 	case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
183323230efSJohn Youn 		val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
184323230efSJohn Youn 		break;
185323230efSJohn Youn 	default:
186323230efSJohn Youn 		val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
187323230efSJohn Youn 		break;
188323230efSJohn Youn 	}
189323230efSJohn Youn 
190bea8e86cSJohn Youn 	hsotg->params.otg_cap = val;
191323230efSJohn Youn }
192323230efSJohn Youn 
193245977c9SJohn Youn static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
194323230efSJohn Youn {
195245977c9SJohn Youn 	int val;
196245977c9SJohn Youn 	u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
197323230efSJohn Youn 
198323230efSJohn Youn 	val = DWC2_PHY_TYPE_PARAM_FS;
199323230efSJohn Youn 	if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
200323230efSJohn Youn 		if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
201323230efSJohn Youn 		    hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
202323230efSJohn Youn 			val = DWC2_PHY_TYPE_PARAM_UTMI;
203323230efSJohn Youn 		else
204323230efSJohn Youn 			val = DWC2_PHY_TYPE_PARAM_ULPI;
205323230efSJohn Youn 	}
206245977c9SJohn Youn 
207245977c9SJohn Youn 	if (dwc2_is_fs_iot(hsotg))
208245977c9SJohn Youn 		hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
209323230efSJohn Youn 
210bea8e86cSJohn Youn 	hsotg->params.phy_type = val;
211323230efSJohn Youn }
212323230efSJohn Youn 
213245977c9SJohn Youn static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
214323230efSJohn Youn {
215245977c9SJohn Youn 	int val;
216323230efSJohn Youn 
217245977c9SJohn Youn 	val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
218323230efSJohn Youn 		DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
219245977c9SJohn Youn 
220245977c9SJohn Youn 	if (dwc2_is_fs_iot(hsotg))
221245977c9SJohn Youn 		val = DWC2_SPEED_PARAM_FULL;
222245977c9SJohn Youn 
223245977c9SJohn Youn 	if (dwc2_is_hs_iot(hsotg))
224245977c9SJohn Youn 		val = DWC2_SPEED_PARAM_HIGH;
225323230efSJohn Youn 
226bea8e86cSJohn Youn 	hsotg->params.speed = val;
227323230efSJohn Youn }
228323230efSJohn Youn 
229245977c9SJohn Youn static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
230323230efSJohn Youn {
231245977c9SJohn Youn 	int val;
232323230efSJohn Youn 
233323230efSJohn Youn 	val = (hsotg->hw_params.utmi_phy_data_width ==
234323230efSJohn Youn 	       GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
235323230efSJohn Youn 
236bea8e86cSJohn Youn 	hsotg->params.phy_utmi_width = val;
237323230efSJohn Youn }
238323230efSJohn Youn 
23905ee799fSJohn Youn static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
24005ee799fSJohn Youn {
24105ee799fSJohn Youn 	struct dwc2_core_params *p = &hsotg->params;
242c138ecfaSSevak Arakelyan 	int depth_average;
243c138ecfaSSevak Arakelyan 	int fifo_count;
244c138ecfaSSevak Arakelyan 	int i;
245c138ecfaSSevak Arakelyan 
246c138ecfaSSevak Arakelyan 	fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
24705ee799fSJohn Youn 
248245977c9SJohn Youn 	memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
249c138ecfaSSevak Arakelyan 	depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
250c138ecfaSSevak Arakelyan 	for (i = 1; i <= fifo_count; i++)
251c138ecfaSSevak Arakelyan 		p->g_tx_fifo_size[i] = depth_average;
2529962b62fSJohn Youn }
2539962b62fSJohn Youn 
25405ee799fSJohn Youn /**
255245977c9SJohn Youn  * dwc2_set_default_params() - Set all core parameters to their
256245977c9SJohn Youn  * auto-detected default values.
257323230efSJohn Youn  */
258245977c9SJohn Youn static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
259323230efSJohn Youn {
26005ee799fSJohn Youn 	struct dwc2_hw_params *hw = &hsotg->hw_params;
26105ee799fSJohn Youn 	struct dwc2_core_params *p = &hsotg->params;
2626b66ce51SJohn Youn 	bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
263323230efSJohn Youn 
264245977c9SJohn Youn 	dwc2_set_param_otg_cap(hsotg);
265245977c9SJohn Youn 	dwc2_set_param_phy_type(hsotg);
266245977c9SJohn Youn 	dwc2_set_param_speed(hsotg);
267245977c9SJohn Youn 	dwc2_set_param_phy_utmi_width(hsotg);
268245977c9SJohn Youn 	p->phy_ulpi_ddr = false;
269245977c9SJohn Youn 	p->phy_ulpi_ext_vbus = false;
270245977c9SJohn Youn 
271245977c9SJohn Youn 	p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
272245977c9SJohn Youn 	p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
273245977c9SJohn Youn 	p->i2c_enable = hw->i2c_enable;
274245977c9SJohn Youn 	p->ulpi_fs_ls = false;
275245977c9SJohn Youn 	p->ts_dline = false;
276245977c9SJohn Youn 	p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
277245977c9SJohn Youn 	p->uframe_sched = true;
278245977c9SJohn Youn 	p->external_id_pin_ctl = false;
279245977c9SJohn Youn 	p->hibernation = false;
280245977c9SJohn Youn 	p->max_packet_count = hw->max_packet_count;
281245977c9SJohn Youn 	p->max_transfer_size = hw->max_transfer_size;
282245977c9SJohn Youn 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT;
283245977c9SJohn Youn 
2846b66ce51SJohn Youn 	if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
2856b66ce51SJohn Youn 	    (hsotg->dr_mode == USB_DR_MODE_OTG)) {
286245977c9SJohn Youn 		p->host_dma = dma_capable;
287245977c9SJohn Youn 		p->dma_desc_enable = false;
288245977c9SJohn Youn 		p->dma_desc_fs_enable = false;
289245977c9SJohn Youn 		p->host_support_fs_ls_low_power = false;
290245977c9SJohn Youn 		p->host_ls_low_power_phy_clk = false;
291245977c9SJohn Youn 		p->host_channels = hw->host_channels;
292245977c9SJohn Youn 		p->host_rx_fifo_size = hw->rx_fifo_size;
293245977c9SJohn Youn 		p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
294245977c9SJohn Youn 		p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
2956b66ce51SJohn Youn 	}
2966b66ce51SJohn Youn 
29705ee799fSJohn Youn 	if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
29805ee799fSJohn Youn 	    (hsotg->dr_mode == USB_DR_MODE_OTG)) {
299245977c9SJohn Youn 		p->g_dma = dma_capable;
300245977c9SJohn Youn 		p->g_dma_desc = hw->dma_desc_enable;
30105ee799fSJohn Youn 
30205ee799fSJohn Youn 		/*
30305ee799fSJohn Youn 		 * The values for g_rx_fifo_size (2048) and
30405ee799fSJohn Youn 		 * g_np_tx_fifo_size (1024) come from the legacy s3c
30505ee799fSJohn Youn 		 * gadget driver. These defaults have been hard-coded
30605ee799fSJohn Youn 		 * for some time so many platforms depend on these
30705ee799fSJohn Youn 		 * values. Leave them as defaults for now and only
30805ee799fSJohn Youn 		 * auto-detect if the hardware does not support the
30905ee799fSJohn Youn 		 * default.
31005ee799fSJohn Youn 		 */
311245977c9SJohn Youn 		p->g_rx_fifo_size = 2048;
312245977c9SJohn Youn 		p->g_np_tx_fifo_size = 1024;
31305ee799fSJohn Youn 		dwc2_set_param_tx_fifo_sizes(hsotg);
31405ee799fSJohn Youn 	}
315323230efSJohn Youn }
316323230efSJohn Youn 
317f9f93cbbSJohn Youn /**
318f9f93cbbSJohn Youn  * dwc2_get_device_properties() - Read in device properties.
319f9f93cbbSJohn Youn  *
320f9f93cbbSJohn Youn  * Read in the device properties and adjust core parameters if needed.
321f9f93cbbSJohn Youn  */
322f9f93cbbSJohn Youn static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
323f9f93cbbSJohn Youn {
324f9f93cbbSJohn Youn 	struct dwc2_core_params *p = &hsotg->params;
325f9f93cbbSJohn Youn 	int num;
326f9f93cbbSJohn Youn 
327f9f93cbbSJohn Youn 	if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
328f9f93cbbSJohn Youn 	    (hsotg->dr_mode == USB_DR_MODE_OTG)) {
329f9f93cbbSJohn Youn 		device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
330f9f93cbbSJohn Youn 					 &p->g_rx_fifo_size);
331f9f93cbbSJohn Youn 
332f9f93cbbSJohn Youn 		device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
333f9f93cbbSJohn Youn 					 &p->g_np_tx_fifo_size);
334f9f93cbbSJohn Youn 
335f9f93cbbSJohn Youn 		num = device_property_read_u32_array(hsotg->dev,
336f9f93cbbSJohn Youn 						     "g-tx-fifo-size",
337f9f93cbbSJohn Youn 						     NULL, 0);
338f9f93cbbSJohn Youn 
339f9f93cbbSJohn Youn 		if (num > 0) {
340f9f93cbbSJohn Youn 			num = min(num, 15);
341f9f93cbbSJohn Youn 			memset(p->g_tx_fifo_size, 0,
342f9f93cbbSJohn Youn 			       sizeof(p->g_tx_fifo_size));
343f9f93cbbSJohn Youn 			device_property_read_u32_array(hsotg->dev,
344f9f93cbbSJohn Youn 						       "g-tx-fifo-size",
345f9f93cbbSJohn Youn 						       &p->g_tx_fifo_size[1],
346f9f93cbbSJohn Youn 						       num);
347f9f93cbbSJohn Youn 		}
348f9f93cbbSJohn Youn 	}
349f9f93cbbSJohn Youn }
350f9f93cbbSJohn Youn 
351d936e666SJohn Youn static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
352d936e666SJohn Youn {
353d936e666SJohn Youn 	int valid = 1;
354d936e666SJohn Youn 
355d936e666SJohn Youn 	switch (hsotg->params.otg_cap) {
356d936e666SJohn Youn 	case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
357d936e666SJohn Youn 		if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
358d936e666SJohn Youn 			valid = 0;
359d936e666SJohn Youn 		break;
360d936e666SJohn Youn 	case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
361d936e666SJohn Youn 		switch (hsotg->hw_params.op_mode) {
362d936e666SJohn Youn 		case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
363d936e666SJohn Youn 		case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
364d936e666SJohn Youn 		case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
365d936e666SJohn Youn 		case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
366d936e666SJohn Youn 			break;
367d936e666SJohn Youn 		default:
368d936e666SJohn Youn 			valid = 0;
369d936e666SJohn Youn 			break;
370d936e666SJohn Youn 		}
371d936e666SJohn Youn 		break;
372d936e666SJohn Youn 	case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
373d936e666SJohn Youn 		/* always valid */
374d936e666SJohn Youn 		break;
375d936e666SJohn Youn 	default:
376d936e666SJohn Youn 		valid = 0;
377d936e666SJohn Youn 		break;
378d936e666SJohn Youn 	}
379d936e666SJohn Youn 
380d936e666SJohn Youn 	if (!valid)
381d936e666SJohn Youn 		dwc2_set_param_otg_cap(hsotg);
382d936e666SJohn Youn }
383d936e666SJohn Youn 
384d936e666SJohn Youn static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
385d936e666SJohn Youn {
386d936e666SJohn Youn 	int valid = 0;
387d936e666SJohn Youn 	u32 hs_phy_type;
388d936e666SJohn Youn 	u32 fs_phy_type;
389d936e666SJohn Youn 
390d936e666SJohn Youn 	hs_phy_type = hsotg->hw_params.hs_phy_type;
391d936e666SJohn Youn 	fs_phy_type = hsotg->hw_params.fs_phy_type;
392d936e666SJohn Youn 
393d936e666SJohn Youn 	switch (hsotg->params.phy_type) {
394d936e666SJohn Youn 	case DWC2_PHY_TYPE_PARAM_FS:
395d936e666SJohn Youn 		if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
396d936e666SJohn Youn 			valid = 1;
397d936e666SJohn Youn 		break;
398d936e666SJohn Youn 	case DWC2_PHY_TYPE_PARAM_UTMI:
399d936e666SJohn Youn 		if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
400d936e666SJohn Youn 		    (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
401d936e666SJohn Youn 			valid = 1;
402d936e666SJohn Youn 		break;
403d936e666SJohn Youn 	case DWC2_PHY_TYPE_PARAM_ULPI:
404d936e666SJohn Youn 		if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
405d936e666SJohn Youn 		    (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
406d936e666SJohn Youn 			valid = 1;
407d936e666SJohn Youn 		break;
408d936e666SJohn Youn 	default:
409d936e666SJohn Youn 		break;
410d936e666SJohn Youn 	}
411d936e666SJohn Youn 
412d936e666SJohn Youn 	if (!valid)
413d936e666SJohn Youn 		dwc2_set_param_phy_type(hsotg);
414d936e666SJohn Youn }
415d936e666SJohn Youn 
416d936e666SJohn Youn static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
417d936e666SJohn Youn {
418d936e666SJohn Youn 	int valid = 1;
419d936e666SJohn Youn 	int phy_type = hsotg->params.phy_type;
420d936e666SJohn Youn 	int speed = hsotg->params.speed;
421d936e666SJohn Youn 
422d936e666SJohn Youn 	switch (speed) {
423d936e666SJohn Youn 	case DWC2_SPEED_PARAM_HIGH:
424d936e666SJohn Youn 		if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
425d936e666SJohn Youn 		    (phy_type == DWC2_PHY_TYPE_PARAM_FS))
426d936e666SJohn Youn 			valid = 0;
427d936e666SJohn Youn 		break;
428d936e666SJohn Youn 	case DWC2_SPEED_PARAM_FULL:
429d936e666SJohn Youn 	case DWC2_SPEED_PARAM_LOW:
430d936e666SJohn Youn 		break;
431d936e666SJohn Youn 	default:
432d936e666SJohn Youn 		valid = 0;
433d936e666SJohn Youn 		break;
434d936e666SJohn Youn 	}
435d936e666SJohn Youn 
436d936e666SJohn Youn 	if (!valid)
437d936e666SJohn Youn 		dwc2_set_param_speed(hsotg);
438d936e666SJohn Youn }
439d936e666SJohn Youn 
440d936e666SJohn Youn static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
441d936e666SJohn Youn {
442d936e666SJohn Youn 	int valid = 0;
443d936e666SJohn Youn 	int param = hsotg->params.phy_utmi_width;
444d936e666SJohn Youn 	int width = hsotg->hw_params.utmi_phy_data_width;
445d936e666SJohn Youn 
446d936e666SJohn Youn 	switch (width) {
447d936e666SJohn Youn 	case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
448d936e666SJohn Youn 		valid = (param == 8);
449d936e666SJohn Youn 		break;
450d936e666SJohn Youn 	case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
451d936e666SJohn Youn 		valid = (param == 16);
452d936e666SJohn Youn 		break;
453d936e666SJohn Youn 	case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
454d936e666SJohn Youn 		valid = (param == 8 || param == 16);
455d936e666SJohn Youn 		break;
456d936e666SJohn Youn 	}
457d936e666SJohn Youn 
458d936e666SJohn Youn 	if (!valid)
459d936e666SJohn Youn 		dwc2_set_param_phy_utmi_width(hsotg);
460d936e666SJohn Youn }
461d936e666SJohn Youn 
4623c6aea73SSevak Arakelyan static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
4633c6aea73SSevak Arakelyan {
4643c6aea73SSevak Arakelyan 	int fifo_count;
4653c6aea73SSevak Arakelyan 	int fifo;
4663c6aea73SSevak Arakelyan 	int min;
4673c6aea73SSevak Arakelyan 	u32 total = 0;
4683c6aea73SSevak Arakelyan 	u32 dptxfszn;
4693c6aea73SSevak Arakelyan 
4703c6aea73SSevak Arakelyan 	fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4713c6aea73SSevak Arakelyan 	min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
4723c6aea73SSevak Arakelyan 
4733c6aea73SSevak Arakelyan 	for (fifo = 1; fifo <= fifo_count; fifo++)
4743c6aea73SSevak Arakelyan 		total += hsotg->params.g_tx_fifo_size[fifo];
4753c6aea73SSevak Arakelyan 
4763c6aea73SSevak Arakelyan 	if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
4773c6aea73SSevak Arakelyan 		dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
4783c6aea73SSevak Arakelyan 			 __func__);
4793c6aea73SSevak Arakelyan 		dwc2_set_param_tx_fifo_sizes(hsotg);
4803c6aea73SSevak Arakelyan 	}
4813c6aea73SSevak Arakelyan 
4823c6aea73SSevak Arakelyan 	for (fifo = 1; fifo <= fifo_count; fifo++) {
4833c6aea73SSevak Arakelyan 		dptxfszn = (dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)) &
4843c6aea73SSevak Arakelyan 			FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
4853c6aea73SSevak Arakelyan 
4863c6aea73SSevak Arakelyan 		if (hsotg->params.g_tx_fifo_size[fifo] < min ||
4873c6aea73SSevak Arakelyan 		    hsotg->params.g_tx_fifo_size[fifo] >  dptxfszn) {
4883c6aea73SSevak Arakelyan 			dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
4893c6aea73SSevak Arakelyan 				 __func__, fifo,
4903c6aea73SSevak Arakelyan 				 hsotg->params.g_tx_fifo_size[fifo]);
4913c6aea73SSevak Arakelyan 			hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
4923c6aea73SSevak Arakelyan 		}
4933c6aea73SSevak Arakelyan 	}
4943c6aea73SSevak Arakelyan }
4953c6aea73SSevak Arakelyan 
496d936e666SJohn Youn #define CHECK_RANGE(_param, _min, _max, _def) do {			\
497d936e666SJohn Youn 		if ((hsotg->params._param) < (_min) ||			\
498d936e666SJohn Youn 		    (hsotg->params._param) > (_max)) {			\
499d936e666SJohn Youn 			dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
500d936e666SJohn Youn 				 __func__, #_param, hsotg->params._param); \
501d936e666SJohn Youn 			hsotg->params._param = (_def);			\
502d936e666SJohn Youn 		}							\
503d936e666SJohn Youn 	} while (0)
504d936e666SJohn Youn 
505d936e666SJohn Youn #define CHECK_BOOL(_param, _check) do {					\
506d936e666SJohn Youn 		if (hsotg->params._param && !(_check)) {		\
507d936e666SJohn Youn 			dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
508d936e666SJohn Youn 				 __func__, #_param, hsotg->params._param); \
509d936e666SJohn Youn 			hsotg->params._param = false;			\
510d936e666SJohn Youn 		}							\
511d936e666SJohn Youn 	} while (0)
512d936e666SJohn Youn 
513d936e666SJohn Youn static void dwc2_check_params(struct dwc2_hsotg *hsotg)
514d936e666SJohn Youn {
515d936e666SJohn Youn 	struct dwc2_hw_params *hw = &hsotg->hw_params;
516d936e666SJohn Youn 	struct dwc2_core_params *p = &hsotg->params;
517d936e666SJohn Youn 	bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
518d936e666SJohn Youn 
519d936e666SJohn Youn 	dwc2_check_param_otg_cap(hsotg);
520d936e666SJohn Youn 	dwc2_check_param_phy_type(hsotg);
521d936e666SJohn Youn 	dwc2_check_param_speed(hsotg);
522d936e666SJohn Youn 	dwc2_check_param_phy_utmi_width(hsotg);
523d936e666SJohn Youn 	CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
524d936e666SJohn Youn 	CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
525d936e666SJohn Youn 	CHECK_BOOL(i2c_enable, hw->i2c_enable);
526d936e666SJohn Youn 	CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
527d936e666SJohn Youn 	CHECK_RANGE(max_packet_count,
528d936e666SJohn Youn 		    15, hw->max_packet_count,
529d936e666SJohn Youn 		    hw->max_packet_count);
530d936e666SJohn Youn 	CHECK_RANGE(max_transfer_size,
531d936e666SJohn Youn 		    2047, hw->max_transfer_size,
532d936e666SJohn Youn 		    hw->max_transfer_size);
533d936e666SJohn Youn 
534d936e666SJohn Youn 	if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
535d936e666SJohn Youn 	    (hsotg->dr_mode == USB_DR_MODE_OTG)) {
536d936e666SJohn Youn 		CHECK_BOOL(host_dma, dma_capable);
537d936e666SJohn Youn 		CHECK_BOOL(dma_desc_enable, p->host_dma);
538d936e666SJohn Youn 		CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
539d936e666SJohn Youn 		CHECK_BOOL(host_ls_low_power_phy_clk,
540d936e666SJohn Youn 			   p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
541d936e666SJohn Youn 		CHECK_RANGE(host_channels,
542d936e666SJohn Youn 			    1, hw->host_channels,
543d936e666SJohn Youn 			    hw->host_channels);
544d936e666SJohn Youn 		CHECK_RANGE(host_rx_fifo_size,
545d936e666SJohn Youn 			    16, hw->rx_fifo_size,
546d936e666SJohn Youn 			    hw->rx_fifo_size);
547d936e666SJohn Youn 		CHECK_RANGE(host_nperio_tx_fifo_size,
548d936e666SJohn Youn 			    16, hw->host_nperio_tx_fifo_size,
549d936e666SJohn Youn 			    hw->host_nperio_tx_fifo_size);
550d936e666SJohn Youn 		CHECK_RANGE(host_perio_tx_fifo_size,
551d936e666SJohn Youn 			    16, hw->host_perio_tx_fifo_size,
552d936e666SJohn Youn 			    hw->host_perio_tx_fifo_size);
553d936e666SJohn Youn 	}
554d936e666SJohn Youn 
555d936e666SJohn Youn 	if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
556d936e666SJohn Youn 	    (hsotg->dr_mode == USB_DR_MODE_OTG)) {
557d936e666SJohn Youn 		CHECK_BOOL(g_dma, dma_capable);
558d936e666SJohn Youn 		CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
559d936e666SJohn Youn 		CHECK_RANGE(g_rx_fifo_size,
560d936e666SJohn Youn 			    16, hw->rx_fifo_size,
561d936e666SJohn Youn 			    hw->rx_fifo_size);
562d936e666SJohn Youn 		CHECK_RANGE(g_np_tx_fifo_size,
563d936e666SJohn Youn 			    16, hw->dev_nperio_tx_fifo_size,
564d936e666SJohn Youn 			    hw->dev_nperio_tx_fifo_size);
5653c6aea73SSevak Arakelyan 		dwc2_check_param_tx_fifo_sizes(hsotg);
566d936e666SJohn Youn 	}
567d936e666SJohn Youn }
568d936e666SJohn Youn 
569323230efSJohn Youn /*
570323230efSJohn Youn  * Gets host hardware parameters. Forces host mode if not currently in
571323230efSJohn Youn  * host mode. Should be called immediately after a core soft reset in
572323230efSJohn Youn  * order to get the reset values.
573323230efSJohn Youn  */
574323230efSJohn Youn static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
575323230efSJohn Youn {
576323230efSJohn Youn 	struct dwc2_hw_params *hw = &hsotg->hw_params;
577323230efSJohn Youn 	u32 gnptxfsiz;
578323230efSJohn Youn 	u32 hptxfsiz;
579323230efSJohn Youn 	bool forced;
580323230efSJohn Youn 
581323230efSJohn Youn 	if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
582323230efSJohn Youn 		return;
583323230efSJohn Youn 
584323230efSJohn Youn 	forced = dwc2_force_mode_if_needed(hsotg, true);
585323230efSJohn Youn 
586323230efSJohn Youn 	gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
587323230efSJohn Youn 	hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
588323230efSJohn Youn 
589323230efSJohn Youn 	if (forced)
590323230efSJohn Youn 		dwc2_clear_force_mode(hsotg);
591323230efSJohn Youn 
592323230efSJohn Youn 	hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
593323230efSJohn Youn 				       FIFOSIZE_DEPTH_SHIFT;
594323230efSJohn Youn 	hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
595323230efSJohn Youn 				      FIFOSIZE_DEPTH_SHIFT;
596323230efSJohn Youn }
597323230efSJohn Youn 
598323230efSJohn Youn /*
599323230efSJohn Youn  * Gets device hardware parameters. Forces device mode if not
600323230efSJohn Youn  * currently in device mode. Should be called immediately after a core
601323230efSJohn Youn  * soft reset in order to get the reset values.
602323230efSJohn Youn  */
603323230efSJohn Youn static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
604323230efSJohn Youn {
605323230efSJohn Youn 	struct dwc2_hw_params *hw = &hsotg->hw_params;
606323230efSJohn Youn 	bool forced;
607323230efSJohn Youn 	u32 gnptxfsiz;
608323230efSJohn Youn 
609323230efSJohn Youn 	if (hsotg->dr_mode == USB_DR_MODE_HOST)
610323230efSJohn Youn 		return;
611323230efSJohn Youn 
612323230efSJohn Youn 	forced = dwc2_force_mode_if_needed(hsotg, false);
613323230efSJohn Youn 
614323230efSJohn Youn 	gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
615323230efSJohn Youn 
616323230efSJohn Youn 	if (forced)
617323230efSJohn Youn 		dwc2_clear_force_mode(hsotg);
618323230efSJohn Youn 
619323230efSJohn Youn 	hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
620323230efSJohn Youn 				       FIFOSIZE_DEPTH_SHIFT;
621323230efSJohn Youn }
622323230efSJohn Youn 
623323230efSJohn Youn /**
624323230efSJohn Youn  * During device initialization, read various hardware configuration
625323230efSJohn Youn  * registers and interpret the contents.
626323230efSJohn Youn  */
627323230efSJohn Youn int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
628323230efSJohn Youn {
629323230efSJohn Youn 	struct dwc2_hw_params *hw = &hsotg->hw_params;
630323230efSJohn Youn 	unsigned int width;
631323230efSJohn Youn 	u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
632323230efSJohn Youn 	u32 grxfsiz;
633323230efSJohn Youn 
634323230efSJohn Youn 	/*
635323230efSJohn Youn 	 * Attempt to ensure this device is really a DWC_otg Controller.
636323230efSJohn Youn 	 * Read and verify the GSNPSID register contents. The value should be
637323230efSJohn Youn 	 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
638323230efSJohn Youn 	 * as in "OTG version 2.xx" or "OTG version 3.xx".
639323230efSJohn Youn 	 */
640323230efSJohn Youn 	hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
641323230efSJohn Youn 	if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
6421e6b98ebSVardan Mikayelyan 	    (hw->snpsid & 0xfffff000) != 0x4f543000 &&
6431e6b98ebSVardan Mikayelyan 	    (hw->snpsid & 0xffff0000) != 0x55310000 &&
6441e6b98ebSVardan Mikayelyan 	    (hw->snpsid & 0xffff0000) != 0x55320000) {
645323230efSJohn Youn 		dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
646323230efSJohn Youn 			hw->snpsid);
647323230efSJohn Youn 		return -ENODEV;
648323230efSJohn Youn 	}
649323230efSJohn Youn 
650323230efSJohn Youn 	dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
651323230efSJohn Youn 		hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
652323230efSJohn Youn 		hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
653323230efSJohn Youn 
654323230efSJohn Youn 	hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
655323230efSJohn Youn 	hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
656323230efSJohn Youn 	hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
657323230efSJohn Youn 	hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
658323230efSJohn Youn 	grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
659323230efSJohn Youn 
660323230efSJohn Youn 	/*
661323230efSJohn Youn 	 * Host specific hardware parameters. Reading these parameters
662323230efSJohn Youn 	 * requires the controller to be in host mode. The mode will
663323230efSJohn Youn 	 * be forced, if necessary, to read these values.
664323230efSJohn Youn 	 */
665323230efSJohn Youn 	dwc2_get_host_hwparams(hsotg);
666323230efSJohn Youn 	dwc2_get_dev_hwparams(hsotg);
667323230efSJohn Youn 
668323230efSJohn Youn 	/* hwcfg1 */
669323230efSJohn Youn 	hw->dev_ep_dirs = hwcfg1;
670323230efSJohn Youn 
671323230efSJohn Youn 	/* hwcfg2 */
672323230efSJohn Youn 	hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
673323230efSJohn Youn 		      GHWCFG2_OP_MODE_SHIFT;
674323230efSJohn Youn 	hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
675323230efSJohn Youn 		   GHWCFG2_ARCHITECTURE_SHIFT;
676323230efSJohn Youn 	hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
677323230efSJohn Youn 	hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
678323230efSJohn Youn 				GHWCFG2_NUM_HOST_CHAN_SHIFT);
679323230efSJohn Youn 	hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
680323230efSJohn Youn 			  GHWCFG2_HS_PHY_TYPE_SHIFT;
681323230efSJohn Youn 	hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
682323230efSJohn Youn 			  GHWCFG2_FS_PHY_TYPE_SHIFT;
683323230efSJohn Youn 	hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
684323230efSJohn Youn 			 GHWCFG2_NUM_DEV_EP_SHIFT;
685323230efSJohn Youn 	hw->nperio_tx_q_depth =
686323230efSJohn Youn 		(hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
687323230efSJohn Youn 		GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
688323230efSJohn Youn 	hw->host_perio_tx_q_depth =
689323230efSJohn Youn 		(hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
690323230efSJohn Youn 		GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
691323230efSJohn Youn 	hw->dev_token_q_depth =
692323230efSJohn Youn 		(hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
693323230efSJohn Youn 		GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
694323230efSJohn Youn 
695323230efSJohn Youn 	/* hwcfg3 */
696323230efSJohn Youn 	width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
697323230efSJohn Youn 		GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
698323230efSJohn Youn 	hw->max_transfer_size = (1 << (width + 11)) - 1;
699323230efSJohn Youn 	width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
700323230efSJohn Youn 		GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
701323230efSJohn Youn 	hw->max_packet_count = (1 << (width + 4)) - 1;
702323230efSJohn Youn 	hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
703323230efSJohn Youn 	hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
704323230efSJohn Youn 			      GHWCFG3_DFIFO_DEPTH_SHIFT;
705323230efSJohn Youn 
706323230efSJohn Youn 	/* hwcfg4 */
707323230efSJohn Youn 	hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
708323230efSJohn Youn 	hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
709323230efSJohn Youn 				  GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
710323230efSJohn Youn 	hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
711323230efSJohn Youn 	hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
712323230efSJohn Youn 	hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
713323230efSJohn Youn 				  GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
714323230efSJohn Youn 
715323230efSJohn Youn 	/* fifo sizes */
716d1531319SJohn Youn 	hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
717323230efSJohn Youn 				GRXFSIZ_DEPTH_SHIFT;
718323230efSJohn Youn 
719323230efSJohn Youn 	return 0;
720323230efSJohn Youn }
721323230efSJohn Youn 
722334bbd4eSJohn Youn int dwc2_init_params(struct dwc2_hsotg *hsotg)
723334bbd4eSJohn Youn {
7247de1debcSJohn Youn 	const struct of_device_id *match;
7257de1debcSJohn Youn 	void (*set_params)(void *data);
7267de1debcSJohn Youn 
727245977c9SJohn Youn 	dwc2_set_default_params(hsotg);
728f9f93cbbSJohn Youn 	dwc2_get_device_properties(hsotg);
729334bbd4eSJohn Youn 
7307de1debcSJohn Youn 	match = of_match_device(dwc2_of_match_table, hsotg->dev);
7317de1debcSJohn Youn 	if (match && match->data) {
7327de1debcSJohn Youn 		set_params = match->data;
7337de1debcSJohn Youn 		set_params(hsotg);
7347de1debcSJohn Youn 	}
7357de1debcSJohn Youn 
736d936e666SJohn Youn 	dwc2_check_params(hsotg);
737d936e666SJohn Youn 
738334bbd4eSJohn Youn 	return 0;
739334bbd4eSJohn Youn }
740