1dd11376bSBart Van Assche // SPDX-License-Identifier: GPL-2.0-only
2dd11376bSBart Van Assche /*
3dd11376bSBart Van Assche * UFS Host Controller driver for Exynos specific extensions
4dd11376bSBart Van Assche *
5dd11376bSBart Van Assche * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
6dd11376bSBart Van Assche * Author: Seungwon Jeon <essuuj@gmail.com>
7dd11376bSBart Van Assche * Author: Alim Akhtar <alim.akhtar@samsung.com>
8dd11376bSBart Van Assche *
9dd11376bSBart Van Assche */
10dd11376bSBart Van Assche
11dd11376bSBart Van Assche #include <linux/clk.h>
12dd11376bSBart Van Assche #include <linux/delay.h>
13dd11376bSBart Van Assche #include <linux/module.h>
14dd11376bSBart Van Assche #include <linux/of.h>
15dd11376bSBart Van Assche #include <linux/of_address.h>
16dd11376bSBart Van Assche #include <linux/mfd/syscon.h>
17dd11376bSBart Van Assche #include <linux/phy/phy.h>
18dd11376bSBart Van Assche #include <linux/platform_device.h>
19dd11376bSBart Van Assche #include <linux/regmap.h>
20dd11376bSBart Van Assche
21dd11376bSBart Van Assche #include <ufs/ufshcd.h>
22dd11376bSBart Van Assche #include "ufshcd-pltfrm.h"
23dd11376bSBart Van Assche #include <ufs/ufshci.h>
24dd11376bSBart Van Assche #include <ufs/unipro.h>
25dd11376bSBart Van Assche
26dd11376bSBart Van Assche #include "ufs-exynos.h"
27dd11376bSBart Van Assche
28dd11376bSBart Van Assche /*
29dd11376bSBart Van Assche * Exynos's Vendor specific registers for UFSHCI
30dd11376bSBart Van Assche */
31dd11376bSBart Van Assche #define HCI_TXPRDT_ENTRY_SIZE 0x00
32dd11376bSBart Van Assche #define PRDT_PREFECT_EN BIT(31)
33dd11376bSBart Van Assche #define PRDT_SET_SIZE(x) ((x) & 0x1F)
34dd11376bSBart Van Assche #define HCI_RXPRDT_ENTRY_SIZE 0x04
35dd11376bSBart Van Assche #define HCI_1US_TO_CNT_VAL 0x0C
36dd11376bSBart Van Assche #define CNT_VAL_1US_MASK 0x3FF
37dd11376bSBart Van Assche #define HCI_UTRL_NEXUS_TYPE 0x40
38dd11376bSBart Van Assche #define HCI_UTMRL_NEXUS_TYPE 0x44
39dd11376bSBart Van Assche #define HCI_SW_RST 0x50
40dd11376bSBart Van Assche #define UFS_LINK_SW_RST BIT(0)
41dd11376bSBart Van Assche #define UFS_UNIPRO_SW_RST BIT(1)
42dd11376bSBart Van Assche #define UFS_SW_RST_MASK (UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST)
43dd11376bSBart Van Assche #define HCI_DATA_REORDER 0x60
44dd11376bSBart Van Assche #define HCI_UNIPRO_APB_CLK_CTRL 0x68
45dd11376bSBart Van Assche #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF))
46dd11376bSBart Van Assche #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C
47dd11376bSBart Van Assche #define HCI_GPIO_OUT 0x70
48dd11376bSBart Van Assche #define HCI_ERR_EN_PA_LAYER 0x78
49dd11376bSBart Van Assche #define HCI_ERR_EN_DL_LAYER 0x7C
50dd11376bSBart Van Assche #define HCI_ERR_EN_N_LAYER 0x80
51dd11376bSBart Van Assche #define HCI_ERR_EN_T_LAYER 0x84
52dd11376bSBart Van Assche #define HCI_ERR_EN_DME_LAYER 0x88
53dd11376bSBart Van Assche #define HCI_CLKSTOP_CTRL 0xB0
54dd11376bSBart Van Assche #define REFCLKOUT_STOP BIT(4)
55daa782a5SAlim Akhtar #define MPHY_APBCLK_STOP BIT(3)
56dd11376bSBart Van Assche #define REFCLK_STOP BIT(2)
57dd11376bSBart Van Assche #define UNIPRO_MCLK_STOP BIT(1)
58dd11376bSBart Van Assche #define UNIPRO_PCLK_STOP BIT(0)
59dd11376bSBart Van Assche #define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\
60daa782a5SAlim Akhtar UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
61dd11376bSBart Van Assche UNIPRO_PCLK_STOP)
62dd11376bSBart Van Assche #define HCI_MISC 0xB4
63dd11376bSBart Van Assche #define REFCLK_CTRL_EN BIT(7)
64dd11376bSBart Van Assche #define UNIPRO_PCLK_CTRL_EN BIT(6)
65dd11376bSBart Van Assche #define UNIPRO_MCLK_CTRL_EN BIT(5)
66dd11376bSBart Van Assche #define HCI_CORECLK_CTRL_EN BIT(4)
67dd11376bSBart Van Assche #define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\
68dd11376bSBart Van Assche UNIPRO_PCLK_CTRL_EN |\
69dd11376bSBart Van Assche UNIPRO_MCLK_CTRL_EN)
70dd11376bSBart Van Assche /* Device fatal error */
71dd11376bSBart Van Assche #define DFES_ERR_EN BIT(31)
72dd11376bSBart Van Assche #define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\
73dd11376bSBart Van Assche UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
74dd11376bSBart Van Assche #define DFES_DEF_L3_ERRS (UIC_NETWORK_UNSUPPORTED_HEADER_TYPE |\
75dd11376bSBart Van Assche UIC_NETWORK_BAD_DEVICEID_ENC |\
76dd11376bSBart Van Assche UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING)
77dd11376bSBart Van Assche #define DFES_DEF_L4_ERRS (UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE |\
78dd11376bSBart Van Assche UIC_TRANSPORT_UNKNOWN_CPORTID |\
79dd11376bSBart Van Assche UIC_TRANSPORT_NO_CONNECTION_RX |\
80dd11376bSBart Van Assche UIC_TRANSPORT_BAD_TC)
81dd11376bSBart Van Assche
82dd11376bSBart Van Assche /* FSYS UFS Shareability */
83dd11376bSBart Van Assche #define UFS_WR_SHARABLE BIT(2)
84dd11376bSBart Van Assche #define UFS_RD_SHARABLE BIT(1)
85dd11376bSBart Van Assche #define UFS_SHARABLE (UFS_WR_SHARABLE | UFS_RD_SHARABLE)
86dd11376bSBart Van Assche #define UFS_SHAREABILITY_OFFSET 0x710
87dd11376bSBart Van Assche
88dd11376bSBart Van Assche /* Multi-host registers */
89dd11376bSBart Van Assche #define MHCTRL 0xC4
90dd11376bSBart Van Assche #define MHCTRL_EN_VH_MASK (0xE)
91dd11376bSBart Van Assche #define MHCTRL_EN_VH(vh) (vh << 1)
92dd11376bSBart Van Assche #define PH2VH_MBOX 0xD8
93dd11376bSBart Van Assche
94dd11376bSBart Van Assche #define MH_MSG_MASK (0xFF)
95dd11376bSBart Van Assche
96dd11376bSBart Van Assche #define MH_MSG(id, msg) ((id << 8) | (msg & 0xFF))
97dd11376bSBart Van Assche #define MH_MSG_PH_READY 0x1
98dd11376bSBart Van Assche #define MH_MSG_VH_READY 0x2
99dd11376bSBart Van Assche
100dd11376bSBart Van Assche #define ALLOW_INQUIRY BIT(25)
101dd11376bSBart Van Assche #define ALLOW_MODE_SELECT BIT(24)
102dd11376bSBart Van Assche #define ALLOW_MODE_SENSE BIT(23)
103dd11376bSBart Van Assche #define ALLOW_PRE_FETCH GENMASK(22, 21)
104dd11376bSBart Van Assche #define ALLOW_READ_CMD_ALL GENMASK(20, 18) /* read_6/10/16 */
105dd11376bSBart Van Assche #define ALLOW_READ_BUFFER BIT(17)
106dd11376bSBart Van Assche #define ALLOW_READ_CAPACITY GENMASK(16, 15)
107dd11376bSBart Van Assche #define ALLOW_REPORT_LUNS BIT(14)
108dd11376bSBart Van Assche #define ALLOW_REQUEST_SENSE BIT(13)
109dd11376bSBart Van Assche #define ALLOW_SYNCHRONIZE_CACHE GENMASK(8, 7)
110dd11376bSBart Van Assche #define ALLOW_TEST_UNIT_READY BIT(6)
111dd11376bSBart Van Assche #define ALLOW_UNMAP BIT(5)
112dd11376bSBart Van Assche #define ALLOW_VERIFY BIT(4)
113dd11376bSBart Van Assche #define ALLOW_WRITE_CMD_ALL GENMASK(3, 1) /* write_6/10/16 */
114dd11376bSBart Van Assche
115dd11376bSBart Van Assche #define ALLOW_TRANS_VH_DEFAULT (ALLOW_INQUIRY | ALLOW_MODE_SELECT | \
116dd11376bSBart Van Assche ALLOW_MODE_SENSE | ALLOW_PRE_FETCH | \
117dd11376bSBart Van Assche ALLOW_READ_CMD_ALL | ALLOW_READ_BUFFER | \
118dd11376bSBart Van Assche ALLOW_READ_CAPACITY | ALLOW_REPORT_LUNS | \
119dd11376bSBart Van Assche ALLOW_REQUEST_SENSE | ALLOW_SYNCHRONIZE_CACHE | \
120dd11376bSBart Van Assche ALLOW_TEST_UNIT_READY | ALLOW_UNMAP | \
121dd11376bSBart Van Assche ALLOW_VERIFY | ALLOW_WRITE_CMD_ALL)
122dd11376bSBart Van Assche
123dd11376bSBart Van Assche #define HCI_MH_ALLOWABLE_TRAN_OF_VH 0x30C
124dd11376bSBart Van Assche #define HCI_MH_IID_IN_TASK_TAG 0X308
125dd11376bSBart Van Assche
126dd11376bSBart Van Assche #define PH_READY_TIMEOUT_MS (5 * MSEC_PER_SEC)
127dd11376bSBart Van Assche
128dd11376bSBart Van Assche enum {
129dd11376bSBart Van Assche UNIPRO_L1_5 = 0,/* PHY Adapter */
130dd11376bSBart Van Assche UNIPRO_L2, /* Data Link */
131dd11376bSBart Van Assche UNIPRO_L3, /* Network */
132dd11376bSBart Van Assche UNIPRO_L4, /* Transport */
133dd11376bSBart Van Assche UNIPRO_DME, /* DME */
134dd11376bSBart Van Assche };
135dd11376bSBart Van Assche
136dd11376bSBart Van Assche /*
137dd11376bSBart Van Assche * UNIPRO registers
138dd11376bSBart Van Assche */
139216f74e8SAlim Akhtar #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8
140216f74e8SAlim Akhtar #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC
141216f74e8SAlim Akhtar #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0
142216f74e8SAlim Akhtar
143dd11376bSBart Van Assche /*
144dd11376bSBart Van Assche * UFS Protector registers
145dd11376bSBart Van Assche */
146dd11376bSBart Van Assche #define UFSPRSECURITY 0x010
147dd11376bSBart Van Assche #define NSSMU BIT(14)
148dd11376bSBart Van Assche #define UFSPSBEGIN0 0x200
149dd11376bSBart Van Assche #define UFSPSEND0 0x204
150dd11376bSBart Van Assche #define UFSPSLUN0 0x208
151dd11376bSBart Van Assche #define UFSPSCTRL0 0x20C
152dd11376bSBart Van Assche
153dd11376bSBart Van Assche #define CNTR_DIV_VAL 40
154dd11376bSBart Van Assche
155dd11376bSBart Van Assche static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en);
156dd11376bSBart Van Assche static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en);
157dd11376bSBart Van Assche
exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs * ufs)158dd11376bSBart Van Assche static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs)
159dd11376bSBart Van Assche {
160dd11376bSBart Van Assche exynos_ufs_auto_ctrl_hcc(ufs, true);
161dd11376bSBart Van Assche }
162dd11376bSBart Van Assche
exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs * ufs)163dd11376bSBart Van Assche static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs)
164dd11376bSBart Van Assche {
165dd11376bSBart Van Assche exynos_ufs_auto_ctrl_hcc(ufs, false);
166dd11376bSBart Van Assche }
167dd11376bSBart Van Assche
exynos_ufs_disable_auto_ctrl_hcc_save(struct exynos_ufs * ufs,u32 * val)168dd11376bSBart Van Assche static inline void exynos_ufs_disable_auto_ctrl_hcc_save(
169dd11376bSBart Van Assche struct exynos_ufs *ufs, u32 *val)
170dd11376bSBart Van Assche {
171dd11376bSBart Van Assche *val = hci_readl(ufs, HCI_MISC);
172dd11376bSBart Van Assche exynos_ufs_auto_ctrl_hcc(ufs, false);
173dd11376bSBart Van Assche }
174dd11376bSBart Van Assche
exynos_ufs_auto_ctrl_hcc_restore(struct exynos_ufs * ufs,u32 * val)175dd11376bSBart Van Assche static inline void exynos_ufs_auto_ctrl_hcc_restore(
176dd11376bSBart Van Assche struct exynos_ufs *ufs, u32 *val)
177dd11376bSBart Van Assche {
178dd11376bSBart Van Assche hci_writel(ufs, *val, HCI_MISC);
179dd11376bSBart Van Assche }
180dd11376bSBart Van Assche
exynos_ufs_gate_clks(struct exynos_ufs * ufs)181dd11376bSBart Van Assche static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs)
182dd11376bSBart Van Assche {
183dd11376bSBart Van Assche exynos_ufs_ctrl_clkstop(ufs, true);
184dd11376bSBart Van Assche }
185dd11376bSBart Van Assche
exynos_ufs_ungate_clks(struct exynos_ufs * ufs)186dd11376bSBart Van Assche static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs)
187dd11376bSBart Van Assche {
188dd11376bSBart Van Assche exynos_ufs_ctrl_clkstop(ufs, false);
189dd11376bSBart Van Assche }
190dd11376bSBart Van Assche
exynos7_ufs_drv_init(struct device * dev,struct exynos_ufs * ufs)191dd11376bSBart Van Assche static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
192dd11376bSBart Van Assche {
193dd11376bSBart Van Assche return 0;
194dd11376bSBart Van Assche }
195dd11376bSBart Van Assche
exynosauto_ufs_drv_init(struct device * dev,struct exynos_ufs * ufs)196dd11376bSBart Van Assche static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
197dd11376bSBart Van Assche {
198dd11376bSBart Van Assche struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
199dd11376bSBart Van Assche
200dd11376bSBart Van Assche /* IO Coherency setting */
201dd11376bSBart Van Assche if (ufs->sysreg) {
202dd11376bSBart Van Assche return regmap_update_bits(ufs->sysreg,
203dd11376bSBart Van Assche ufs->shareability_reg_offset,
204dd11376bSBart Van Assche UFS_SHARABLE, UFS_SHARABLE);
205dd11376bSBart Van Assche }
206dd11376bSBart Van Assche
207dd11376bSBart Van Assche attr->tx_dif_p_nsec = 3200000;
208dd11376bSBart Van Assche
209dd11376bSBart Van Assche return 0;
210dd11376bSBart Van Assche }
211dd11376bSBart Van Assche
exynosauto_ufs_post_hce_enable(struct exynos_ufs * ufs)212dd11376bSBart Van Assche static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs)
213dd11376bSBart Van Assche {
214dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
215dd11376bSBart Van Assche
216dd11376bSBart Van Assche /* Enable Virtual Host #1 */
217dd11376bSBart Van Assche ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL);
218dd11376bSBart Van Assche /* Default VH Transfer permissions */
219dd11376bSBart Van Assche hci_writel(ufs, ALLOW_TRANS_VH_DEFAULT, HCI_MH_ALLOWABLE_TRAN_OF_VH);
220dd11376bSBart Van Assche /* IID information is replaced in TASKTAG[7:5] instead of IID in UCD */
221dd11376bSBart Van Assche hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG);
222dd11376bSBart Van Assche
223dd11376bSBart Van Assche return 0;
224dd11376bSBart Van Assche }
225dd11376bSBart Van Assche
exynosauto_ufs_pre_link(struct exynos_ufs * ufs)226dd11376bSBart Van Assche static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs)
227dd11376bSBart Van Assche {
228dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
229dd11376bSBart Van Assche int i;
230dd11376bSBart Van Assche u32 tx_line_reset_period, rx_line_reset_period;
231dd11376bSBart Van Assche
232dd11376bSBart Van Assche rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC;
233dd11376bSBart Van Assche tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC;
234dd11376bSBart Van Assche
235dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
236dd11376bSBart Van Assche for_each_ufs_rx_lane(ufs, i) {
237dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i),
238dd11376bSBart Van Assche DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
239dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0);
240dd11376bSBart Van Assche
241dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i),
242dd11376bSBart Van Assche (rx_line_reset_period >> 16) & 0xFF);
243dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i),
244dd11376bSBart Van Assche (rx_line_reset_period >> 8) & 0xFF);
245dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i),
246dd11376bSBart Van Assche (rx_line_reset_period) & 0xFF);
247dd11376bSBart Van Assche
248dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79);
249dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
250dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
251dd11376bSBart Van Assche }
252dd11376bSBart Van Assche
253dd11376bSBart Van Assche for_each_ufs_tx_lane(ufs, i) {
254dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i),
255dd11376bSBart Van Assche DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
256dd11376bSBart Van Assche /* Not to affect VND_TX_LINERESET_PVALUE to VND_TX_CLK_PRD */
257dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i),
258dd11376bSBart Van Assche 0x02);
259dd11376bSBart Van Assche
260dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i),
261dd11376bSBart Van Assche (tx_line_reset_period >> 16) & 0xFF);
262dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i),
263dd11376bSBart Van Assche (tx_line_reset_period >> 8) & 0xFF);
264dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i),
265dd11376bSBart Van Assche (tx_line_reset_period) & 0xFF);
266dd11376bSBart Van Assche
267dd11376bSBart Van Assche /* TX PWM Gear Capability / PWM_G1_ONLY */
268dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1);
269dd11376bSBart Van Assche }
270dd11376bSBart Van Assche
271dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
272dd11376bSBart Van Assche
273dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
274dd11376bSBart Van Assche
275dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000);
276dd11376bSBart Van Assche
277dd11376bSBart Van Assche return 0;
278dd11376bSBart Van Assche }
279dd11376bSBart Van Assche
exynosauto_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)280dd11376bSBart Van Assche static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
281dd11376bSBart Van Assche struct ufs_pa_layer_attr *pwr)
282dd11376bSBart Van Assche {
283dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
284dd11376bSBart Van Assche
285dd11376bSBart Van Assche /* PACP_PWR_req and delivered to the remote DME */
286dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
287dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
288dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
289dd11376bSBart Van Assche
290dd11376bSBart Van Assche return 0;
291dd11376bSBart Van Assche }
292dd11376bSBart Van Assche
exynosauto_ufs_post_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)293dd11376bSBart Van Assche static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs,
294dd11376bSBart Van Assche struct ufs_pa_layer_attr *pwr)
295dd11376bSBart Van Assche {
296dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
297dd11376bSBart Van Assche u32 enabled_vh;
298dd11376bSBart Van Assche
299dd11376bSBart Van Assche enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK;
300dd11376bSBart Van Assche
301dd11376bSBart Van Assche /* Send physical host ready message to virtual hosts */
302dd11376bSBart Van Assche ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX);
303dd11376bSBart Van Assche
304dd11376bSBart Van Assche return 0;
305dd11376bSBart Van Assche }
306dd11376bSBart Van Assche
exynos7_ufs_pre_link(struct exynos_ufs * ufs)307dd11376bSBart Van Assche static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
308dd11376bSBart Van Assche {
309dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
310dd11376bSBart Van Assche u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
311dd11376bSBart Van Assche int i;
312dd11376bSBart Van Assche
313dd11376bSBart Van Assche exynos_ufs_enable_ov_tm(hba);
314dd11376bSBart Van Assche for_each_ufs_tx_lane(ufs, i)
315dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
316dd11376bSBart Van Assche for_each_ufs_rx_lane(ufs, i) {
317dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
318dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
319dd11376bSBart Van Assche }
320dd11376bSBart Van Assche exynos_ufs_disable_ov_tm(hba);
321dd11376bSBart Van Assche
322dd11376bSBart Van Assche for_each_ufs_tx_lane(ufs, i)
323dd11376bSBart Van Assche ufshcd_dme_set(hba,
324dd11376bSBart Van Assche UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
325dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
326dd11376bSBart Van Assche udelay(1);
327dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
328dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
329dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
330dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
331dd11376bSBart Van Assche udelay(1600);
332dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
333dd11376bSBart Van Assche
334dd11376bSBart Van Assche return 0;
335dd11376bSBart Van Assche }
336dd11376bSBart Van Assche
exynos7_ufs_post_link(struct exynos_ufs * ufs)337dd11376bSBart Van Assche static int exynos7_ufs_post_link(struct exynos_ufs *ufs)
338dd11376bSBart Van Assche {
339dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
340dd11376bSBart Van Assche int i;
341dd11376bSBart Van Assche
342dd11376bSBart Van Assche exynos_ufs_enable_ov_tm(hba);
343dd11376bSBart Van Assche for_each_ufs_tx_lane(ufs, i) {
344dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83);
345dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07);
346dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i),
347dd11376bSBart Van Assche TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000)));
348dd11376bSBart Van Assche }
349dd11376bSBart Van Assche exynos_ufs_disable_ov_tm(hba);
350dd11376bSBart Van Assche
351dd11376bSBart Van Assche exynos_ufs_enable_dbg_mode(hba);
352dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8);
353dd11376bSBart Van Assche exynos_ufs_disable_dbg_mode(hba);
354dd11376bSBart Van Assche
355dd11376bSBart Van Assche return 0;
356dd11376bSBart Van Assche }
357dd11376bSBart Van Assche
exynos7_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)358dd11376bSBart Van Assche static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs,
359dd11376bSBart Van Assche struct ufs_pa_layer_attr *pwr)
360dd11376bSBart Van Assche {
361dd11376bSBart Van Assche unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE);
362dd11376bSBart Van Assche
363dd11376bSBart Van Assche return 0;
364dd11376bSBart Van Assche }
365dd11376bSBart Van Assche
exynos7_ufs_post_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)366dd11376bSBart Van Assche static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs,
367dd11376bSBart Van Assche struct ufs_pa_layer_attr *pwr)
368dd11376bSBart Van Assche {
369dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
370dd11376bSBart Van Assche int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx);
371dd11376bSBart Van Assche
372dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1);
373dd11376bSBart Van Assche
374dd11376bSBart Van Assche if (lanes == 1) {
375dd11376bSBart Van Assche exynos_ufs_enable_dbg_mode(hba);
376dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1);
377dd11376bSBart Van Assche exynos_ufs_disable_dbg_mode(hba);
378dd11376bSBart Van Assche }
379dd11376bSBart Van Assche
380dd11376bSBart Van Assche return 0;
381dd11376bSBart Van Assche }
382dd11376bSBart Van Assche
383dd11376bSBart Van Assche /*
384dd11376bSBart Van Assche * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
385dd11376bSBart Van Assche * Control should be disabled in the below cases
386dd11376bSBart Van Assche * - Before host controller S/W reset
387dd11376bSBart Van Assche * - Access to UFS protector's register
388dd11376bSBart Van Assche */
exynos_ufs_auto_ctrl_hcc(struct exynos_ufs * ufs,bool en)389dd11376bSBart Van Assche static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en)
390dd11376bSBart Van Assche {
391dd11376bSBart Van Assche u32 misc = hci_readl(ufs, HCI_MISC);
392dd11376bSBart Van Assche
393dd11376bSBart Van Assche if (en)
394dd11376bSBart Van Assche hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC);
395dd11376bSBart Van Assche else
396dd11376bSBart Van Assche hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC);
397dd11376bSBart Van Assche }
398dd11376bSBart Van Assche
exynos_ufs_ctrl_clkstop(struct exynos_ufs * ufs,bool en)399dd11376bSBart Van Assche static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en)
400dd11376bSBart Van Assche {
401dd11376bSBart Van Assche u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL);
402dd11376bSBart Van Assche u32 misc = hci_readl(ufs, HCI_MISC);
403dd11376bSBart Van Assche
404dd11376bSBart Van Assche if (en) {
405dd11376bSBart Van Assche hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC);
406dd11376bSBart Van Assche hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
407dd11376bSBart Van Assche } else {
408dd11376bSBart Van Assche hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
409dd11376bSBart Van Assche hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC);
410dd11376bSBart Van Assche }
411dd11376bSBart Van Assche }
412dd11376bSBart Van Assche
exynos_ufs_get_clk_info(struct exynos_ufs * ufs)413dd11376bSBart Van Assche static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs)
414dd11376bSBart Van Assche {
415dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
416dd11376bSBart Van Assche struct list_head *head = &hba->clk_list_head;
417dd11376bSBart Van Assche struct ufs_clk_info *clki;
418dd11376bSBart Van Assche unsigned long pclk_rate;
419dd11376bSBart Van Assche u32 f_min, f_max;
420dd11376bSBart Van Assche u8 div = 0;
421dd11376bSBart Van Assche int ret = 0;
422dd11376bSBart Van Assche
423dd11376bSBart Van Assche if (list_empty(head))
424dd11376bSBart Van Assche goto out;
425dd11376bSBart Van Assche
426dd11376bSBart Van Assche list_for_each_entry(clki, head, list) {
427dd11376bSBart Van Assche if (!IS_ERR(clki->clk)) {
428dd11376bSBart Van Assche if (!strcmp(clki->name, "core_clk"))
429dd11376bSBart Van Assche ufs->clk_hci_core = clki->clk;
430dd11376bSBart Van Assche else if (!strcmp(clki->name, "sclk_unipro_main"))
431dd11376bSBart Van Assche ufs->clk_unipro_main = clki->clk;
432dd11376bSBart Van Assche }
433dd11376bSBart Van Assche }
434dd11376bSBart Van Assche
435dd11376bSBart Van Assche if (!ufs->clk_hci_core || !ufs->clk_unipro_main) {
436dd11376bSBart Van Assche dev_err(hba->dev, "failed to get clk info\n");
437dd11376bSBart Van Assche ret = -EINVAL;
438dd11376bSBart Van Assche goto out;
439dd11376bSBart Van Assche }
440dd11376bSBart Van Assche
441dd11376bSBart Van Assche ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main);
442dd11376bSBart Van Assche pclk_rate = clk_get_rate(ufs->clk_hci_core);
443dd11376bSBart Van Assche f_min = ufs->pclk_avail_min;
444dd11376bSBart Van Assche f_max = ufs->pclk_avail_max;
445dd11376bSBart Van Assche
446dd11376bSBart Van Assche if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
447dd11376bSBart Van Assche do {
448dd11376bSBart Van Assche pclk_rate /= (div + 1);
449dd11376bSBart Van Assche
450dd11376bSBart Van Assche if (pclk_rate <= f_max)
451dd11376bSBart Van Assche break;
452dd11376bSBart Van Assche div++;
453dd11376bSBart Van Assche } while (pclk_rate >= f_min);
454dd11376bSBart Van Assche }
455dd11376bSBart Van Assche
456dd11376bSBart Van Assche if (unlikely(pclk_rate < f_min || pclk_rate > f_max)) {
457dd11376bSBart Van Assche dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate);
458dd11376bSBart Van Assche ret = -EINVAL;
459dd11376bSBart Van Assche goto out;
460dd11376bSBart Van Assche }
461dd11376bSBart Van Assche
462dd11376bSBart Van Assche ufs->pclk_rate = pclk_rate;
463dd11376bSBart Van Assche ufs->pclk_div = div;
464dd11376bSBart Van Assche
465dd11376bSBart Van Assche out:
466dd11376bSBart Van Assche return ret;
467dd11376bSBart Van Assche }
468dd11376bSBart Van Assche
exynos_ufs_set_unipro_pclk_div(struct exynos_ufs * ufs)469dd11376bSBart Van Assche static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs)
470dd11376bSBart Van Assche {
471dd11376bSBart Van Assche if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
472dd11376bSBart Van Assche u32 val;
473dd11376bSBart Van Assche
474dd11376bSBart Van Assche val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL);
475dd11376bSBart Van Assche hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div),
476dd11376bSBart Van Assche HCI_UNIPRO_APB_CLK_CTRL);
477dd11376bSBart Van Assche }
478dd11376bSBart Van Assche }
479dd11376bSBart Van Assche
exynos_ufs_set_pwm_clk_div(struct exynos_ufs * ufs)480dd11376bSBart Van Assche static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs)
481dd11376bSBart Van Assche {
482dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
483dd11376bSBart Van Assche struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
484dd11376bSBart Van Assche
485dd11376bSBart Van Assche ufshcd_dme_set(hba,
486dd11376bSBart Van Assche UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl);
487dd11376bSBart Van Assche }
488dd11376bSBart Van Assche
exynos_ufs_calc_pwm_clk_div(struct exynos_ufs * ufs)489dd11376bSBart Van Assche static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs)
490dd11376bSBart Van Assche {
491dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
492dd11376bSBart Van Assche struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
493dd11376bSBart Van Assche const unsigned int div = 30, mult = 20;
494dd11376bSBart Van Assche const unsigned long pwm_min = 3 * 1000 * 1000;
495dd11376bSBart Van Assche const unsigned long pwm_max = 9 * 1000 * 1000;
496dd11376bSBart Van Assche const int divs[] = {32, 16, 8, 4};
497dd11376bSBart Van Assche unsigned long clk = 0, _clk, clk_period;
498dd11376bSBart Van Assche int i = 0, clk_idx = -1;
499dd11376bSBart Van Assche
500dd11376bSBart Van Assche clk_period = UNIPRO_PCLK_PERIOD(ufs);
501dd11376bSBart Van Assche for (i = 0; i < ARRAY_SIZE(divs); i++) {
502dd11376bSBart Van Assche _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div);
503dd11376bSBart Van Assche if (_clk >= pwm_min && _clk <= pwm_max) {
504dd11376bSBart Van Assche if (_clk > clk) {
505dd11376bSBart Van Assche clk_idx = i;
506dd11376bSBart Van Assche clk = _clk;
507dd11376bSBart Van Assche }
508dd11376bSBart Van Assche }
509dd11376bSBart Van Assche }
510dd11376bSBart Van Assche
511dd11376bSBart Van Assche if (clk_idx == -1) {
512dd11376bSBart Van Assche ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx);
513dd11376bSBart Van Assche dev_err(hba->dev,
514dd11376bSBart Van Assche "failed to decide pwm clock divider, will not change\n");
515dd11376bSBart Van Assche }
516dd11376bSBart Van Assche
517dd11376bSBart Van Assche attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK;
518dd11376bSBart Van Assche }
519dd11376bSBart Van Assche
exynos_ufs_calc_time_cntr(struct exynos_ufs * ufs,long period)520dd11376bSBart Van Assche long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period)
521dd11376bSBart Van Assche {
522dd11376bSBart Van Assche const int precise = 10;
523dd11376bSBart Van Assche long pclk_rate = ufs->pclk_rate;
524dd11376bSBart Van Assche long clk_period, fraction;
525dd11376bSBart Van Assche
526dd11376bSBart Van Assche clk_period = UNIPRO_PCLK_PERIOD(ufs);
527dd11376bSBart Van Assche fraction = ((NSEC_PER_SEC % pclk_rate) * precise) / pclk_rate;
528dd11376bSBart Van Assche
529dd11376bSBart Van Assche return (period * precise) / ((clk_period * precise) + fraction);
530dd11376bSBart Van Assche }
531dd11376bSBart Van Assche
exynos_ufs_specify_phy_time_attr(struct exynos_ufs * ufs)532dd11376bSBart Van Assche static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs)
533dd11376bSBart Van Assche {
534dd11376bSBart Van Assche struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
535dd11376bSBart Van Assche struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
536dd11376bSBart Van Assche
537dd11376bSBart Van Assche t_cfg->tx_linereset_p =
538dd11376bSBart Van Assche exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec);
539dd11376bSBart Van Assche t_cfg->tx_linereset_n =
540dd11376bSBart Van Assche exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec);
541dd11376bSBart Van Assche t_cfg->tx_high_z_cnt =
542dd11376bSBart Van Assche exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec);
543dd11376bSBart Van Assche t_cfg->tx_base_n_val =
544dd11376bSBart Van Assche exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec);
545dd11376bSBart Van Assche t_cfg->tx_gran_n_val =
546dd11376bSBart Van Assche exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec);
547dd11376bSBart Van Assche t_cfg->tx_sleep_cnt =
548dd11376bSBart Van Assche exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt);
549dd11376bSBart Van Assche
550dd11376bSBart Van Assche t_cfg->rx_linereset =
551dd11376bSBart Van Assche exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec);
552dd11376bSBart Van Assche t_cfg->rx_hibern8_wait =
553dd11376bSBart Van Assche exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec);
554dd11376bSBart Van Assche t_cfg->rx_base_n_val =
555dd11376bSBart Van Assche exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec);
556dd11376bSBart Van Assche t_cfg->rx_gran_n_val =
557dd11376bSBart Van Assche exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec);
558dd11376bSBart Van Assche t_cfg->rx_sleep_cnt =
559dd11376bSBart Van Assche exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt);
560dd11376bSBart Van Assche t_cfg->rx_stall_cnt =
561dd11376bSBart Van Assche exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt);
562dd11376bSBart Van Assche }
563dd11376bSBart Van Assche
exynos_ufs_config_phy_time_attr(struct exynos_ufs * ufs)564dd11376bSBart Van Assche static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs)
565dd11376bSBart Van Assche {
566dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
567dd11376bSBart Van Assche struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
568dd11376bSBart Van Assche int i;
569dd11376bSBart Van Assche
570dd11376bSBart Van Assche exynos_ufs_set_pwm_clk_div(ufs);
571dd11376bSBart Van Assche
572dd11376bSBart Van Assche exynos_ufs_enable_ov_tm(hba);
573dd11376bSBart Van Assche
574dd11376bSBart Van Assche for_each_ufs_rx_lane(ufs, i) {
575dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i),
576dd11376bSBart Van Assche ufs->drv_data->uic_attr->rx_filler_enable);
577dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i),
578dd11376bSBart Van Assche RX_LINERESET(t_cfg->rx_linereset));
579dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i),
580dd11376bSBart Van Assche RX_BASE_NVAL_L(t_cfg->rx_base_n_val));
581dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i),
582dd11376bSBart Van Assche RX_BASE_NVAL_H(t_cfg->rx_base_n_val));
583dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i),
584dd11376bSBart Van Assche RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val));
585dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i),
586dd11376bSBart Van Assche RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val));
587dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i),
588dd11376bSBart Van Assche RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt));
589dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i),
590dd11376bSBart Van Assche RX_OV_STALL_CNT(t_cfg->rx_stall_cnt));
591dd11376bSBart Van Assche }
592dd11376bSBart Van Assche
593dd11376bSBart Van Assche for_each_ufs_tx_lane(ufs, i) {
594dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i),
595dd11376bSBart Van Assche TX_LINERESET_P(t_cfg->tx_linereset_p));
596dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i),
597dd11376bSBart Van Assche TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt));
598dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i),
599dd11376bSBart Van Assche TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt));
600dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i),
601dd11376bSBart Van Assche TX_BASE_NVAL_L(t_cfg->tx_base_n_val));
602dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i),
603dd11376bSBart Van Assche TX_BASE_NVAL_H(t_cfg->tx_base_n_val));
604dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i),
605dd11376bSBart Van Assche TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val));
606dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i),
607dd11376bSBart Van Assche TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val));
608dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i),
609dd11376bSBart Van Assche TX_OV_H8_ENTER_EN |
610dd11376bSBart Van Assche TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt));
611dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i),
612dd11376bSBart Van Assche ufs->drv_data->uic_attr->tx_min_activatetime);
613dd11376bSBart Van Assche }
614dd11376bSBart Van Assche
615dd11376bSBart Van Assche exynos_ufs_disable_ov_tm(hba);
616dd11376bSBart Van Assche }
617dd11376bSBart Van Assche
exynos_ufs_config_phy_cap_attr(struct exynos_ufs * ufs)618dd11376bSBart Van Assche static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs)
619dd11376bSBart Van Assche {
620dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
621dd11376bSBart Van Assche struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
622dd11376bSBart Van Assche int i;
623dd11376bSBart Van Assche
624dd11376bSBart Van Assche exynos_ufs_enable_ov_tm(hba);
625dd11376bSBart Van Assche
626dd11376bSBart Van Assche for_each_ufs_rx_lane(ufs, i) {
627dd11376bSBart Van Assche ufshcd_dme_set(hba,
628dd11376bSBart Van Assche UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i),
629dd11376bSBart Van Assche attr->rx_hs_g1_sync_len_cap);
630dd11376bSBart Van Assche ufshcd_dme_set(hba,
631dd11376bSBart Van Assche UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i),
632dd11376bSBart Van Assche attr->rx_hs_g2_sync_len_cap);
633dd11376bSBart Van Assche ufshcd_dme_set(hba,
634dd11376bSBart Van Assche UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i),
635dd11376bSBart Van Assche attr->rx_hs_g3_sync_len_cap);
636dd11376bSBart Van Assche ufshcd_dme_set(hba,
637dd11376bSBart Van Assche UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i),
638dd11376bSBart Van Assche attr->rx_hs_g1_prep_sync_len_cap);
639dd11376bSBart Van Assche ufshcd_dme_set(hba,
640dd11376bSBart Van Assche UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i),
641dd11376bSBart Van Assche attr->rx_hs_g2_prep_sync_len_cap);
642dd11376bSBart Van Assche ufshcd_dme_set(hba,
643dd11376bSBart Van Assche UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i),
644dd11376bSBart Van Assche attr->rx_hs_g3_prep_sync_len_cap);
645dd11376bSBart Van Assche }
646dd11376bSBart Van Assche
647dd11376bSBart Van Assche if (attr->rx_adv_fine_gran_sup_en == 0) {
648dd11376bSBart Van Assche for_each_ufs_rx_lane(ufs, i) {
649dd11376bSBart Van Assche ufshcd_dme_set(hba,
650dd11376bSBart Van Assche UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0);
651dd11376bSBart Van Assche
652dd11376bSBart Van Assche if (attr->rx_min_actv_time_cap)
653dd11376bSBart Van Assche ufshcd_dme_set(hba,
654cb2bf7c6SAlim Akhtar UIC_ARG_MIB_SEL(
655cb2bf7c6SAlim Akhtar RX_MIN_ACTIVATETIME_CAPABILITY, i),
656cb2bf7c6SAlim Akhtar attr->rx_min_actv_time_cap);
657dd11376bSBart Van Assche
658dd11376bSBart Van Assche if (attr->rx_hibern8_time_cap)
659dd11376bSBart Van Assche ufshcd_dme_set(hba,
660dd11376bSBart Van Assche UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i),
661dd11376bSBart Van Assche attr->rx_hibern8_time_cap);
662dd11376bSBart Van Assche }
663dd11376bSBart Van Assche } else if (attr->rx_adv_fine_gran_sup_en == 1) {
664dd11376bSBart Van Assche for_each_ufs_rx_lane(ufs, i) {
665dd11376bSBart Van Assche if (attr->rx_adv_fine_gran_step)
666dd11376bSBart Van Assche ufshcd_dme_set(hba,
667dd11376bSBart Van Assche UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP,
668dd11376bSBart Van Assche i), RX_ADV_FINE_GRAN_STEP(
669dd11376bSBart Van Assche attr->rx_adv_fine_gran_step));
670dd11376bSBart Van Assche
671dd11376bSBart Van Assche if (attr->rx_adv_min_actv_time_cap)
672dd11376bSBart Van Assche ufshcd_dme_set(hba,
673dd11376bSBart Van Assche UIC_ARG_MIB_SEL(
674dd11376bSBart Van Assche RX_ADV_MIN_ACTIVATETIME_CAP, i),
675dd11376bSBart Van Assche attr->rx_adv_min_actv_time_cap);
676dd11376bSBart Van Assche
677dd11376bSBart Van Assche if (attr->rx_adv_hibern8_time_cap)
678dd11376bSBart Van Assche ufshcd_dme_set(hba,
679dd11376bSBart Van Assche UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP,
680dd11376bSBart Van Assche i),
681dd11376bSBart Van Assche attr->rx_adv_hibern8_time_cap);
682dd11376bSBart Van Assche }
683dd11376bSBart Van Assche }
684dd11376bSBart Van Assche
685dd11376bSBart Van Assche exynos_ufs_disable_ov_tm(hba);
686dd11376bSBart Van Assche }
687dd11376bSBart Van Assche
exynos_ufs_establish_connt(struct exynos_ufs * ufs)688dd11376bSBart Van Assche static void exynos_ufs_establish_connt(struct exynos_ufs *ufs)
689dd11376bSBart Van Assche {
690dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
691dd11376bSBart Van Assche enum {
692dd11376bSBart Van Assche DEV_ID = 0x00,
693dd11376bSBart Van Assche PEER_DEV_ID = 0x01,
694dd11376bSBart Van Assche PEER_CPORT_ID = 0x00,
695dd11376bSBart Van Assche TRAFFIC_CLASS = 0x00,
696dd11376bSBart Van Assche };
697dd11376bSBart Van Assche
698dd11376bSBart Van Assche /* allow cport attributes to be set */
699dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE);
700dd11376bSBart Van Assche
701dd11376bSBart Van Assche /* local unipro attributes */
702dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID);
703dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), true);
704dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID);
705dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID);
706dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS);
707dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS);
708dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED);
709dd11376bSBart Van Assche }
710dd11376bSBart Van Assche
exynos_ufs_config_smu(struct exynos_ufs * ufs)711dd11376bSBart Van Assche static void exynos_ufs_config_smu(struct exynos_ufs *ufs)
712dd11376bSBart Van Assche {
713dd11376bSBart Van Assche u32 reg, val;
714dd11376bSBart Van Assche
715dd11376bSBart Van Assche exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
716dd11376bSBart Van Assche
717dd11376bSBart Van Assche /* make encryption disabled by default */
718dd11376bSBart Van Assche reg = ufsp_readl(ufs, UFSPRSECURITY);
719dd11376bSBart Van Assche ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY);
720dd11376bSBart Van Assche ufsp_writel(ufs, 0x0, UFSPSBEGIN0);
721dd11376bSBart Van Assche ufsp_writel(ufs, 0xffffffff, UFSPSEND0);
722dd11376bSBart Van Assche ufsp_writel(ufs, 0xff, UFSPSLUN0);
723dd11376bSBart Van Assche ufsp_writel(ufs, 0xf1, UFSPSCTRL0);
724dd11376bSBart Van Assche
725dd11376bSBart Van Assche exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
726dd11376bSBart Van Assche }
727dd11376bSBart Van Assche
exynos_ufs_config_sync_pattern_mask(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)728dd11376bSBart Van Assche static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs,
729dd11376bSBart Van Assche struct ufs_pa_layer_attr *pwr)
730dd11376bSBart Van Assche {
731dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
732dd11376bSBart Van Assche u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx);
733dd11376bSBart Van Assche u32 mask, sync_len;
734dd11376bSBart Van Assche enum {
735dd11376bSBart Van Assche SYNC_LEN_G1 = 80 * 1000, /* 80us */
736dd11376bSBart Van Assche SYNC_LEN_G2 = 40 * 1000, /* 44us */
737dd11376bSBart Van Assche SYNC_LEN_G3 = 20 * 1000, /* 20us */
738dd11376bSBart Van Assche };
739dd11376bSBart Van Assche int i;
740dd11376bSBart Van Assche
741dd11376bSBart Van Assche if (g == 1)
742dd11376bSBart Van Assche sync_len = SYNC_LEN_G1;
743dd11376bSBart Van Assche else if (g == 2)
744dd11376bSBart Van Assche sync_len = SYNC_LEN_G2;
745dd11376bSBart Van Assche else if (g == 3)
746dd11376bSBart Van Assche sync_len = SYNC_LEN_G3;
747dd11376bSBart Van Assche else
748dd11376bSBart Van Assche return;
749dd11376bSBart Van Assche
750dd11376bSBart Van Assche mask = exynos_ufs_calc_time_cntr(ufs, sync_len);
751dd11376bSBart Van Assche mask = (mask >> 8) & 0xff;
752dd11376bSBart Van Assche
753dd11376bSBart Van Assche exynos_ufs_enable_ov_tm(hba);
754dd11376bSBart Van Assche
755dd11376bSBart Van Assche for_each_ufs_rx_lane(ufs, i)
756dd11376bSBart Van Assche ufshcd_dme_set(hba,
757dd11376bSBart Van Assche UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask);
758dd11376bSBart Van Assche
759dd11376bSBart Van Assche exynos_ufs_disable_ov_tm(hba);
760dd11376bSBart Van Assche }
761dd11376bSBart Van Assche
exynos_ufs_pre_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)762dd11376bSBart Van Assche static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
763dd11376bSBart Van Assche struct ufs_pa_layer_attr *dev_max_params,
764dd11376bSBart Van Assche struct ufs_pa_layer_attr *dev_req_params)
765dd11376bSBart Van Assche {
766dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
767dd11376bSBart Van Assche struct phy *generic_phy = ufs->phy;
768dd11376bSBart Van Assche struct ufs_dev_params ufs_exynos_cap;
769dd11376bSBart Van Assche int ret;
770dd11376bSBart Van Assche
771dd11376bSBart Van Assche if (!dev_req_params) {
772dd11376bSBart Van Assche pr_err("%s: incoming dev_req_params is NULL\n", __func__);
773dd11376bSBart Van Assche ret = -EINVAL;
774dd11376bSBart Van Assche goto out;
775dd11376bSBart Van Assche }
776dd11376bSBart Van Assche
777dd11376bSBart Van Assche ufshcd_init_pwr_dev_param(&ufs_exynos_cap);
778dd11376bSBart Van Assche
779dd11376bSBart Van Assche ret = ufshcd_get_pwr_dev_param(&ufs_exynos_cap,
780dd11376bSBart Van Assche dev_max_params, dev_req_params);
781dd11376bSBart Van Assche if (ret) {
782dd11376bSBart Van Assche pr_err("%s: failed to determine capabilities\n", __func__);
783dd11376bSBart Van Assche goto out;
784dd11376bSBart Van Assche }
785dd11376bSBart Van Assche
786dd11376bSBart Van Assche if (ufs->drv_data->pre_pwr_change)
787dd11376bSBart Van Assche ufs->drv_data->pre_pwr_change(ufs, dev_req_params);
788dd11376bSBart Van Assche
789dd11376bSBart Van Assche if (ufshcd_is_hs_mode(dev_req_params)) {
790dd11376bSBart Van Assche exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params);
791dd11376bSBart Van Assche
792dd11376bSBart Van Assche switch (dev_req_params->hs_rate) {
793dd11376bSBart Van Assche case PA_HS_MODE_A:
794dd11376bSBart Van Assche case PA_HS_MODE_B:
795dd11376bSBart Van Assche phy_calibrate(generic_phy);
796dd11376bSBart Van Assche break;
797dd11376bSBart Van Assche }
798dd11376bSBart Van Assche }
799dd11376bSBart Van Assche
800dd11376bSBart Van Assche /* setting for three timeout values for traffic class #0 */
801dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);
802dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224);
803dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);
804dd11376bSBart Van Assche
805dd11376bSBart Van Assche return 0;
806dd11376bSBart Van Assche out:
807dd11376bSBart Van Assche return ret;
808dd11376bSBart Van Assche }
809dd11376bSBart Van Assche
810dd11376bSBart Van Assche #define PWR_MODE_STR_LEN 64
exynos_ufs_post_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * pwr_req)811dd11376bSBart Van Assche static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba,
812dd11376bSBart Van Assche struct ufs_pa_layer_attr *pwr_req)
813dd11376bSBart Van Assche {
814dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
815dd11376bSBart Van Assche struct phy *generic_phy = ufs->phy;
816dd11376bSBart Van Assche int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx);
817dd11376bSBart Van Assche int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx);
818dd11376bSBart Van Assche char pwr_str[PWR_MODE_STR_LEN] = "";
819dd11376bSBart Van Assche
820dd11376bSBart Van Assche /* let default be PWM Gear 1, Lane 1 */
821dd11376bSBart Van Assche if (!gear)
822dd11376bSBart Van Assche gear = 1;
823dd11376bSBart Van Assche
824dd11376bSBart Van Assche if (!lanes)
825dd11376bSBart Van Assche lanes = 1;
826dd11376bSBart Van Assche
827dd11376bSBart Van Assche if (ufs->drv_data->post_pwr_change)
828dd11376bSBart Van Assche ufs->drv_data->post_pwr_change(ufs, pwr_req);
829dd11376bSBart Van Assche
830dd11376bSBart Van Assche if ((ufshcd_is_hs_mode(pwr_req))) {
831dd11376bSBart Van Assche switch (pwr_req->hs_rate) {
832dd11376bSBart Van Assche case PA_HS_MODE_A:
833dd11376bSBart Van Assche case PA_HS_MODE_B:
834dd11376bSBart Van Assche phy_calibrate(generic_phy);
835dd11376bSBart Van Assche break;
836dd11376bSBart Van Assche }
837dd11376bSBart Van Assche
838dd11376bSBart Van Assche snprintf(pwr_str, PWR_MODE_STR_LEN, "%s series_%s G_%d L_%d",
839dd11376bSBart Van Assche "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B",
840dd11376bSBart Van Assche gear, lanes);
841dd11376bSBart Van Assche } else {
842dd11376bSBart Van Assche snprintf(pwr_str, PWR_MODE_STR_LEN, "%s G_%d L_%d",
843dd11376bSBart Van Assche "SLOW", gear, lanes);
844dd11376bSBart Van Assche }
845dd11376bSBart Van Assche
846dd11376bSBart Van Assche dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str);
847dd11376bSBart Van Assche
848dd11376bSBart Van Assche return 0;
849dd11376bSBart Van Assche }
850dd11376bSBart Van Assche
exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba * hba,int tag,bool is_scsi_cmd)851dd11376bSBart Van Assche static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba,
852dd11376bSBart Van Assche int tag, bool is_scsi_cmd)
853dd11376bSBart Van Assche {
854dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
855dd11376bSBart Van Assche u32 type;
856dd11376bSBart Van Assche
857dd11376bSBart Van Assche type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
858dd11376bSBart Van Assche
859dd11376bSBart Van Assche if (is_scsi_cmd)
860dd11376bSBart Van Assche hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE);
861dd11376bSBart Van Assche else
862dd11376bSBart Van Assche hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE);
863dd11376bSBart Van Assche }
864dd11376bSBart Van Assche
exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba * hba,int tag,u8 func)865dd11376bSBart Van Assche static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba,
866dd11376bSBart Van Assche int tag, u8 func)
867dd11376bSBart Van Assche {
868dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
869dd11376bSBart Van Assche u32 type;
870dd11376bSBart Van Assche
871dd11376bSBart Van Assche type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE);
872dd11376bSBart Van Assche
873dd11376bSBart Van Assche switch (func) {
874dd11376bSBart Van Assche case UFS_ABORT_TASK:
875dd11376bSBart Van Assche case UFS_QUERY_TASK:
876dd11376bSBart Van Assche hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE);
877dd11376bSBart Van Assche break;
878dd11376bSBart Van Assche case UFS_ABORT_TASK_SET:
879dd11376bSBart Van Assche case UFS_CLEAR_TASK_SET:
880dd11376bSBart Van Assche case UFS_LOGICAL_RESET:
881dd11376bSBart Van Assche case UFS_QUERY_TASK_SET:
882dd11376bSBart Van Assche hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE);
883dd11376bSBart Van Assche break;
884dd11376bSBart Van Assche }
885dd11376bSBart Van Assche }
886dd11376bSBart Van Assche
exynos_ufs_phy_init(struct exynos_ufs * ufs)887dd11376bSBart Van Assche static int exynos_ufs_phy_init(struct exynos_ufs *ufs)
888dd11376bSBart Van Assche {
889dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
890dd11376bSBart Van Assche struct phy *generic_phy = ufs->phy;
891dd11376bSBart Van Assche int ret = 0;
892dd11376bSBart Van Assche
893dd11376bSBart Van Assche if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) {
894dd11376bSBart Van Assche ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),
895dd11376bSBart Van Assche &ufs->avail_ln_rx);
896dd11376bSBart Van Assche ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),
897dd11376bSBart Van Assche &ufs->avail_ln_tx);
898dd11376bSBart Van Assche WARN(ufs->avail_ln_rx != ufs->avail_ln_tx,
899dd11376bSBart Van Assche "available data lane is not equal(rx:%d, tx:%d)\n",
900dd11376bSBart Van Assche ufs->avail_ln_rx, ufs->avail_ln_tx);
901dd11376bSBart Van Assche }
902dd11376bSBart Van Assche
903dd11376bSBart Van Assche phy_set_bus_width(generic_phy, ufs->avail_ln_rx);
904dd11376bSBart Van Assche ret = phy_init(generic_phy);
905dd11376bSBart Van Assche if (ret) {
906dd11376bSBart Van Assche dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
907dd11376bSBart Van Assche __func__, ret);
9083d73b200SChanho Park return ret;
909dd11376bSBart Van Assche }
910dd11376bSBart Van Assche
9113d73b200SChanho Park ret = phy_power_on(generic_phy);
9123d73b200SChanho Park if (ret)
9133d73b200SChanho Park goto out_exit_phy;
9143d73b200SChanho Park
915dd11376bSBart Van Assche return 0;
916dd11376bSBart Van Assche
917dd11376bSBart Van Assche out_exit_phy:
918dd11376bSBart Van Assche phy_exit(generic_phy);
919dd11376bSBart Van Assche
920dd11376bSBart Van Assche return ret;
921dd11376bSBart Van Assche }
922dd11376bSBart Van Assche
exynos_ufs_config_unipro(struct exynos_ufs * ufs)923dd11376bSBart Van Assche static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
924dd11376bSBart Van Assche {
925dd11376bSBart Van Assche struct ufs_hba *hba = ufs->hba;
926dd11376bSBart Van Assche
927dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
928dd11376bSBart Van Assche DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
929dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS),
930dd11376bSBart Van Assche ufs->drv_data->uic_attr->tx_trailingclks);
931dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE),
932dd11376bSBart Van Assche ufs->drv_data->uic_attr->pa_dbg_option_suite);
933dd11376bSBart Van Assche }
934dd11376bSBart Van Assche
exynos_ufs_config_intr(struct exynos_ufs * ufs,u32 errs,u8 index)935dd11376bSBart Van Assche static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
936dd11376bSBart Van Assche {
937dd11376bSBart Van Assche switch (index) {
938dd11376bSBart Van Assche case UNIPRO_L1_5:
939dd11376bSBart Van Assche hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER);
940dd11376bSBart Van Assche break;
941dd11376bSBart Van Assche case UNIPRO_L2:
942dd11376bSBart Van Assche hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER);
943dd11376bSBart Van Assche break;
944dd11376bSBart Van Assche case UNIPRO_L3:
945dd11376bSBart Van Assche hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER);
946dd11376bSBart Van Assche break;
947dd11376bSBart Van Assche case UNIPRO_L4:
948dd11376bSBart Van Assche hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER);
949dd11376bSBart Van Assche break;
950dd11376bSBart Van Assche case UNIPRO_DME:
951dd11376bSBart Van Assche hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER);
952dd11376bSBart Van Assche break;
953dd11376bSBart Van Assche }
954dd11376bSBart Van Assche }
955dd11376bSBart Van Assche
exynos_ufs_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)956dd11376bSBart Van Assche static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on,
957dd11376bSBart Van Assche enum ufs_notify_change_status status)
958dd11376bSBart Van Assche {
959dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
960dd11376bSBart Van Assche
961dd11376bSBart Van Assche if (!ufs)
962dd11376bSBart Van Assche return 0;
963dd11376bSBart Van Assche
964dd11376bSBart Van Assche if (on && status == PRE_CHANGE) {
965dd11376bSBart Van Assche if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
966dd11376bSBart Van Assche exynos_ufs_disable_auto_ctrl_hcc(ufs);
967dd11376bSBart Van Assche exynos_ufs_ungate_clks(ufs);
968dd11376bSBart Van Assche } else if (!on && status == POST_CHANGE) {
969dd11376bSBart Van Assche exynos_ufs_gate_clks(ufs);
970dd11376bSBart Van Assche if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
971dd11376bSBart Van Assche exynos_ufs_enable_auto_ctrl_hcc(ufs);
972dd11376bSBart Van Assche }
973dd11376bSBart Van Assche
974dd11376bSBart Van Assche return 0;
975dd11376bSBart Van Assche }
976dd11376bSBart Van Assche
exynos_ufs_pre_link(struct ufs_hba * hba)977dd11376bSBart Van Assche static int exynos_ufs_pre_link(struct ufs_hba *hba)
978dd11376bSBart Van Assche {
979dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
980dd11376bSBart Van Assche
981dd11376bSBart Van Assche /* hci */
982dd11376bSBart Van Assche exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2);
983dd11376bSBart Van Assche exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3);
984dd11376bSBart Van Assche exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4);
985dd11376bSBart Van Assche exynos_ufs_set_unipro_pclk_div(ufs);
986dd11376bSBart Van Assche
987dd11376bSBart Van Assche /* unipro */
988dd11376bSBart Van Assche exynos_ufs_config_unipro(ufs);
989dd11376bSBart Van Assche
990dd11376bSBart Van Assche /* m-phy */
991dd11376bSBart Van Assche exynos_ufs_phy_init(ufs);
992dd11376bSBart Van Assche if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) {
993dd11376bSBart Van Assche exynos_ufs_config_phy_time_attr(ufs);
994dd11376bSBart Van Assche exynos_ufs_config_phy_cap_attr(ufs);
995dd11376bSBart Van Assche }
996dd11376bSBart Van Assche
997dd11376bSBart Van Assche exynos_ufs_setup_clocks(hba, true, PRE_CHANGE);
998dd11376bSBart Van Assche
999dd11376bSBart Van Assche if (ufs->drv_data->pre_link)
1000dd11376bSBart Van Assche ufs->drv_data->pre_link(ufs);
1001dd11376bSBart Van Assche
1002dd11376bSBart Van Assche return 0;
1003dd11376bSBart Van Assche }
1004dd11376bSBart Van Assche
exynos_ufs_fit_aggr_timeout(struct exynos_ufs * ufs)1005dd11376bSBart Van Assche static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs)
1006dd11376bSBart Van Assche {
1007dd11376bSBart Van Assche u32 val;
1008dd11376bSBart Van Assche
1009dd11376bSBart Van Assche val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL);
1010dd11376bSBart Van Assche hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL);
1011dd11376bSBart Van Assche }
1012dd11376bSBart Van Assche
exynos_ufs_post_link(struct ufs_hba * hba)1013dd11376bSBart Van Assche static int exynos_ufs_post_link(struct ufs_hba *hba)
1014dd11376bSBart Van Assche {
1015dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1016dd11376bSBart Van Assche struct phy *generic_phy = ufs->phy;
1017dd11376bSBart Van Assche struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1018dd11376bSBart Van Assche
1019dd11376bSBart Van Assche exynos_ufs_establish_connt(ufs);
1020dd11376bSBart Van Assche exynos_ufs_fit_aggr_timeout(ufs);
1021dd11376bSBart Van Assche
1022dd11376bSBart Van Assche hci_writel(ufs, 0xa, HCI_DATA_REORDER);
1023dd11376bSBart Van Assche hci_writel(ufs, PRDT_SET_SIZE(12), HCI_TXPRDT_ENTRY_SIZE);
1024dd11376bSBart Van Assche hci_writel(ufs, PRDT_SET_SIZE(12), HCI_RXPRDT_ENTRY_SIZE);
1025dd11376bSBart Van Assche hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE);
1026dd11376bSBart Van Assche hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE);
1027dd11376bSBart Van Assche hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN);
1028dd11376bSBart Van Assche
1029dd11376bSBart Van Assche if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)
1030dd11376bSBart Van Assche ufshcd_dme_set(hba,
1031dd11376bSBart Van Assche UIC_ARG_MIB(T_DBG_SKIP_INIT_HIBERN8_EXIT), true);
1032dd11376bSBart Van Assche
1033dd11376bSBart Van Assche if (attr->pa_granularity) {
1034dd11376bSBart Van Assche exynos_ufs_enable_dbg_mode(hba);
1035dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY),
1036dd11376bSBart Van Assche attr->pa_granularity);
1037dd11376bSBart Van Assche exynos_ufs_disable_dbg_mode(hba);
1038dd11376bSBart Van Assche
1039dd11376bSBart Van Assche if (attr->pa_tactivate)
1040dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
1041dd11376bSBart Van Assche attr->pa_tactivate);
1042dd11376bSBart Van Assche if (attr->pa_hibern8time &&
1043dd11376bSBart Van Assche !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER))
1044dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
1045dd11376bSBart Van Assche attr->pa_hibern8time);
1046dd11376bSBart Van Assche }
1047dd11376bSBart Van Assche
1048dd11376bSBart Van Assche if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1049dd11376bSBart Van Assche if (!attr->pa_granularity)
1050dd11376bSBart Van Assche ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
1051dd11376bSBart Van Assche &attr->pa_granularity);
1052dd11376bSBart Van Assche if (!attr->pa_hibern8time)
1053dd11376bSBart Van Assche ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
1054dd11376bSBart Van Assche &attr->pa_hibern8time);
1055dd11376bSBart Van Assche /*
1056dd11376bSBart Van Assche * not wait for HIBERN8 time to exit hibernation
1057dd11376bSBart Van Assche */
1058dd11376bSBart Van Assche ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0);
1059dd11376bSBart Van Assche
1060dd11376bSBart Van Assche if (attr->pa_granularity < 1 || attr->pa_granularity > 6) {
1061dd11376bSBart Van Assche /* Valid range for granularity: 1 ~ 6 */
1062dd11376bSBart Van Assche dev_warn(hba->dev,
1063dd11376bSBart Van Assche "%s: pa_granularity %d is invalid, assuming backwards compatibility\n",
1064dd11376bSBart Van Assche __func__,
1065dd11376bSBart Van Assche attr->pa_granularity);
1066dd11376bSBart Van Assche attr->pa_granularity = 6;
1067dd11376bSBart Van Assche }
1068dd11376bSBart Van Assche }
1069dd11376bSBart Van Assche
1070dd11376bSBart Van Assche phy_calibrate(generic_phy);
1071dd11376bSBart Van Assche
1072dd11376bSBart Van Assche if (ufs->drv_data->post_link)
1073dd11376bSBart Van Assche ufs->drv_data->post_link(ufs);
1074dd11376bSBart Van Assche
1075dd11376bSBart Van Assche return 0;
1076dd11376bSBart Van Assche }
1077dd11376bSBart Van Assche
exynos_ufs_parse_dt(struct device * dev,struct exynos_ufs * ufs)1078dd11376bSBart Van Assche static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
1079dd11376bSBart Van Assche {
1080dd11376bSBart Van Assche struct device_node *np = dev->of_node;
1081dd11376bSBart Van Assche struct exynos_ufs_uic_attr *attr;
1082dd11376bSBart Van Assche int ret = 0;
1083dd11376bSBart Van Assche
1084dd11376bSBart Van Assche ufs->drv_data = device_get_match_data(dev);
1085dd11376bSBart Van Assche
1086dd11376bSBart Van Assche if (ufs->drv_data && ufs->drv_data->uic_attr) {
1087dd11376bSBart Van Assche attr = ufs->drv_data->uic_attr;
1088dd11376bSBart Van Assche } else {
1089dd11376bSBart Van Assche dev_err(dev, "failed to get uic attributes\n");
1090dd11376bSBart Van Assche ret = -EINVAL;
1091dd11376bSBart Van Assche goto out;
1092dd11376bSBart Van Assche }
1093dd11376bSBart Van Assche
1094dd11376bSBart Van Assche ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg");
1095dd11376bSBart Van Assche if (IS_ERR(ufs->sysreg))
1096dd11376bSBart Van Assche ufs->sysreg = NULL;
1097dd11376bSBart Van Assche else {
1098dd11376bSBart Van Assche if (of_property_read_u32_index(np, "samsung,sysreg", 1,
1099dd11376bSBart Van Assche &ufs->shareability_reg_offset)) {
1100dd11376bSBart Van Assche dev_warn(dev, "can't get an offset from sysreg. Set to default value\n");
1101dd11376bSBart Van Assche ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET;
1102dd11376bSBart Van Assche }
1103dd11376bSBart Van Assche }
1104dd11376bSBart Van Assche
1105dd11376bSBart Van Assche ufs->pclk_avail_min = PCLK_AVAIL_MIN;
1106dd11376bSBart Van Assche ufs->pclk_avail_max = PCLK_AVAIL_MAX;
1107dd11376bSBart Van Assche
1108dd11376bSBart Van Assche attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN;
1109dd11376bSBart Van Assche attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL;
1110dd11376bSBart Van Assche attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP;
1111dd11376bSBart Van Assche attr->pa_granularity = PA_GRANULARITY_VAL;
1112dd11376bSBart Van Assche attr->pa_tactivate = PA_TACTIVATE_VAL;
1113dd11376bSBart Van Assche attr->pa_hibern8time = PA_HIBERN8TIME_VAL;
1114dd11376bSBart Van Assche
1115dd11376bSBart Van Assche out:
1116dd11376bSBart Van Assche return ret;
1117dd11376bSBart Van Assche }
1118dd11376bSBart Van Assche
exynos_ufs_priv_init(struct ufs_hba * hba,struct exynos_ufs * ufs)1119dd11376bSBart Van Assche static inline void exynos_ufs_priv_init(struct ufs_hba *hba,
1120dd11376bSBart Van Assche struct exynos_ufs *ufs)
1121dd11376bSBart Van Assche {
1122dd11376bSBart Van Assche ufs->hba = hba;
1123dd11376bSBart Van Assche ufs->opts = ufs->drv_data->opts;
1124dd11376bSBart Van Assche ufs->rx_sel_idx = PA_MAXDATALANES;
1125dd11376bSBart Van Assche if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX)
1126dd11376bSBart Van Assche ufs->rx_sel_idx = 0;
1127dd11376bSBart Van Assche hba->priv = (void *)ufs;
1128dd11376bSBart Van Assche hba->quirks = ufs->drv_data->quirks;
1129dd11376bSBart Van Assche }
1130dd11376bSBart Van Assche
exynos_ufs_init(struct ufs_hba * hba)1131dd11376bSBart Van Assche static int exynos_ufs_init(struct ufs_hba *hba)
1132dd11376bSBart Van Assche {
1133dd11376bSBart Van Assche struct device *dev = hba->dev;
1134dd11376bSBart Van Assche struct platform_device *pdev = to_platform_device(dev);
1135dd11376bSBart Van Assche struct exynos_ufs *ufs;
1136dd11376bSBart Van Assche int ret;
1137dd11376bSBart Van Assche
1138dd11376bSBart Van Assche ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
1139dd11376bSBart Van Assche if (!ufs)
1140dd11376bSBart Van Assche return -ENOMEM;
1141dd11376bSBart Van Assche
1142dd11376bSBart Van Assche /* exynos-specific hci */
1143dd11376bSBart Van Assche ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
1144dd11376bSBart Van Assche if (IS_ERR(ufs->reg_hci)) {
1145dd11376bSBart Van Assche dev_err(dev, "cannot ioremap for hci vendor register\n");
1146dd11376bSBart Van Assche return PTR_ERR(ufs->reg_hci);
1147dd11376bSBart Van Assche }
1148dd11376bSBart Van Assche
1149dd11376bSBart Van Assche /* unipro */
1150dd11376bSBart Van Assche ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro");
1151dd11376bSBart Van Assche if (IS_ERR(ufs->reg_unipro)) {
1152dd11376bSBart Van Assche dev_err(dev, "cannot ioremap for unipro register\n");
1153dd11376bSBart Van Assche return PTR_ERR(ufs->reg_unipro);
1154dd11376bSBart Van Assche }
1155dd11376bSBart Van Assche
1156dd11376bSBart Van Assche /* ufs protector */
1157dd11376bSBart Van Assche ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp");
1158dd11376bSBart Van Assche if (IS_ERR(ufs->reg_ufsp)) {
1159dd11376bSBart Van Assche dev_err(dev, "cannot ioremap for ufs protector register\n");
1160dd11376bSBart Van Assche return PTR_ERR(ufs->reg_ufsp);
1161dd11376bSBart Van Assche }
1162dd11376bSBart Van Assche
1163dd11376bSBart Van Assche ret = exynos_ufs_parse_dt(dev, ufs);
1164dd11376bSBart Van Assche if (ret) {
1165dd11376bSBart Van Assche dev_err(dev, "failed to get dt info.\n");
1166dd11376bSBart Van Assche goto out;
1167dd11376bSBart Van Assche }
1168dd11376bSBart Van Assche
1169dd11376bSBart Van Assche ufs->phy = devm_phy_get(dev, "ufs-phy");
1170dd11376bSBart Van Assche if (IS_ERR(ufs->phy)) {
1171dd11376bSBart Van Assche ret = PTR_ERR(ufs->phy);
1172dd11376bSBart Van Assche dev_err(dev, "failed to get ufs-phy\n");
1173dd11376bSBart Van Assche goto out;
1174dd11376bSBart Van Assche }
1175dd11376bSBart Van Assche
1176dd11376bSBart Van Assche exynos_ufs_priv_init(hba, ufs);
1177dd11376bSBart Van Assche
1178dd11376bSBart Van Assche if (ufs->drv_data->drv_init) {
1179dd11376bSBart Van Assche ret = ufs->drv_data->drv_init(dev, ufs);
1180dd11376bSBart Van Assche if (ret) {
1181dd11376bSBart Van Assche dev_err(dev, "failed to init drv-data\n");
1182dd11376bSBart Van Assche goto out;
1183dd11376bSBart Van Assche }
1184dd11376bSBart Van Assche }
1185dd11376bSBart Van Assche
1186dd11376bSBart Van Assche ret = exynos_ufs_get_clk_info(ufs);
1187dd11376bSBart Van Assche if (ret)
1188dd11376bSBart Van Assche goto out;
1189dd11376bSBart Van Assche exynos_ufs_specify_phy_time_attr(ufs);
1190dd11376bSBart Van Assche exynos_ufs_config_smu(ufs);
1191dd11376bSBart Van Assche return 0;
1192dd11376bSBart Van Assche
1193dd11376bSBart Van Assche out:
1194dd11376bSBart Van Assche hba->priv = NULL;
1195dd11376bSBart Van Assche return ret;
1196dd11376bSBart Van Assche }
1197dd11376bSBart Van Assche
exynos_ufs_host_reset(struct ufs_hba * hba)1198dd11376bSBart Van Assche static int exynos_ufs_host_reset(struct ufs_hba *hba)
1199dd11376bSBart Van Assche {
1200dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1201dd11376bSBart Van Assche unsigned long timeout = jiffies + msecs_to_jiffies(1);
1202dd11376bSBart Van Assche u32 val;
1203dd11376bSBart Van Assche int ret = 0;
1204dd11376bSBart Van Assche
1205dd11376bSBart Van Assche exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
1206dd11376bSBart Van Assche
1207dd11376bSBart Van Assche hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST);
1208dd11376bSBart Van Assche
1209dd11376bSBart Van Assche do {
1210dd11376bSBart Van Assche if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK))
1211dd11376bSBart Van Assche goto out;
1212dd11376bSBart Van Assche } while (time_before(jiffies, timeout));
1213dd11376bSBart Van Assche
1214dd11376bSBart Van Assche dev_err(hba->dev, "timeout host sw-reset\n");
1215dd11376bSBart Van Assche ret = -ETIMEDOUT;
1216dd11376bSBart Van Assche
1217dd11376bSBart Van Assche out:
1218dd11376bSBart Van Assche exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
1219dd11376bSBart Van Assche return ret;
1220dd11376bSBart Van Assche }
1221dd11376bSBart Van Assche
exynos_ufs_dev_hw_reset(struct ufs_hba * hba)1222dd11376bSBart Van Assche static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba)
1223dd11376bSBart Van Assche {
1224dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1225dd11376bSBart Van Assche
1226dd11376bSBart Van Assche hci_writel(ufs, 0 << 0, HCI_GPIO_OUT);
1227dd11376bSBart Van Assche udelay(5);
1228dd11376bSBart Van Assche hci_writel(ufs, 1 << 0, HCI_GPIO_OUT);
1229dd11376bSBart Van Assche }
1230dd11376bSBart Van Assche
exynos_ufs_pre_hibern8(struct ufs_hba * hba,enum uic_cmd_dme cmd)1231*cdcc26d7SPeter Griffin static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd)
1232dd11376bSBart Van Assche {
1233dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1234dd11376bSBart Van Assche struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1235dd11376bSBart Van Assche
1236*cdcc26d7SPeter Griffin if (cmd == UIC_CMD_DME_HIBER_EXIT) {
1237dd11376bSBart Van Assche if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1238dd11376bSBart Van Assche exynos_ufs_disable_auto_ctrl_hcc(ufs);
1239dd11376bSBart Van Assche exynos_ufs_ungate_clks(ufs);
1240dd11376bSBart Van Assche
1241dd11376bSBart Van Assche if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1242dd11376bSBart Van Assche static const unsigned int granularity_tbl[] = {
1243dd11376bSBart Van Assche 1, 4, 8, 16, 32, 100
1244dd11376bSBart Van Assche };
1245dd11376bSBart Van Assche int h8_time = attr->pa_hibern8time *
1246dd11376bSBart Van Assche granularity_tbl[attr->pa_granularity - 1];
1247dd11376bSBart Van Assche unsigned long us;
1248dd11376bSBart Van Assche s64 delta;
1249dd11376bSBart Van Assche
1250dd11376bSBart Van Assche do {
1251dd11376bSBart Van Assche delta = h8_time - ktime_us_delta(ktime_get(),
1252dd11376bSBart Van Assche ufs->entry_hibern8_t);
1253dd11376bSBart Van Assche if (delta <= 0)
1254dd11376bSBart Van Assche break;
1255dd11376bSBart Van Assche
1256dd11376bSBart Van Assche us = min_t(s64, delta, USEC_PER_MSEC);
1257dd11376bSBart Van Assche if (us >= 10)
1258dd11376bSBart Van Assche usleep_range(us, us + 10);
1259dd11376bSBart Van Assche } while (1);
1260dd11376bSBart Van Assche }
1261dd11376bSBart Van Assche }
1262dd11376bSBart Van Assche }
1263dd11376bSBart Van Assche
exynos_ufs_post_hibern8(struct ufs_hba * hba,enum uic_cmd_dme cmd)1264*cdcc26d7SPeter Griffin static void exynos_ufs_post_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd)
1265dd11376bSBart Van Assche {
1266dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1267dd11376bSBart Van Assche
1268*cdcc26d7SPeter Griffin if (cmd == UIC_CMD_DME_HIBER_EXIT) {
1269dd11376bSBart Van Assche u32 cur_mode = 0;
1270dd11376bSBart Van Assche u32 pwrmode;
1271dd11376bSBart Van Assche
1272dd11376bSBart Van Assche if (ufshcd_is_hs_mode(&ufs->dev_req_params))
1273dd11376bSBart Van Assche pwrmode = FAST_MODE;
1274dd11376bSBart Van Assche else
1275dd11376bSBart Van Assche pwrmode = SLOW_MODE;
1276dd11376bSBart Van Assche
1277dd11376bSBart Van Assche ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode);
1278dd11376bSBart Van Assche if (cur_mode != (pwrmode << 4 | pwrmode)) {
1279dd11376bSBart Van Assche dev_warn(hba->dev, "%s: power mode change\n", __func__);
1280dd11376bSBart Van Assche hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf;
1281dd11376bSBart Van Assche hba->pwr_info.pwr_tx = cur_mode & 0xf;
1282dd11376bSBart Van Assche ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
1283dd11376bSBart Van Assche }
1284dd11376bSBart Van Assche
1285dd11376bSBart Van Assche if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB))
1286dd11376bSBart Van Assche exynos_ufs_establish_connt(ufs);
1287*cdcc26d7SPeter Griffin } else if (cmd == UIC_CMD_DME_HIBER_ENTER) {
1288dd11376bSBart Van Assche ufs->entry_hibern8_t = ktime_get();
1289dd11376bSBart Van Assche exynos_ufs_gate_clks(ufs);
1290dd11376bSBart Van Assche if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1291dd11376bSBart Van Assche exynos_ufs_enable_auto_ctrl_hcc(ufs);
1292dd11376bSBart Van Assche }
1293dd11376bSBart Van Assche }
1294dd11376bSBart Van Assche
exynos_ufs_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1295dd11376bSBart Van Assche static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba,
1296dd11376bSBart Van Assche enum ufs_notify_change_status status)
1297dd11376bSBart Van Assche {
1298dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1299dd11376bSBart Van Assche int ret = 0;
1300dd11376bSBart Van Assche
1301dd11376bSBart Van Assche switch (status) {
1302dd11376bSBart Van Assche case PRE_CHANGE:
13039a80bc5dSBart Van Assche /*
13049a80bc5dSBart Van Assche * The maximum segment size must be set after scsi_host_alloc()
13059a80bc5dSBart Van Assche * has been called and before LUN scanning starts
13069a80bc5dSBart Van Assche * (ufshcd_async_scan()). Note: this callback may also be called
13079a80bc5dSBart Van Assche * from other functions than ufshcd_init().
13089a80bc5dSBart Van Assche */
130923caa33dSAvri Altman hba->host->max_segment_size = SZ_4K;
13109a80bc5dSBart Van Assche
1311dd11376bSBart Van Assche if (ufs->drv_data->pre_hce_enable) {
1312dd11376bSBart Van Assche ret = ufs->drv_data->pre_hce_enable(ufs);
1313dd11376bSBart Van Assche if (ret)
1314dd11376bSBart Van Assche return ret;
1315dd11376bSBart Van Assche }
1316dd11376bSBart Van Assche
1317dd11376bSBart Van Assche ret = exynos_ufs_host_reset(hba);
1318dd11376bSBart Van Assche if (ret)
1319dd11376bSBart Van Assche return ret;
1320dd11376bSBart Van Assche exynos_ufs_dev_hw_reset(hba);
1321dd11376bSBart Van Assche break;
1322dd11376bSBart Van Assche case POST_CHANGE:
1323dd11376bSBart Van Assche exynos_ufs_calc_pwm_clk_div(ufs);
1324dd11376bSBart Van Assche if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL))
1325dd11376bSBart Van Assche exynos_ufs_enable_auto_ctrl_hcc(ufs);
1326dd11376bSBart Van Assche
1327dd11376bSBart Van Assche if (ufs->drv_data->post_hce_enable)
1328dd11376bSBart Van Assche ret = ufs->drv_data->post_hce_enable(ufs);
1329dd11376bSBart Van Assche
1330dd11376bSBart Van Assche break;
1331dd11376bSBart Van Assche }
1332dd11376bSBart Van Assche
1333dd11376bSBart Van Assche return ret;
1334dd11376bSBart Van Assche }
1335dd11376bSBart Van Assche
exynos_ufs_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1336dd11376bSBart Van Assche static int exynos_ufs_link_startup_notify(struct ufs_hba *hba,
1337dd11376bSBart Van Assche enum ufs_notify_change_status status)
1338dd11376bSBart Van Assche {
1339dd11376bSBart Van Assche int ret = 0;
1340dd11376bSBart Van Assche
1341dd11376bSBart Van Assche switch (status) {
1342dd11376bSBart Van Assche case PRE_CHANGE:
1343dd11376bSBart Van Assche ret = exynos_ufs_pre_link(hba);
1344dd11376bSBart Van Assche break;
1345dd11376bSBart Van Assche case POST_CHANGE:
1346dd11376bSBart Van Assche ret = exynos_ufs_post_link(hba);
1347dd11376bSBart Van Assche break;
1348dd11376bSBart Van Assche }
1349dd11376bSBart Van Assche
1350dd11376bSBart Van Assche return ret;
1351dd11376bSBart Van Assche }
1352dd11376bSBart Van Assche
exynos_ufs_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)1353dd11376bSBart Van Assche static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba,
1354dd11376bSBart Van Assche enum ufs_notify_change_status status,
1355dd11376bSBart Van Assche struct ufs_pa_layer_attr *dev_max_params,
1356dd11376bSBart Van Assche struct ufs_pa_layer_attr *dev_req_params)
1357dd11376bSBart Van Assche {
1358dd11376bSBart Van Assche int ret = 0;
1359dd11376bSBart Van Assche
1360dd11376bSBart Van Assche switch (status) {
1361dd11376bSBart Van Assche case PRE_CHANGE:
1362dd11376bSBart Van Assche ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params,
1363dd11376bSBart Van Assche dev_req_params);
1364dd11376bSBart Van Assche break;
1365dd11376bSBart Van Assche case POST_CHANGE:
1366dd11376bSBart Van Assche ret = exynos_ufs_post_pwr_mode(hba, dev_req_params);
1367dd11376bSBart Van Assche break;
1368dd11376bSBart Van Assche }
1369dd11376bSBart Van Assche
1370dd11376bSBart Van Assche return ret;
1371dd11376bSBart Van Assche }
1372dd11376bSBart Van Assche
exynos_ufs_hibern8_notify(struct ufs_hba * hba,enum uic_cmd_dme cmd,enum ufs_notify_change_status notify)1373dd11376bSBart Van Assche static void exynos_ufs_hibern8_notify(struct ufs_hba *hba,
1374*cdcc26d7SPeter Griffin enum uic_cmd_dme cmd,
1375dd11376bSBart Van Assche enum ufs_notify_change_status notify)
1376dd11376bSBart Van Assche {
1377dd11376bSBart Van Assche switch ((u8)notify) {
1378dd11376bSBart Van Assche case PRE_CHANGE:
1379*cdcc26d7SPeter Griffin exynos_ufs_pre_hibern8(hba, cmd);
1380dd11376bSBart Van Assche break;
1381dd11376bSBart Van Assche case POST_CHANGE:
1382*cdcc26d7SPeter Griffin exynos_ufs_post_hibern8(hba, cmd);
1383dd11376bSBart Van Assche break;
1384dd11376bSBart Van Assche }
1385dd11376bSBart Van Assche }
1386dd11376bSBart Van Assche
exynos_ufs_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op,enum ufs_notify_change_status status)1387dd11376bSBart Van Assche static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
1388dd11376bSBart Van Assche enum ufs_notify_change_status status)
1389dd11376bSBart Van Assche {
1390dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1391dd11376bSBart Van Assche
1392dd11376bSBart Van Assche if (status == PRE_CHANGE)
1393dd11376bSBart Van Assche return 0;
1394dd11376bSBart Van Assche
1395dd11376bSBart Van Assche if (!ufshcd_is_link_active(hba))
1396dd11376bSBart Van Assche phy_power_off(ufs->phy);
1397dd11376bSBart Van Assche
1398dd11376bSBart Van Assche return 0;
1399dd11376bSBart Van Assche }
1400dd11376bSBart Van Assche
exynos_ufs_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)1401dd11376bSBart Van Assche static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
1402dd11376bSBart Van Assche {
1403dd11376bSBart Van Assche struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1404dd11376bSBart Van Assche
1405dd11376bSBart Van Assche if (!ufshcd_is_link_active(hba))
1406dd11376bSBart Van Assche phy_power_on(ufs->phy);
1407dd11376bSBart Van Assche
1408dd11376bSBart Van Assche exynos_ufs_config_smu(ufs);
1409dd11376bSBart Van Assche
1410dd11376bSBart Van Assche return 0;
1411dd11376bSBart Van Assche }
1412dd11376bSBart Van Assche
exynosauto_ufs_vh_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1413dd11376bSBart Van Assche static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba,
1414dd11376bSBart Van Assche enum ufs_notify_change_status status)
1415dd11376bSBart Van Assche {
1416dd11376bSBart Van Assche if (status == POST_CHANGE) {
1417dd11376bSBart Van Assche ufshcd_set_link_active(hba);
1418dd11376bSBart Van Assche ufshcd_set_ufs_dev_active(hba);
1419dd11376bSBart Van Assche }
1420dd11376bSBart Van Assche
1421dd11376bSBart Van Assche return 0;
1422dd11376bSBart Van Assche }
1423dd11376bSBart Van Assche
exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba * hba)1424dd11376bSBart Van Assche static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba)
1425dd11376bSBart Van Assche {
1426dd11376bSBart Van Assche u32 mbox;
1427dd11376bSBart Van Assche ktime_t start, stop;
1428dd11376bSBart Van Assche
1429dd11376bSBart Van Assche start = ktime_get();
1430dd11376bSBart Van Assche stop = ktime_add(start, ms_to_ktime(PH_READY_TIMEOUT_MS));
1431dd11376bSBart Van Assche
1432dd11376bSBart Van Assche do {
1433dd11376bSBart Van Assche mbox = ufshcd_readl(hba, PH2VH_MBOX);
1434dd11376bSBart Van Assche /* TODO: Mailbox message protocols between the PH and VHs are
1435dd11376bSBart Van Assche * not implemented yet. This will be supported later
1436dd11376bSBart Van Assche */
1437dd11376bSBart Van Assche if ((mbox & MH_MSG_MASK) == MH_MSG_PH_READY)
1438dd11376bSBart Van Assche return 0;
1439dd11376bSBart Van Assche
1440dd11376bSBart Van Assche usleep_range(40, 50);
1441dd11376bSBart Van Assche } while (ktime_before(ktime_get(), stop));
1442dd11376bSBart Van Assche
1443dd11376bSBart Van Assche return -ETIME;
1444dd11376bSBart Van Assche }
1445dd11376bSBart Van Assche
exynosauto_ufs_vh_init(struct ufs_hba * hba)1446dd11376bSBart Van Assche static int exynosauto_ufs_vh_init(struct ufs_hba *hba)
1447dd11376bSBart Van Assche {
1448dd11376bSBart Van Assche struct device *dev = hba->dev;
1449dd11376bSBart Van Assche struct platform_device *pdev = to_platform_device(dev);
1450dd11376bSBart Van Assche struct exynos_ufs *ufs;
1451dd11376bSBart Van Assche int ret;
1452dd11376bSBart Van Assche
1453dd11376bSBart Van Assche ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
1454dd11376bSBart Van Assche if (!ufs)
1455dd11376bSBart Van Assche return -ENOMEM;
1456dd11376bSBart Van Assche
1457dd11376bSBart Van Assche /* exynos-specific hci */
1458dd11376bSBart Van Assche ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
1459dd11376bSBart Van Assche if (IS_ERR(ufs->reg_hci)) {
1460dd11376bSBart Van Assche dev_err(dev, "cannot ioremap for hci vendor register\n");
1461dd11376bSBart Van Assche return PTR_ERR(ufs->reg_hci);
1462dd11376bSBart Van Assche }
1463dd11376bSBart Van Assche
1464dd11376bSBart Van Assche ret = exynosauto_ufs_vh_wait_ph_ready(hba);
1465dd11376bSBart Van Assche if (ret)
1466dd11376bSBart Van Assche return ret;
1467dd11376bSBart Van Assche
1468dd11376bSBart Van Assche ufs->drv_data = device_get_match_data(dev);
1469dd11376bSBart Van Assche if (!ufs->drv_data)
1470dd11376bSBart Van Assche return -ENODEV;
1471dd11376bSBart Van Assche
1472dd11376bSBart Van Assche exynos_ufs_priv_init(hba, ufs);
1473dd11376bSBart Van Assche
1474dd11376bSBart Van Assche return 0;
1475dd11376bSBart Van Assche }
1476dd11376bSBart Van Assche
fsd_ufs_pre_link(struct exynos_ufs * ufs)1477216f74e8SAlim Akhtar static int fsd_ufs_pre_link(struct exynos_ufs *ufs)
1478216f74e8SAlim Akhtar {
1479216f74e8SAlim Akhtar int i;
1480216f74e8SAlim Akhtar struct ufs_hba *hba = ufs->hba;
1481216f74e8SAlim Akhtar
1482216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
1483216f74e8SAlim Akhtar DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1484216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
1485216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
1486216f74e8SAlim Akhtar
1487216f74e8SAlim Akhtar for_each_ufs_tx_lane(ufs, i) {
1488216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i),
1489216f74e8SAlim Akhtar DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1490216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
1491216f74e8SAlim Akhtar }
1492216f74e8SAlim Akhtar
1493216f74e8SAlim Akhtar for_each_ufs_rx_lane(ufs, i) {
1494216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
1495216f74e8SAlim Akhtar DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1496216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
1497216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
1498216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
1499216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
1500216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
1501216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
1502216f74e8SAlim Akhtar }
1503216f74e8SAlim Akhtar
1504216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
1505216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20);
1506216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), 0x2e820183);
1507216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
1508216f74e8SAlim Akhtar
1509216f74e8SAlim Akhtar exynos_ufs_establish_connt(ufs);
1510216f74e8SAlim Akhtar
1511216f74e8SAlim Akhtar return 0;
1512216f74e8SAlim Akhtar }
1513216f74e8SAlim Akhtar
fsd_ufs_post_link(struct exynos_ufs * ufs)1514216f74e8SAlim Akhtar static int fsd_ufs_post_link(struct exynos_ufs *ufs)
1515216f74e8SAlim Akhtar {
1516216f74e8SAlim Akhtar int i;
1517216f74e8SAlim Akhtar struct ufs_hba *hba = ufs->hba;
1518216f74e8SAlim Akhtar u32 hw_cap_min_tactivate;
1519216f74e8SAlim Akhtar u32 peer_rx_min_actv_time_cap;
1520216f74e8SAlim Akhtar u32 max_rx_hibern8_time_cap;
1521216f74e8SAlim Akhtar
1522216f74e8SAlim Akhtar ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
1523216f74e8SAlim Akhtar &hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */
1524216f74e8SAlim Akhtar ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
1525216f74e8SAlim Akhtar &peer_rx_min_actv_time_cap); /* PA_TActivate */
1526216f74e8SAlim Akhtar ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
1527216f74e8SAlim Akhtar &max_rx_hibern8_time_cap); /* PA_Hibern8Time */
1528216f74e8SAlim Akhtar
1529216f74e8SAlim Akhtar if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
1530216f74e8SAlim Akhtar ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
1531216f74e8SAlim Akhtar peer_rx_min_actv_time_cap + 1);
1532216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), max_rx_hibern8_time_cap + 1);
1533216f74e8SAlim Akhtar
1534216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x01);
1535216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xFA);
1536216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x00);
1537216f74e8SAlim Akhtar
1538216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
1539216f74e8SAlim Akhtar
1540216f74e8SAlim Akhtar for_each_ufs_rx_lane(ufs, i) {
1541216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
1542216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
1543216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
1544216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
1545216f74e8SAlim Akhtar }
1546216f74e8SAlim Akhtar
1547216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
1548216f74e8SAlim Akhtar
1549216f74e8SAlim Akhtar return 0;
1550216f74e8SAlim Akhtar }
1551216f74e8SAlim Akhtar
fsd_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)1552216f74e8SAlim Akhtar static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
1553216f74e8SAlim Akhtar struct ufs_pa_layer_attr *pwr)
1554216f74e8SAlim Akhtar {
1555216f74e8SAlim Akhtar struct ufs_hba *hba = ufs->hba;
1556216f74e8SAlim Akhtar
1557216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1);
1558216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1);
1559216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
1560216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
1561216f74e8SAlim Akhtar ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
1562216f74e8SAlim Akhtar
1563216f74e8SAlim Akhtar unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0);
1564216f74e8SAlim Akhtar unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1);
1565216f74e8SAlim Akhtar unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2);
1566216f74e8SAlim Akhtar
1567216f74e8SAlim Akhtar return 0;
1568216f74e8SAlim Akhtar }
1569216f74e8SAlim Akhtar
1570dcad25cbSKrzysztof Kozlowski static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
1571dd11376bSBart Van Assche .name = "exynos_ufs",
1572dd11376bSBart Van Assche .init = exynos_ufs_init,
1573dd11376bSBart Van Assche .hce_enable_notify = exynos_ufs_hce_enable_notify,
1574dd11376bSBart Van Assche .link_startup_notify = exynos_ufs_link_startup_notify,
1575dd11376bSBart Van Assche .pwr_change_notify = exynos_ufs_pwr_change_notify,
1576dd11376bSBart Van Assche .setup_clocks = exynos_ufs_setup_clocks,
1577dd11376bSBart Van Assche .setup_xfer_req = exynos_ufs_specify_nexus_t_xfer_req,
1578dd11376bSBart Van Assche .setup_task_mgmt = exynos_ufs_specify_nexus_t_tm_req,
1579dd11376bSBart Van Assche .hibern8_notify = exynos_ufs_hibern8_notify,
1580dd11376bSBart Van Assche .suspend = exynos_ufs_suspend,
1581dd11376bSBart Van Assche .resume = exynos_ufs_resume,
1582dd11376bSBart Van Assche };
1583dd11376bSBart Van Assche
1584dd11376bSBart Van Assche static struct ufs_hba_variant_ops ufs_hba_exynosauto_vh_ops = {
1585dd11376bSBart Van Assche .name = "exynosauto_ufs_vh",
1586dd11376bSBart Van Assche .init = exynosauto_ufs_vh_init,
1587dd11376bSBart Van Assche .link_startup_notify = exynosauto_ufs_vh_link_startup_notify,
1588dd11376bSBart Van Assche };
1589dd11376bSBart Van Assche
exynos_ufs_probe(struct platform_device * pdev)1590dd11376bSBart Van Assche static int exynos_ufs_probe(struct platform_device *pdev)
1591dd11376bSBart Van Assche {
1592dd11376bSBart Van Assche int err;
1593dd11376bSBart Van Assche struct device *dev = &pdev->dev;
1594dd11376bSBart Van Assche const struct ufs_hba_variant_ops *vops = &ufs_hba_exynos_ops;
1595dd11376bSBart Van Assche const struct exynos_ufs_drv_data *drv_data =
1596dd11376bSBart Van Assche device_get_match_data(dev);
1597dd11376bSBart Van Assche
1598dd11376bSBart Van Assche if (drv_data && drv_data->vops)
1599dd11376bSBart Van Assche vops = drv_data->vops;
1600dd11376bSBart Van Assche
1601dd11376bSBart Van Assche err = ufshcd_pltfrm_init(pdev, vops);
1602dd11376bSBart Van Assche if (err)
1603dd11376bSBart Van Assche dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1604dd11376bSBart Van Assche
1605dd11376bSBart Van Assche return err;
1606dd11376bSBart Van Assche }
1607dd11376bSBart Van Assche
exynos_ufs_remove(struct platform_device * pdev)1608dd11376bSBart Van Assche static int exynos_ufs_remove(struct platform_device *pdev)
1609dd11376bSBart Van Assche {
1610dd11376bSBart Van Assche struct ufs_hba *hba = platform_get_drvdata(pdev);
16113d73b200SChanho Park struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1612dd11376bSBart Van Assche
1613dd11376bSBart Van Assche pm_runtime_get_sync(&(pdev)->dev);
1614dd11376bSBart Van Assche ufshcd_remove(hba);
16153d73b200SChanho Park
16163d73b200SChanho Park phy_power_off(ufs->phy);
16173d73b200SChanho Park phy_exit(ufs->phy);
16183d73b200SChanho Park
1619dd11376bSBart Van Assche return 0;
1620dd11376bSBart Van Assche }
1621dd11376bSBart Van Assche
1622dd11376bSBart Van Assche static struct exynos_ufs_uic_attr exynos7_uic_attr = {
1623dd11376bSBart Van Assche .tx_trailingclks = 0x10,
1624dd11376bSBart Van Assche .tx_dif_p_nsec = 3000000, /* unit: ns */
1625dd11376bSBart Van Assche .tx_dif_n_nsec = 1000000, /* unit: ns */
1626dd11376bSBart Van Assche .tx_high_z_cnt_nsec = 20000, /* unit: ns */
1627dd11376bSBart Van Assche .tx_base_unit_nsec = 100000, /* unit: ns */
1628dd11376bSBart Van Assche .tx_gran_unit_nsec = 4000, /* unit: ns */
1629dd11376bSBart Van Assche .tx_sleep_cnt = 1000, /* unit: ns */
1630dd11376bSBart Van Assche .tx_min_activatetime = 0xa,
1631dd11376bSBart Van Assche .rx_filler_enable = 0x2,
1632dd11376bSBart Van Assche .rx_dif_p_nsec = 1000000, /* unit: ns */
1633dd11376bSBart Van Assche .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
1634dd11376bSBart Van Assche .rx_base_unit_nsec = 100000, /* unit: ns */
1635dd11376bSBart Van Assche .rx_gran_unit_nsec = 4000, /* unit: ns */
1636dd11376bSBart Van Assche .rx_sleep_cnt = 1280, /* unit: ns */
1637dd11376bSBart Van Assche .rx_stall_cnt = 320, /* unit: ns */
1638dd11376bSBart Van Assche .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
1639dd11376bSBart Van Assche .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
1640dd11376bSBart Van Assche .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
1641dd11376bSBart Van Assche .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
1642dd11376bSBart Van Assche .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
1643dd11376bSBart Van Assche .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
1644dd11376bSBart Van Assche .pa_dbg_option_suite = 0x30103,
1645dd11376bSBart Van Assche };
1646dd11376bSBart Van Assche
1647dcad25cbSKrzysztof Kozlowski static const struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
1648dd11376bSBart Van Assche .uic_attr = &exynos7_uic_attr,
1649dd11376bSBart Van Assche .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1650dd11376bSBart Van Assche UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
1651dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1652dd11376bSBart Van Assche UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
1653dd11376bSBart Van Assche .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
1654dd11376bSBart Van Assche EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
1655dd11376bSBart Van Assche EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
1656dd11376bSBart Van Assche .drv_init = exynosauto_ufs_drv_init,
1657dd11376bSBart Van Assche .post_hce_enable = exynosauto_ufs_post_hce_enable,
1658dd11376bSBart Van Assche .pre_link = exynosauto_ufs_pre_link,
1659dd11376bSBart Van Assche .pre_pwr_change = exynosauto_ufs_pre_pwr_change,
1660dd11376bSBart Van Assche .post_pwr_change = exynosauto_ufs_post_pwr_change,
1661dd11376bSBart Van Assche };
1662dd11376bSBart Van Assche
1663dcad25cbSKrzysztof Kozlowski static const struct exynos_ufs_drv_data exynosauto_ufs_vh_drvs = {
1664dd11376bSBart Van Assche .vops = &ufs_hba_exynosauto_vh_ops,
1665dd11376bSBart Van Assche .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1666dd11376bSBart Van Assche UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
1667dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1668dd11376bSBart Van Assche UFSHCI_QUIRK_BROKEN_HCE |
1669dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_UIC_CMD |
1670dd11376bSBart Van Assche UFSHCD_QUIRK_SKIP_PH_CONFIGURATION |
1671dd11376bSBart Van Assche UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
1672dd11376bSBart Van Assche .opts = EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
1673dd11376bSBart Van Assche };
1674dd11376bSBart Van Assche
1675dcad25cbSKrzysztof Kozlowski static const struct exynos_ufs_drv_data exynos_ufs_drvs = {
1676dd11376bSBart Van Assche .uic_attr = &exynos7_uic_attr,
1677dd11376bSBart Van Assche .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1678dd11376bSBart Van Assche UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
1679dd11376bSBart Van Assche UFSHCI_QUIRK_BROKEN_HCE |
1680dd11376bSBart Van Assche UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
1681dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1682dd11376bSBart Van Assche UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL |
1683dd11376bSBart Van Assche UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING |
168486bd0c4aSBart Van Assche UFSHCD_QUIRK_4KB_DMA_ALIGNMENT,
1685dd11376bSBart Van Assche .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
1686dd11376bSBart Van Assche EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
1687dd11376bSBart Van Assche EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX |
1688dd11376bSBart Van Assche EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB |
1689dd11376bSBart Van Assche EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER,
1690dd11376bSBart Van Assche .drv_init = exynos7_ufs_drv_init,
1691dd11376bSBart Van Assche .pre_link = exynos7_ufs_pre_link,
1692dd11376bSBart Van Assche .post_link = exynos7_ufs_post_link,
1693dd11376bSBart Van Assche .pre_pwr_change = exynos7_ufs_pre_pwr_change,
1694dd11376bSBart Van Assche .post_pwr_change = exynos7_ufs_post_pwr_change,
1695dd11376bSBart Van Assche };
1696dd11376bSBart Van Assche
1697216f74e8SAlim Akhtar static struct exynos_ufs_uic_attr fsd_uic_attr = {
1698216f74e8SAlim Akhtar .tx_trailingclks = 0x10,
1699216f74e8SAlim Akhtar .tx_dif_p_nsec = 3000000, /* unit: ns */
1700216f74e8SAlim Akhtar .tx_dif_n_nsec = 1000000, /* unit: ns */
1701216f74e8SAlim Akhtar .tx_high_z_cnt_nsec = 20000, /* unit: ns */
1702216f74e8SAlim Akhtar .tx_base_unit_nsec = 100000, /* unit: ns */
1703216f74e8SAlim Akhtar .tx_gran_unit_nsec = 4000, /* unit: ns */
1704216f74e8SAlim Akhtar .tx_sleep_cnt = 1000, /* unit: ns */
1705216f74e8SAlim Akhtar .tx_min_activatetime = 0xa,
1706216f74e8SAlim Akhtar .rx_filler_enable = 0x2,
1707216f74e8SAlim Akhtar .rx_dif_p_nsec = 1000000, /* unit: ns */
1708216f74e8SAlim Akhtar .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
1709216f74e8SAlim Akhtar .rx_base_unit_nsec = 100000, /* unit: ns */
1710216f74e8SAlim Akhtar .rx_gran_unit_nsec = 4000, /* unit: ns */
1711216f74e8SAlim Akhtar .rx_sleep_cnt = 1280, /* unit: ns */
1712216f74e8SAlim Akhtar .rx_stall_cnt = 320, /* unit: ns */
1713216f74e8SAlim Akhtar .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
1714216f74e8SAlim Akhtar .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
1715216f74e8SAlim Akhtar .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
1716216f74e8SAlim Akhtar .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
1717216f74e8SAlim Akhtar .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
1718216f74e8SAlim Akhtar .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
1719216f74e8SAlim Akhtar .pa_dbg_option_suite = 0x2E820183,
1720216f74e8SAlim Akhtar };
1721216f74e8SAlim Akhtar
172237dd4ab1SAlim Akhtar static const struct exynos_ufs_drv_data fsd_ufs_drvs = {
1723216f74e8SAlim Akhtar .uic_attr = &fsd_uic_attr,
1724216f74e8SAlim Akhtar .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1725216f74e8SAlim Akhtar UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
1726216f74e8SAlim Akhtar UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1727216f74e8SAlim Akhtar UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING |
1728216f74e8SAlim Akhtar UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
1729216f74e8SAlim Akhtar .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
1730216f74e8SAlim Akhtar EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
1731216f74e8SAlim Akhtar EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
1732216f74e8SAlim Akhtar EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
1733216f74e8SAlim Akhtar .pre_link = fsd_ufs_pre_link,
1734216f74e8SAlim Akhtar .post_link = fsd_ufs_post_link,
1735216f74e8SAlim Akhtar .pre_pwr_change = fsd_ufs_pre_pwr_change,
1736216f74e8SAlim Akhtar };
1737216f74e8SAlim Akhtar
1738dd11376bSBart Van Assche static const struct of_device_id exynos_ufs_of_match[] = {
1739dd11376bSBart Van Assche { .compatible = "samsung,exynos7-ufs",
1740dd11376bSBart Van Assche .data = &exynos_ufs_drvs },
1741dd11376bSBart Van Assche { .compatible = "samsung,exynosautov9-ufs",
1742dd11376bSBart Van Assche .data = &exynosauto_ufs_drvs },
1743dd11376bSBart Van Assche { .compatible = "samsung,exynosautov9-ufs-vh",
1744dd11376bSBart Van Assche .data = &exynosauto_ufs_vh_drvs },
1745216f74e8SAlim Akhtar { .compatible = "tesla,fsd-ufs",
1746216f74e8SAlim Akhtar .data = &fsd_ufs_drvs },
1747dd11376bSBart Van Assche {},
1748dd11376bSBart Van Assche };
1749dd11376bSBart Van Assche
1750dd11376bSBart Van Assche static const struct dev_pm_ops exynos_ufs_pm_ops = {
1751dd11376bSBart Van Assche SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
1752dd11376bSBart Van Assche SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1753dd11376bSBart Van Assche .prepare = ufshcd_suspend_prepare,
1754dd11376bSBart Van Assche .complete = ufshcd_resume_complete,
1755dd11376bSBart Van Assche };
1756dd11376bSBart Van Assche
1757dd11376bSBart Van Assche static struct platform_driver exynos_ufs_pltform = {
1758dd11376bSBart Van Assche .probe = exynos_ufs_probe,
1759dd11376bSBart Van Assche .remove = exynos_ufs_remove,
1760dd11376bSBart Van Assche .driver = {
1761dd11376bSBart Van Assche .name = "exynos-ufshc",
1762dd11376bSBart Van Assche .pm = &exynos_ufs_pm_ops,
1763cd6a6893SKrzysztof Kozlowski .of_match_table = exynos_ufs_of_match,
1764dd11376bSBart Van Assche },
1765dd11376bSBart Van Assche };
1766dd11376bSBart Van Assche module_platform_driver(exynos_ufs_pltform);
1767dd11376bSBart Van Assche
1768dd11376bSBart Van Assche MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>");
1769dd11376bSBart Van Assche MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>");
1770dd11376bSBart Van Assche MODULE_DESCRIPTION("Exynos UFS HCI Driver");
1771dd11376bSBart Van Assche MODULE_LICENSE("GPL v2");
1772