1 /* sunzilog.c: Zilog serial driver for Sparc systems. 2 * 3 * Driver for Zilog serial chips found on Sun workstations and 4 * servers. This driver could actually be made more generic. 5 * 6 * This is based on the old drivers/sbus/char/zs.c code. A lot 7 * of code has been simply moved over directly from there but 8 * much has been rewritten. Credits therefore go out to Eddie 9 * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their 10 * work there. 11 * 12 * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net) 13 */ 14 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/errno.h> 18 #include <linux/delay.h> 19 #include <linux/tty.h> 20 #include <linux/tty_flip.h> 21 #include <linux/major.h> 22 #include <linux/string.h> 23 #include <linux/ptrace.h> 24 #include <linux/ioport.h> 25 #include <linux/slab.h> 26 #include <linux/circ_buf.h> 27 #include <linux/serial.h> 28 #include <linux/sysrq.h> 29 #include <linux/console.h> 30 #include <linux/spinlock.h> 31 #ifdef CONFIG_SERIO 32 #include <linux/serio.h> 33 #endif 34 #include <linux/init.h> 35 #include <linux/of_device.h> 36 37 #include <asm/io.h> 38 #include <asm/irq.h> 39 #include <asm/prom.h> 40 #include <asm/setup.h> 41 42 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 43 #define SUPPORT_SYSRQ 44 #endif 45 46 #include <linux/serial_core.h> 47 #include <linux/sunserialcore.h> 48 49 #include "sunzilog.h" 50 51 /* On 32-bit sparcs we need to delay after register accesses 52 * to accommodate sun4 systems, but we do not need to flush writes. 53 * On 64-bit sparc we only need to flush single writes to ensure 54 * completion. 55 */ 56 #ifndef CONFIG_SPARC64 57 #define ZSDELAY() udelay(5) 58 #define ZSDELAY_LONG() udelay(20) 59 #define ZS_WSYNC(channel) do { } while (0) 60 #else 61 #define ZSDELAY() 62 #define ZSDELAY_LONG() 63 #define ZS_WSYNC(__channel) \ 64 readb(&((__channel)->control)) 65 #endif 66 67 #define ZS_CLOCK 4915200 /* Zilog input clock rate. */ 68 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */ 69 70 /* 71 * We wrap our port structure around the generic uart_port. 72 */ 73 struct uart_sunzilog_port { 74 struct uart_port port; 75 76 /* IRQ servicing chain. */ 77 struct uart_sunzilog_port *next; 78 79 /* Current values of Zilog write registers. */ 80 unsigned char curregs[NUM_ZSREGS]; 81 82 unsigned int flags; 83 #define SUNZILOG_FLAG_CONS_KEYB 0x00000001 84 #define SUNZILOG_FLAG_CONS_MOUSE 0x00000002 85 #define SUNZILOG_FLAG_IS_CONS 0x00000004 86 #define SUNZILOG_FLAG_IS_KGDB 0x00000008 87 #define SUNZILOG_FLAG_MODEM_STATUS 0x00000010 88 #define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020 89 #define SUNZILOG_FLAG_REGS_HELD 0x00000040 90 #define SUNZILOG_FLAG_TX_STOPPED 0x00000080 91 #define SUNZILOG_FLAG_TX_ACTIVE 0x00000100 92 #define SUNZILOG_FLAG_ESCC 0x00000200 93 #define SUNZILOG_FLAG_ISR_HANDLER 0x00000400 94 95 unsigned int cflag; 96 97 unsigned char parity_mask; 98 unsigned char prev_status; 99 100 #ifdef CONFIG_SERIO 101 struct serio serio; 102 int serio_open; 103 #endif 104 }; 105 106 static void sunzilog_putchar(struct uart_port *port, int ch); 107 108 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase)) 109 #define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT)) 110 111 #define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB) 112 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE) 113 #define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS) 114 #define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB) 115 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS) 116 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A) 117 #define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD) 118 #define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED) 119 #define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE) 120 121 /* Reading and writing Zilog8530 registers. The delays are to make this 122 * driver work on the Sun4 which needs a settling delay after each chip 123 * register access, other machines handle this in hardware via auxiliary 124 * flip-flops which implement the settle time we do in software. 125 * 126 * The port lock must be held and local IRQs must be disabled 127 * when {read,write}_zsreg is invoked. 128 */ 129 static unsigned char read_zsreg(struct zilog_channel __iomem *channel, 130 unsigned char reg) 131 { 132 unsigned char retval; 133 134 writeb(reg, &channel->control); 135 ZSDELAY(); 136 retval = readb(&channel->control); 137 ZSDELAY(); 138 139 return retval; 140 } 141 142 static void write_zsreg(struct zilog_channel __iomem *channel, 143 unsigned char reg, unsigned char value) 144 { 145 writeb(reg, &channel->control); 146 ZSDELAY(); 147 writeb(value, &channel->control); 148 ZSDELAY(); 149 } 150 151 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel) 152 { 153 int i; 154 155 for (i = 0; i < 32; i++) { 156 unsigned char regval; 157 158 regval = readb(&channel->control); 159 ZSDELAY(); 160 if (regval & Rx_CH_AV) 161 break; 162 163 regval = read_zsreg(channel, R1); 164 readb(&channel->data); 165 ZSDELAY(); 166 167 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) { 168 writeb(ERR_RES, &channel->control); 169 ZSDELAY(); 170 ZS_WSYNC(channel); 171 } 172 } 173 } 174 175 /* This function must only be called when the TX is not busy. The UART 176 * port lock must be held and local interrupts disabled. 177 */ 178 static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs) 179 { 180 int i; 181 int escc; 182 unsigned char r15; 183 184 /* Let pending transmits finish. */ 185 for (i = 0; i < 1000; i++) { 186 unsigned char stat = read_zsreg(channel, R1); 187 if (stat & ALL_SNT) 188 break; 189 udelay(100); 190 } 191 192 writeb(ERR_RES, &channel->control); 193 ZSDELAY(); 194 ZS_WSYNC(channel); 195 196 sunzilog_clear_fifo(channel); 197 198 /* Disable all interrupts. */ 199 write_zsreg(channel, R1, 200 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); 201 202 /* Set parity, sync config, stop bits, and clock divisor. */ 203 write_zsreg(channel, R4, regs[R4]); 204 205 /* Set misc. TX/RX control bits. */ 206 write_zsreg(channel, R10, regs[R10]); 207 208 /* Set TX/RX controls sans the enable bits. */ 209 write_zsreg(channel, R3, regs[R3] & ~RxENAB); 210 write_zsreg(channel, R5, regs[R5] & ~TxENAB); 211 212 /* Synchronous mode config. */ 213 write_zsreg(channel, R6, regs[R6]); 214 write_zsreg(channel, R7, regs[R7]); 215 216 /* Don't mess with the interrupt vector (R2, unused by us) and 217 * master interrupt control (R9). We make sure this is setup 218 * properly at probe time then never touch it again. 219 */ 220 221 /* Disable baud generator. */ 222 write_zsreg(channel, R14, regs[R14] & ~BRENAB); 223 224 /* Clock mode control. */ 225 write_zsreg(channel, R11, regs[R11]); 226 227 /* Lower and upper byte of baud rate generator divisor. */ 228 write_zsreg(channel, R12, regs[R12]); 229 write_zsreg(channel, R13, regs[R13]); 230 231 /* Now rewrite R14, with BRENAB (if set). */ 232 write_zsreg(channel, R14, regs[R14]); 233 234 /* External status interrupt control. */ 235 write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN); 236 237 /* ESCC Extension Register */ 238 r15 = read_zsreg(channel, R15); 239 if (r15 & 0x01) { 240 write_zsreg(channel, R7, regs[R7p]); 241 242 /* External status interrupt and FIFO control. */ 243 write_zsreg(channel, R15, regs[R15] & ~WR7pEN); 244 escc = 1; 245 } else { 246 /* Clear FIFO bit case it is an issue */ 247 regs[R15] &= ~FIFOEN; 248 escc = 0; 249 } 250 251 /* Reset external status interrupts. */ 252 write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */ 253 write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */ 254 255 /* Rewrite R3/R5, this time without enables masked. */ 256 write_zsreg(channel, R3, regs[R3]); 257 write_zsreg(channel, R5, regs[R5]); 258 259 /* Rewrite R1, this time without IRQ enabled masked. */ 260 write_zsreg(channel, R1, regs[R1]); 261 262 return escc; 263 } 264 265 /* Reprogram the Zilog channel HW registers with the copies found in the 266 * software state struct. If the transmitter is busy, we defer this update 267 * until the next TX complete interrupt. Else, we do it right now. 268 * 269 * The UART port lock must be held and local interrupts disabled. 270 */ 271 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up, 272 struct zilog_channel __iomem *channel) 273 { 274 if (!ZS_REGS_HELD(up)) { 275 if (ZS_TX_ACTIVE(up)) { 276 up->flags |= SUNZILOG_FLAG_REGS_HELD; 277 } else { 278 __load_zsregs(channel, up->curregs); 279 } 280 } 281 } 282 283 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up) 284 { 285 unsigned int cur_cflag = up->cflag; 286 int brg, new_baud; 287 288 up->cflag &= ~CBAUD; 289 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud); 290 291 brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 292 up->curregs[R12] = (brg & 0xff); 293 up->curregs[R13] = (brg >> 8) & 0xff; 294 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port)); 295 } 296 297 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up, 298 unsigned char ch, int is_break) 299 { 300 if (ZS_IS_KEYB(up)) { 301 /* Stop-A is handled by drivers/char/keyboard.c now. */ 302 #ifdef CONFIG_SERIO 303 if (up->serio_open) 304 serio_interrupt(&up->serio, ch, 0); 305 #endif 306 } else if (ZS_IS_MOUSE(up)) { 307 int ret = suncore_mouse_baud_detection(ch, is_break); 308 309 switch (ret) { 310 case 2: 311 sunzilog_change_mouse_baud(up); 312 /* fallthru */ 313 case 1: 314 break; 315 316 case 0: 317 #ifdef CONFIG_SERIO 318 if (up->serio_open) 319 serio_interrupt(&up->serio, ch, 0); 320 #endif 321 break; 322 }; 323 } 324 } 325 326 static struct tty_struct * 327 sunzilog_receive_chars(struct uart_sunzilog_port *up, 328 struct zilog_channel __iomem *channel) 329 { 330 struct tty_port *port = NULL; 331 struct tty_struct *tty; 332 unsigned char ch, r1, flag; 333 334 tty = NULL; 335 if (up->port.state != NULL) { /* Unopened serial console */ 336 port = &up->port.state->port; 337 tty = port->tty; /* mouse => tty is NULL */ 338 } 339 340 for (;;) { 341 342 r1 = read_zsreg(channel, R1); 343 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { 344 writeb(ERR_RES, &channel->control); 345 ZSDELAY(); 346 ZS_WSYNC(channel); 347 } 348 349 ch = readb(&channel->control); 350 ZSDELAY(); 351 352 /* This funny hack depends upon BRK_ABRT not interfering 353 * with the other bits we care about in R1. 354 */ 355 if (ch & BRK_ABRT) 356 r1 |= BRK_ABRT; 357 358 if (!(ch & Rx_CH_AV)) 359 break; 360 361 ch = readb(&channel->data); 362 ZSDELAY(); 363 364 ch &= up->parity_mask; 365 366 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) { 367 sunzilog_kbdms_receive_chars(up, ch, 0); 368 continue; 369 } 370 371 /* A real serial line, record the character and status. */ 372 flag = TTY_NORMAL; 373 up->port.icount.rx++; 374 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) { 375 if (r1 & BRK_ABRT) { 376 r1 &= ~(PAR_ERR | CRC_ERR); 377 up->port.icount.brk++; 378 if (uart_handle_break(&up->port)) 379 continue; 380 } 381 else if (r1 & PAR_ERR) 382 up->port.icount.parity++; 383 else if (r1 & CRC_ERR) 384 up->port.icount.frame++; 385 if (r1 & Rx_OVR) 386 up->port.icount.overrun++; 387 r1 &= up->port.read_status_mask; 388 if (r1 & BRK_ABRT) 389 flag = TTY_BREAK; 390 else if (r1 & PAR_ERR) 391 flag = TTY_PARITY; 392 else if (r1 & CRC_ERR) 393 flag = TTY_FRAME; 394 } 395 if (uart_handle_sysrq_char(&up->port, ch)) 396 continue; 397 398 if (up->port.ignore_status_mask == 0xff || 399 (r1 & up->port.ignore_status_mask) == 0) { 400 tty_insert_flip_char(port, ch, flag); 401 } 402 if (r1 & Rx_OVR) 403 tty_insert_flip_char(port, 0, TTY_OVERRUN); 404 } 405 406 return tty; 407 } 408 409 static void sunzilog_status_handle(struct uart_sunzilog_port *up, 410 struct zilog_channel __iomem *channel) 411 { 412 unsigned char status; 413 414 status = readb(&channel->control); 415 ZSDELAY(); 416 417 writeb(RES_EXT_INT, &channel->control); 418 ZSDELAY(); 419 ZS_WSYNC(channel); 420 421 if (status & BRK_ABRT) { 422 if (ZS_IS_MOUSE(up)) 423 sunzilog_kbdms_receive_chars(up, 0, 1); 424 if (ZS_IS_CONS(up)) { 425 /* Wait for BREAK to deassert to avoid potentially 426 * confusing the PROM. 427 */ 428 while (1) { 429 status = readb(&channel->control); 430 ZSDELAY(); 431 if (!(status & BRK_ABRT)) 432 break; 433 } 434 sun_do_break(); 435 return; 436 } 437 } 438 439 if (ZS_WANTS_MODEM_STATUS(up)) { 440 if (status & SYNC) 441 up->port.icount.dsr++; 442 443 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. 444 * But it does not tell us which bit has changed, we have to keep 445 * track of this ourselves. 446 */ 447 if ((status ^ up->prev_status) ^ DCD) 448 uart_handle_dcd_change(&up->port, 449 (status & DCD)); 450 if ((status ^ up->prev_status) ^ CTS) 451 uart_handle_cts_change(&up->port, 452 (status & CTS)); 453 454 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 455 } 456 457 up->prev_status = status; 458 } 459 460 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up, 461 struct zilog_channel __iomem *channel) 462 { 463 struct circ_buf *xmit; 464 465 if (ZS_IS_CONS(up)) { 466 unsigned char status = readb(&channel->control); 467 ZSDELAY(); 468 469 /* TX still busy? Just wait for the next TX done interrupt. 470 * 471 * It can occur because of how we do serial console writes. It would 472 * be nice to transmit console writes just like we normally would for 473 * a TTY line. (ie. buffered and TX interrupt driven). That is not 474 * easy because console writes cannot sleep. One solution might be 475 * to poll on enough port->xmit space becoming free. -DaveM 476 */ 477 if (!(status & Tx_BUF_EMP)) 478 return; 479 } 480 481 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE; 482 483 if (ZS_REGS_HELD(up)) { 484 __load_zsregs(channel, up->curregs); 485 up->flags &= ~SUNZILOG_FLAG_REGS_HELD; 486 } 487 488 if (ZS_TX_STOPPED(up)) { 489 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED; 490 goto ack_tx_int; 491 } 492 493 if (up->port.x_char) { 494 up->flags |= SUNZILOG_FLAG_TX_ACTIVE; 495 writeb(up->port.x_char, &channel->data); 496 ZSDELAY(); 497 ZS_WSYNC(channel); 498 499 up->port.icount.tx++; 500 up->port.x_char = 0; 501 return; 502 } 503 504 if (up->port.state == NULL) 505 goto ack_tx_int; 506 xmit = &up->port.state->xmit; 507 if (uart_circ_empty(xmit)) 508 goto ack_tx_int; 509 510 if (uart_tx_stopped(&up->port)) 511 goto ack_tx_int; 512 513 up->flags |= SUNZILOG_FLAG_TX_ACTIVE; 514 writeb(xmit->buf[xmit->tail], &channel->data); 515 ZSDELAY(); 516 ZS_WSYNC(channel); 517 518 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 519 up->port.icount.tx++; 520 521 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 522 uart_write_wakeup(&up->port); 523 524 return; 525 526 ack_tx_int: 527 writeb(RES_Tx_P, &channel->control); 528 ZSDELAY(); 529 ZS_WSYNC(channel); 530 } 531 532 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id) 533 { 534 struct uart_sunzilog_port *up = dev_id; 535 536 while (up) { 537 struct zilog_channel __iomem *channel 538 = ZILOG_CHANNEL_FROM_PORT(&up->port); 539 struct tty_struct *tty; 540 unsigned char r3; 541 542 spin_lock(&up->port.lock); 543 r3 = read_zsreg(channel, R3); 544 545 /* Channel A */ 546 tty = NULL; 547 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { 548 writeb(RES_H_IUS, &channel->control); 549 ZSDELAY(); 550 ZS_WSYNC(channel); 551 552 if (r3 & CHARxIP) 553 tty = sunzilog_receive_chars(up, channel); 554 if (r3 & CHAEXT) 555 sunzilog_status_handle(up, channel); 556 if (r3 & CHATxIP) 557 sunzilog_transmit_chars(up, channel); 558 } 559 spin_unlock(&up->port.lock); 560 561 if (tty) 562 tty_flip_buffer_push(tty); 563 564 /* Channel B */ 565 up = up->next; 566 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 567 568 spin_lock(&up->port.lock); 569 tty = NULL; 570 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 571 writeb(RES_H_IUS, &channel->control); 572 ZSDELAY(); 573 ZS_WSYNC(channel); 574 575 if (r3 & CHBRxIP) 576 tty = sunzilog_receive_chars(up, channel); 577 if (r3 & CHBEXT) 578 sunzilog_status_handle(up, channel); 579 if (r3 & CHBTxIP) 580 sunzilog_transmit_chars(up, channel); 581 } 582 spin_unlock(&up->port.lock); 583 584 if (tty) 585 tty_flip_buffer_push(tty); 586 587 up = up->next; 588 } 589 590 return IRQ_HANDLED; 591 } 592 593 /* A convenient way to quickly get R0 status. The caller must _not_ hold the 594 * port lock, it is acquired here. 595 */ 596 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port) 597 { 598 struct zilog_channel __iomem *channel; 599 unsigned char status; 600 601 channel = ZILOG_CHANNEL_FROM_PORT(port); 602 status = readb(&channel->control); 603 ZSDELAY(); 604 605 return status; 606 } 607 608 /* The port lock is not held. */ 609 static unsigned int sunzilog_tx_empty(struct uart_port *port) 610 { 611 unsigned long flags; 612 unsigned char status; 613 unsigned int ret; 614 615 spin_lock_irqsave(&port->lock, flags); 616 617 status = sunzilog_read_channel_status(port); 618 619 spin_unlock_irqrestore(&port->lock, flags); 620 621 if (status & Tx_BUF_EMP) 622 ret = TIOCSER_TEMT; 623 else 624 ret = 0; 625 626 return ret; 627 } 628 629 /* The port lock is held and interrupts are disabled. */ 630 static unsigned int sunzilog_get_mctrl(struct uart_port *port) 631 { 632 unsigned char status; 633 unsigned int ret; 634 635 status = sunzilog_read_channel_status(port); 636 637 ret = 0; 638 if (status & DCD) 639 ret |= TIOCM_CAR; 640 if (status & SYNC) 641 ret |= TIOCM_DSR; 642 if (status & CTS) 643 ret |= TIOCM_CTS; 644 645 return ret; 646 } 647 648 /* The port lock is held and interrupts are disabled. */ 649 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl) 650 { 651 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port; 652 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port); 653 unsigned char set_bits, clear_bits; 654 655 set_bits = clear_bits = 0; 656 657 if (mctrl & TIOCM_RTS) 658 set_bits |= RTS; 659 else 660 clear_bits |= RTS; 661 if (mctrl & TIOCM_DTR) 662 set_bits |= DTR; 663 else 664 clear_bits |= DTR; 665 666 /* NOTE: Not subject to 'transmitter active' rule. */ 667 up->curregs[R5] |= set_bits; 668 up->curregs[R5] &= ~clear_bits; 669 write_zsreg(channel, R5, up->curregs[R5]); 670 } 671 672 /* The port lock is held and interrupts are disabled. */ 673 static void sunzilog_stop_tx(struct uart_port *port) 674 { 675 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port; 676 677 up->flags |= SUNZILOG_FLAG_TX_STOPPED; 678 } 679 680 /* The port lock is held and interrupts are disabled. */ 681 static void sunzilog_start_tx(struct uart_port *port) 682 { 683 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port; 684 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port); 685 unsigned char status; 686 687 up->flags |= SUNZILOG_FLAG_TX_ACTIVE; 688 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED; 689 690 status = readb(&channel->control); 691 ZSDELAY(); 692 693 /* TX busy? Just wait for the TX done interrupt. */ 694 if (!(status & Tx_BUF_EMP)) 695 return; 696 697 /* Send the first character to jump-start the TX done 698 * IRQ sending engine. 699 */ 700 if (port->x_char) { 701 writeb(port->x_char, &channel->data); 702 ZSDELAY(); 703 ZS_WSYNC(channel); 704 705 port->icount.tx++; 706 port->x_char = 0; 707 } else { 708 struct circ_buf *xmit = &port->state->xmit; 709 710 writeb(xmit->buf[xmit->tail], &channel->data); 711 ZSDELAY(); 712 ZS_WSYNC(channel); 713 714 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 715 port->icount.tx++; 716 717 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 718 uart_write_wakeup(&up->port); 719 } 720 } 721 722 /* The port lock is held. */ 723 static void sunzilog_stop_rx(struct uart_port *port) 724 { 725 struct uart_sunzilog_port *up = UART_ZILOG(port); 726 struct zilog_channel __iomem *channel; 727 728 if (ZS_IS_CONS(up)) 729 return; 730 731 channel = ZILOG_CHANNEL_FROM_PORT(port); 732 733 /* Disable all RX interrupts. */ 734 up->curregs[R1] &= ~RxINT_MASK; 735 sunzilog_maybe_update_regs(up, channel); 736 } 737 738 /* The port lock is held. */ 739 static void sunzilog_enable_ms(struct uart_port *port) 740 { 741 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port; 742 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port); 743 unsigned char new_reg; 744 745 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE); 746 if (new_reg != up->curregs[R15]) { 747 up->curregs[R15] = new_reg; 748 749 /* NOTE: Not subject to 'transmitter active' rule. */ 750 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN); 751 } 752 } 753 754 /* The port lock is not held. */ 755 static void sunzilog_break_ctl(struct uart_port *port, int break_state) 756 { 757 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port; 758 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port); 759 unsigned char set_bits, clear_bits, new_reg; 760 unsigned long flags; 761 762 set_bits = clear_bits = 0; 763 764 if (break_state) 765 set_bits |= SND_BRK; 766 else 767 clear_bits |= SND_BRK; 768 769 spin_lock_irqsave(&port->lock, flags); 770 771 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; 772 if (new_reg != up->curregs[R5]) { 773 up->curregs[R5] = new_reg; 774 775 /* NOTE: Not subject to 'transmitter active' rule. */ 776 write_zsreg(channel, R5, up->curregs[R5]); 777 } 778 779 spin_unlock_irqrestore(&port->lock, flags); 780 } 781 782 static void __sunzilog_startup(struct uart_sunzilog_port *up) 783 { 784 struct zilog_channel __iomem *channel; 785 786 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 787 up->prev_status = readb(&channel->control); 788 789 /* Enable receiver and transmitter. */ 790 up->curregs[R3] |= RxENAB; 791 up->curregs[R5] |= TxENAB; 792 793 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; 794 sunzilog_maybe_update_regs(up, channel); 795 } 796 797 static int sunzilog_startup(struct uart_port *port) 798 { 799 struct uart_sunzilog_port *up = UART_ZILOG(port); 800 unsigned long flags; 801 802 if (ZS_IS_CONS(up)) 803 return 0; 804 805 spin_lock_irqsave(&port->lock, flags); 806 __sunzilog_startup(up); 807 spin_unlock_irqrestore(&port->lock, flags); 808 return 0; 809 } 810 811 /* 812 * The test for ZS_IS_CONS is explained by the following e-mail: 813 ***** 814 * From: Russell King <rmk@arm.linux.org.uk> 815 * Date: Sun, 8 Dec 2002 10:18:38 +0000 816 * 817 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote: 818 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument, 819 * > and I noticed that something is not right with reference 820 * > counting in this case. It seems that when the console 821 * > is open by kernel initially, this is not accounted 822 * > as an open, and uart_startup is not called. 823 * 824 * That is correct. We are unable to call uart_startup when the serial 825 * console is initialised because it may need to allocate memory (as 826 * request_irq does) and the memory allocators may not have been 827 * initialised. 828 * 829 * 1. initialise the port into a state where it can send characters in the 830 * console write method. 831 * 832 * 2. don't do the actual hardware shutdown in your shutdown() method (but 833 * do the normal software shutdown - ie, free irqs etc) 834 ***** 835 */ 836 static void sunzilog_shutdown(struct uart_port *port) 837 { 838 struct uart_sunzilog_port *up = UART_ZILOG(port); 839 struct zilog_channel __iomem *channel; 840 unsigned long flags; 841 842 if (ZS_IS_CONS(up)) 843 return; 844 845 spin_lock_irqsave(&port->lock, flags); 846 847 channel = ZILOG_CHANNEL_FROM_PORT(port); 848 849 /* Disable receiver and transmitter. */ 850 up->curregs[R3] &= ~RxENAB; 851 up->curregs[R5] &= ~TxENAB; 852 853 /* Disable all interrupts and BRK assertion. */ 854 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 855 up->curregs[R5] &= ~SND_BRK; 856 sunzilog_maybe_update_regs(up, channel); 857 858 spin_unlock_irqrestore(&port->lock, flags); 859 } 860 861 /* Shared by TTY driver and serial console setup. The port lock is held 862 * and local interrupts are disabled. 863 */ 864 static void 865 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag, 866 unsigned int iflag, int brg) 867 { 868 869 up->curregs[R10] = NRZ; 870 up->curregs[R11] = TCBR | RCBR; 871 872 /* Program BAUD and clock source. */ 873 up->curregs[R4] &= ~XCLK_MASK; 874 up->curregs[R4] |= X16CLK; 875 up->curregs[R12] = brg & 0xff; 876 up->curregs[R13] = (brg >> 8) & 0xff; 877 up->curregs[R14] = BRSRC | BRENAB; 878 879 /* Character size, stop bits, and parity. */ 880 up->curregs[R3] &= ~RxN_MASK; 881 up->curregs[R5] &= ~TxN_MASK; 882 switch (cflag & CSIZE) { 883 case CS5: 884 up->curregs[R3] |= Rx5; 885 up->curregs[R5] |= Tx5; 886 up->parity_mask = 0x1f; 887 break; 888 case CS6: 889 up->curregs[R3] |= Rx6; 890 up->curregs[R5] |= Tx6; 891 up->parity_mask = 0x3f; 892 break; 893 case CS7: 894 up->curregs[R3] |= Rx7; 895 up->curregs[R5] |= Tx7; 896 up->parity_mask = 0x7f; 897 break; 898 case CS8: 899 default: 900 up->curregs[R3] |= Rx8; 901 up->curregs[R5] |= Tx8; 902 up->parity_mask = 0xff; 903 break; 904 }; 905 up->curregs[R4] &= ~0x0c; 906 if (cflag & CSTOPB) 907 up->curregs[R4] |= SB2; 908 else 909 up->curregs[R4] |= SB1; 910 if (cflag & PARENB) 911 up->curregs[R4] |= PAR_ENAB; 912 else 913 up->curregs[R4] &= ~PAR_ENAB; 914 if (!(cflag & PARODD)) 915 up->curregs[R4] |= PAR_EVEN; 916 else 917 up->curregs[R4] &= ~PAR_EVEN; 918 919 up->port.read_status_mask = Rx_OVR; 920 if (iflag & INPCK) 921 up->port.read_status_mask |= CRC_ERR | PAR_ERR; 922 if (iflag & (BRKINT | PARMRK)) 923 up->port.read_status_mask |= BRK_ABRT; 924 925 up->port.ignore_status_mask = 0; 926 if (iflag & IGNPAR) 927 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR; 928 if (iflag & IGNBRK) { 929 up->port.ignore_status_mask |= BRK_ABRT; 930 if (iflag & IGNPAR) 931 up->port.ignore_status_mask |= Rx_OVR; 932 } 933 934 if ((cflag & CREAD) == 0) 935 up->port.ignore_status_mask = 0xff; 936 } 937 938 /* The port lock is not held. */ 939 static void 940 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios, 941 struct ktermios *old) 942 { 943 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port; 944 unsigned long flags; 945 int baud, brg; 946 947 baud = uart_get_baud_rate(port, termios, old, 1200, 76800); 948 949 spin_lock_irqsave(&up->port.lock, flags); 950 951 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 952 953 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg); 954 955 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 956 up->flags |= SUNZILOG_FLAG_MODEM_STATUS; 957 else 958 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS; 959 960 up->cflag = termios->c_cflag; 961 962 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port)); 963 964 uart_update_timeout(port, termios->c_cflag, baud); 965 966 spin_unlock_irqrestore(&up->port.lock, flags); 967 } 968 969 static const char *sunzilog_type(struct uart_port *port) 970 { 971 struct uart_sunzilog_port *up = UART_ZILOG(port); 972 973 return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs"; 974 } 975 976 /* We do not request/release mappings of the registers here, this 977 * happens at early serial probe time. 978 */ 979 static void sunzilog_release_port(struct uart_port *port) 980 { 981 } 982 983 static int sunzilog_request_port(struct uart_port *port) 984 { 985 return 0; 986 } 987 988 /* These do not need to do anything interesting either. */ 989 static void sunzilog_config_port(struct uart_port *port, int flags) 990 { 991 } 992 993 /* We do not support letting the user mess with the divisor, IRQ, etc. */ 994 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser) 995 { 996 return -EINVAL; 997 } 998 999 #ifdef CONFIG_CONSOLE_POLL 1000 static int sunzilog_get_poll_char(struct uart_port *port) 1001 { 1002 unsigned char ch, r1; 1003 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port; 1004 struct zilog_channel __iomem *channel 1005 = ZILOG_CHANNEL_FROM_PORT(&up->port); 1006 1007 1008 r1 = read_zsreg(channel, R1); 1009 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { 1010 writeb(ERR_RES, &channel->control); 1011 ZSDELAY(); 1012 ZS_WSYNC(channel); 1013 } 1014 1015 ch = readb(&channel->control); 1016 ZSDELAY(); 1017 1018 /* This funny hack depends upon BRK_ABRT not interfering 1019 * with the other bits we care about in R1. 1020 */ 1021 if (ch & BRK_ABRT) 1022 r1 |= BRK_ABRT; 1023 1024 if (!(ch & Rx_CH_AV)) 1025 return NO_POLL_CHAR; 1026 1027 ch = readb(&channel->data); 1028 ZSDELAY(); 1029 1030 ch &= up->parity_mask; 1031 return ch; 1032 } 1033 1034 static void sunzilog_put_poll_char(struct uart_port *port, 1035 unsigned char ch) 1036 { 1037 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *)port; 1038 1039 sunzilog_putchar(&up->port, ch); 1040 } 1041 #endif /* CONFIG_CONSOLE_POLL */ 1042 1043 static struct uart_ops sunzilog_pops = { 1044 .tx_empty = sunzilog_tx_empty, 1045 .set_mctrl = sunzilog_set_mctrl, 1046 .get_mctrl = sunzilog_get_mctrl, 1047 .stop_tx = sunzilog_stop_tx, 1048 .start_tx = sunzilog_start_tx, 1049 .stop_rx = sunzilog_stop_rx, 1050 .enable_ms = sunzilog_enable_ms, 1051 .break_ctl = sunzilog_break_ctl, 1052 .startup = sunzilog_startup, 1053 .shutdown = sunzilog_shutdown, 1054 .set_termios = sunzilog_set_termios, 1055 .type = sunzilog_type, 1056 .release_port = sunzilog_release_port, 1057 .request_port = sunzilog_request_port, 1058 .config_port = sunzilog_config_port, 1059 .verify_port = sunzilog_verify_port, 1060 #ifdef CONFIG_CONSOLE_POLL 1061 .poll_get_char = sunzilog_get_poll_char, 1062 .poll_put_char = sunzilog_put_poll_char, 1063 #endif 1064 }; 1065 1066 static int uart_chip_count; 1067 static struct uart_sunzilog_port *sunzilog_port_table; 1068 static struct zilog_layout __iomem **sunzilog_chip_regs; 1069 1070 static struct uart_sunzilog_port *sunzilog_irq_chain; 1071 1072 static struct uart_driver sunzilog_reg = { 1073 .owner = THIS_MODULE, 1074 .driver_name = "sunzilog", 1075 .dev_name = "ttyS", 1076 .major = TTY_MAJOR, 1077 }; 1078 1079 static int __init sunzilog_alloc_tables(int num_sunzilog) 1080 { 1081 struct uart_sunzilog_port *up; 1082 unsigned long size; 1083 int num_channels = num_sunzilog * 2; 1084 int i; 1085 1086 size = num_channels * sizeof(struct uart_sunzilog_port); 1087 sunzilog_port_table = kzalloc(size, GFP_KERNEL); 1088 if (!sunzilog_port_table) 1089 return -ENOMEM; 1090 1091 for (i = 0; i < num_channels; i++) { 1092 up = &sunzilog_port_table[i]; 1093 1094 spin_lock_init(&up->port.lock); 1095 1096 if (i == 0) 1097 sunzilog_irq_chain = up; 1098 1099 if (i < num_channels - 1) 1100 up->next = up + 1; 1101 else 1102 up->next = NULL; 1103 } 1104 1105 size = num_sunzilog * sizeof(struct zilog_layout __iomem *); 1106 sunzilog_chip_regs = kzalloc(size, GFP_KERNEL); 1107 if (!sunzilog_chip_regs) { 1108 kfree(sunzilog_port_table); 1109 sunzilog_irq_chain = NULL; 1110 return -ENOMEM; 1111 } 1112 1113 return 0; 1114 } 1115 1116 static void sunzilog_free_tables(void) 1117 { 1118 kfree(sunzilog_port_table); 1119 sunzilog_irq_chain = NULL; 1120 kfree(sunzilog_chip_regs); 1121 } 1122 1123 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */ 1124 1125 static void sunzilog_putchar(struct uart_port *port, int ch) 1126 { 1127 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port); 1128 int loops = ZS_PUT_CHAR_MAX_DELAY; 1129 1130 /* This is a timed polling loop so do not switch the explicit 1131 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM 1132 */ 1133 do { 1134 unsigned char val = readb(&channel->control); 1135 if (val & Tx_BUF_EMP) { 1136 ZSDELAY(); 1137 break; 1138 } 1139 udelay(5); 1140 } while (--loops); 1141 1142 writeb(ch, &channel->data); 1143 ZSDELAY(); 1144 ZS_WSYNC(channel); 1145 } 1146 1147 #ifdef CONFIG_SERIO 1148 1149 static DEFINE_SPINLOCK(sunzilog_serio_lock); 1150 1151 static int sunzilog_serio_write(struct serio *serio, unsigned char ch) 1152 { 1153 struct uart_sunzilog_port *up = serio->port_data; 1154 unsigned long flags; 1155 1156 spin_lock_irqsave(&sunzilog_serio_lock, flags); 1157 1158 sunzilog_putchar(&up->port, ch); 1159 1160 spin_unlock_irqrestore(&sunzilog_serio_lock, flags); 1161 1162 return 0; 1163 } 1164 1165 static int sunzilog_serio_open(struct serio *serio) 1166 { 1167 struct uart_sunzilog_port *up = serio->port_data; 1168 unsigned long flags; 1169 int ret; 1170 1171 spin_lock_irqsave(&sunzilog_serio_lock, flags); 1172 if (!up->serio_open) { 1173 up->serio_open = 1; 1174 ret = 0; 1175 } else 1176 ret = -EBUSY; 1177 spin_unlock_irqrestore(&sunzilog_serio_lock, flags); 1178 1179 return ret; 1180 } 1181 1182 static void sunzilog_serio_close(struct serio *serio) 1183 { 1184 struct uart_sunzilog_port *up = serio->port_data; 1185 unsigned long flags; 1186 1187 spin_lock_irqsave(&sunzilog_serio_lock, flags); 1188 up->serio_open = 0; 1189 spin_unlock_irqrestore(&sunzilog_serio_lock, flags); 1190 } 1191 1192 #endif /* CONFIG_SERIO */ 1193 1194 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE 1195 static void 1196 sunzilog_console_write(struct console *con, const char *s, unsigned int count) 1197 { 1198 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index]; 1199 unsigned long flags; 1200 int locked = 1; 1201 1202 local_irq_save(flags); 1203 if (up->port.sysrq) { 1204 locked = 0; 1205 } else if (oops_in_progress) { 1206 locked = spin_trylock(&up->port.lock); 1207 } else 1208 spin_lock(&up->port.lock); 1209 1210 uart_console_write(&up->port, s, count, sunzilog_putchar); 1211 udelay(2); 1212 1213 if (locked) 1214 spin_unlock(&up->port.lock); 1215 local_irq_restore(flags); 1216 } 1217 1218 static int __init sunzilog_console_setup(struct console *con, char *options) 1219 { 1220 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index]; 1221 unsigned long flags; 1222 int baud, brg; 1223 1224 if (up->port.type != PORT_SUNZILOG) 1225 return -1; 1226 1227 printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n", 1228 (sunzilog_reg.minor - 64) + con->index, con->index); 1229 1230 /* Get firmware console settings. */ 1231 sunserial_console_termios(con, up->port.dev->of_node); 1232 1233 /* Firmware console speed is limited to 150-->38400 baud so 1234 * this hackish cflag thing is OK. 1235 */ 1236 switch (con->cflag & CBAUD) { 1237 case B150: baud = 150; break; 1238 case B300: baud = 300; break; 1239 case B600: baud = 600; break; 1240 case B1200: baud = 1200; break; 1241 case B2400: baud = 2400; break; 1242 case B4800: baud = 4800; break; 1243 default: case B9600: baud = 9600; break; 1244 case B19200: baud = 19200; break; 1245 case B38400: baud = 38400; break; 1246 }; 1247 1248 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 1249 1250 spin_lock_irqsave(&up->port.lock, flags); 1251 1252 up->curregs[R15] |= BRKIE; 1253 sunzilog_convert_to_zs(up, con->cflag, 0, brg); 1254 1255 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS); 1256 __sunzilog_startup(up); 1257 1258 spin_unlock_irqrestore(&up->port.lock, flags); 1259 1260 return 0; 1261 } 1262 1263 static struct console sunzilog_console_ops = { 1264 .name = "ttyS", 1265 .write = sunzilog_console_write, 1266 .device = uart_console_device, 1267 .setup = sunzilog_console_setup, 1268 .flags = CON_PRINTBUFFER, 1269 .index = -1, 1270 .data = &sunzilog_reg, 1271 }; 1272 1273 static inline struct console *SUNZILOG_CONSOLE(void) 1274 { 1275 return &sunzilog_console_ops; 1276 } 1277 1278 #else 1279 #define SUNZILOG_CONSOLE() (NULL) 1280 #endif 1281 1282 static void sunzilog_init_kbdms(struct uart_sunzilog_port *up) 1283 { 1284 int baud, brg; 1285 1286 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) { 1287 up->cflag = B1200 | CS8 | CLOCAL | CREAD; 1288 baud = 1200; 1289 } else { 1290 up->cflag = B4800 | CS8 | CLOCAL | CREAD; 1291 baud = 4800; 1292 } 1293 1294 up->curregs[R15] |= BRKIE; 1295 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 1296 sunzilog_convert_to_zs(up, up->cflag, 0, brg); 1297 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS); 1298 __sunzilog_startup(up); 1299 } 1300 1301 #ifdef CONFIG_SERIO 1302 static void sunzilog_register_serio(struct uart_sunzilog_port *up) 1303 { 1304 struct serio *serio = &up->serio; 1305 1306 serio->port_data = up; 1307 1308 serio->id.type = SERIO_RS232; 1309 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) { 1310 serio->id.proto = SERIO_SUNKBD; 1311 strlcpy(serio->name, "zskbd", sizeof(serio->name)); 1312 } else { 1313 serio->id.proto = SERIO_SUN; 1314 serio->id.extra = 1; 1315 strlcpy(serio->name, "zsms", sizeof(serio->name)); 1316 } 1317 strlcpy(serio->phys, 1318 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ? 1319 "zs/serio0" : "zs/serio1"), 1320 sizeof(serio->phys)); 1321 1322 serio->write = sunzilog_serio_write; 1323 serio->open = sunzilog_serio_open; 1324 serio->close = sunzilog_serio_close; 1325 serio->dev.parent = up->port.dev; 1326 1327 serio_register_port(serio); 1328 } 1329 #endif 1330 1331 static void sunzilog_init_hw(struct uart_sunzilog_port *up) 1332 { 1333 struct zilog_channel __iomem *channel; 1334 unsigned long flags; 1335 int baud, brg; 1336 1337 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 1338 1339 spin_lock_irqsave(&up->port.lock, flags); 1340 if (ZS_IS_CHANNEL_A(up)) { 1341 write_zsreg(channel, R9, FHWRES); 1342 ZSDELAY_LONG(); 1343 (void) read_zsreg(channel, R0); 1344 } 1345 1346 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB | 1347 SUNZILOG_FLAG_CONS_MOUSE)) { 1348 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; 1349 up->curregs[R4] = PAR_EVEN | X16CLK | SB1; 1350 up->curregs[R3] = RxENAB | Rx8; 1351 up->curregs[R5] = TxENAB | Tx8; 1352 up->curregs[R6] = 0x00; /* SDLC Address */ 1353 up->curregs[R7] = 0x7E; /* SDLC Flag */ 1354 up->curregs[R9] = NV; 1355 up->curregs[R7p] = 0x00; 1356 sunzilog_init_kbdms(up); 1357 /* Only enable interrupts if an ISR handler available */ 1358 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER) 1359 up->curregs[R9] |= MIE; 1360 write_zsreg(channel, R9, up->curregs[R9]); 1361 } else { 1362 /* Normal serial TTY. */ 1363 up->parity_mask = 0xff; 1364 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; 1365 up->curregs[R4] = PAR_EVEN | X16CLK | SB1; 1366 up->curregs[R3] = RxENAB | Rx8; 1367 up->curregs[R5] = TxENAB | Tx8; 1368 up->curregs[R6] = 0x00; /* SDLC Address */ 1369 up->curregs[R7] = 0x7E; /* SDLC Flag */ 1370 up->curregs[R9] = NV; 1371 up->curregs[R10] = NRZ; 1372 up->curregs[R11] = TCBR | RCBR; 1373 baud = 9600; 1374 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 1375 up->curregs[R12] = (brg & 0xff); 1376 up->curregs[R13] = (brg >> 8) & 0xff; 1377 up->curregs[R14] = BRSRC | BRENAB; 1378 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */ 1379 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL; 1380 if (__load_zsregs(channel, up->curregs)) { 1381 up->flags |= SUNZILOG_FLAG_ESCC; 1382 } 1383 /* Only enable interrupts if an ISR handler available */ 1384 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER) 1385 up->curregs[R9] |= MIE; 1386 write_zsreg(channel, R9, up->curregs[R9]); 1387 } 1388 1389 spin_unlock_irqrestore(&up->port.lock, flags); 1390 1391 #ifdef CONFIG_SERIO 1392 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB | 1393 SUNZILOG_FLAG_CONS_MOUSE)) 1394 sunzilog_register_serio(up); 1395 #endif 1396 } 1397 1398 static int zilog_irq; 1399 1400 static int zs_probe(struct platform_device *op) 1401 { 1402 static int kbm_inst, uart_inst; 1403 int inst; 1404 struct uart_sunzilog_port *up; 1405 struct zilog_layout __iomem *rp; 1406 int keyboard_mouse = 0; 1407 int err; 1408 1409 if (of_find_property(op->dev.of_node, "keyboard", NULL)) 1410 keyboard_mouse = 1; 1411 1412 /* uarts must come before keyboards/mice */ 1413 if (keyboard_mouse) 1414 inst = uart_chip_count + kbm_inst; 1415 else 1416 inst = uart_inst; 1417 1418 sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0, 1419 sizeof(struct zilog_layout), 1420 "zs"); 1421 if (!sunzilog_chip_regs[inst]) 1422 return -ENOMEM; 1423 1424 rp = sunzilog_chip_regs[inst]; 1425 1426 if (!zilog_irq) 1427 zilog_irq = op->archdata.irqs[0]; 1428 1429 up = &sunzilog_port_table[inst * 2]; 1430 1431 /* Channel A */ 1432 up[0].port.mapbase = op->resource[0].start + 0x00; 1433 up[0].port.membase = (void __iomem *) &rp->channelA; 1434 up[0].port.iotype = UPIO_MEM; 1435 up[0].port.irq = op->archdata.irqs[0]; 1436 up[0].port.uartclk = ZS_CLOCK; 1437 up[0].port.fifosize = 1; 1438 up[0].port.ops = &sunzilog_pops; 1439 up[0].port.type = PORT_SUNZILOG; 1440 up[0].port.flags = 0; 1441 up[0].port.line = (inst * 2) + 0; 1442 up[0].port.dev = &op->dev; 1443 up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A; 1444 if (keyboard_mouse) 1445 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB; 1446 sunzilog_init_hw(&up[0]); 1447 1448 /* Channel B */ 1449 up[1].port.mapbase = op->resource[0].start + 0x04; 1450 up[1].port.membase = (void __iomem *) &rp->channelB; 1451 up[1].port.iotype = UPIO_MEM; 1452 up[1].port.irq = op->archdata.irqs[0]; 1453 up[1].port.uartclk = ZS_CLOCK; 1454 up[1].port.fifosize = 1; 1455 up[1].port.ops = &sunzilog_pops; 1456 up[1].port.type = PORT_SUNZILOG; 1457 up[1].port.flags = 0; 1458 up[1].port.line = (inst * 2) + 1; 1459 up[1].port.dev = &op->dev; 1460 up[1].flags |= 0; 1461 if (keyboard_mouse) 1462 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE; 1463 sunzilog_init_hw(&up[1]); 1464 1465 if (!keyboard_mouse) { 1466 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node, 1467 &sunzilog_reg, up[0].port.line, 1468 false)) 1469 up->flags |= SUNZILOG_FLAG_IS_CONS; 1470 err = uart_add_one_port(&sunzilog_reg, &up[0].port); 1471 if (err) { 1472 of_iounmap(&op->resource[0], 1473 rp, sizeof(struct zilog_layout)); 1474 return err; 1475 } 1476 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node, 1477 &sunzilog_reg, up[1].port.line, 1478 false)) 1479 up->flags |= SUNZILOG_FLAG_IS_CONS; 1480 err = uart_add_one_port(&sunzilog_reg, &up[1].port); 1481 if (err) { 1482 uart_remove_one_port(&sunzilog_reg, &up[0].port); 1483 of_iounmap(&op->resource[0], 1484 rp, sizeof(struct zilog_layout)); 1485 return err; 1486 } 1487 uart_inst++; 1488 } else { 1489 printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) " 1490 "is a %s\n", 1491 dev_name(&op->dev), 1492 (unsigned long long) up[0].port.mapbase, 1493 op->archdata.irqs[0], sunzilog_type(&up[0].port)); 1494 printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) " 1495 "is a %s\n", 1496 dev_name(&op->dev), 1497 (unsigned long long) up[1].port.mapbase, 1498 op->archdata.irqs[0], sunzilog_type(&up[1].port)); 1499 kbm_inst++; 1500 } 1501 1502 dev_set_drvdata(&op->dev, &up[0]); 1503 1504 return 0; 1505 } 1506 1507 static void zs_remove_one(struct uart_sunzilog_port *up) 1508 { 1509 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) { 1510 #ifdef CONFIG_SERIO 1511 serio_unregister_port(&up->serio); 1512 #endif 1513 } else 1514 uart_remove_one_port(&sunzilog_reg, &up->port); 1515 } 1516 1517 static int zs_remove(struct platform_device *op) 1518 { 1519 struct uart_sunzilog_port *up = dev_get_drvdata(&op->dev); 1520 struct zilog_layout __iomem *regs; 1521 1522 zs_remove_one(&up[0]); 1523 zs_remove_one(&up[1]); 1524 1525 regs = sunzilog_chip_regs[up[0].port.line / 2]; 1526 of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout)); 1527 1528 dev_set_drvdata(&op->dev, NULL); 1529 1530 return 0; 1531 } 1532 1533 static const struct of_device_id zs_match[] = { 1534 { 1535 .name = "zs", 1536 }, 1537 {}, 1538 }; 1539 MODULE_DEVICE_TABLE(of, zs_match); 1540 1541 static struct platform_driver zs_driver = { 1542 .driver = { 1543 .name = "zs", 1544 .owner = THIS_MODULE, 1545 .of_match_table = zs_match, 1546 }, 1547 .probe = zs_probe, 1548 .remove = zs_remove, 1549 }; 1550 1551 static int __init sunzilog_init(void) 1552 { 1553 struct device_node *dp; 1554 int err; 1555 int num_keybms = 0; 1556 int num_sunzilog = 0; 1557 1558 for_each_node_by_name(dp, "zs") { 1559 num_sunzilog++; 1560 if (of_find_property(dp, "keyboard", NULL)) 1561 num_keybms++; 1562 } 1563 1564 if (num_sunzilog) { 1565 err = sunzilog_alloc_tables(num_sunzilog); 1566 if (err) 1567 goto out; 1568 1569 uart_chip_count = num_sunzilog - num_keybms; 1570 1571 err = sunserial_register_minors(&sunzilog_reg, 1572 uart_chip_count * 2); 1573 if (err) 1574 goto out_free_tables; 1575 } 1576 1577 err = platform_driver_register(&zs_driver); 1578 if (err) 1579 goto out_unregister_uart; 1580 1581 if (zilog_irq) { 1582 struct uart_sunzilog_port *up = sunzilog_irq_chain; 1583 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED, 1584 "zs", sunzilog_irq_chain); 1585 if (err) 1586 goto out_unregister_driver; 1587 1588 /* Enable Interrupts */ 1589 while (up) { 1590 struct zilog_channel __iomem *channel; 1591 1592 /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */ 1593 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 1594 up->flags |= SUNZILOG_FLAG_ISR_HANDLER; 1595 up->curregs[R9] |= MIE; 1596 write_zsreg(channel, R9, up->curregs[R9]); 1597 up = up->next; 1598 } 1599 } 1600 1601 out: 1602 return err; 1603 1604 out_unregister_driver: 1605 platform_driver_unregister(&zs_driver); 1606 1607 out_unregister_uart: 1608 if (num_sunzilog) { 1609 sunserial_unregister_minors(&sunzilog_reg, num_sunzilog); 1610 sunzilog_reg.cons = NULL; 1611 } 1612 1613 out_free_tables: 1614 sunzilog_free_tables(); 1615 goto out; 1616 } 1617 1618 static void __exit sunzilog_exit(void) 1619 { 1620 platform_driver_unregister(&zs_driver); 1621 1622 if (zilog_irq) { 1623 struct uart_sunzilog_port *up = sunzilog_irq_chain; 1624 1625 /* Disable Interrupts */ 1626 while (up) { 1627 struct zilog_channel __iomem *channel; 1628 1629 /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */ 1630 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 1631 up->flags &= ~SUNZILOG_FLAG_ISR_HANDLER; 1632 up->curregs[R9] &= ~MIE; 1633 write_zsreg(channel, R9, up->curregs[R9]); 1634 up = up->next; 1635 } 1636 1637 free_irq(zilog_irq, sunzilog_irq_chain); 1638 zilog_irq = 0; 1639 } 1640 1641 if (sunzilog_reg.nr) { 1642 sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr); 1643 sunzilog_free_tables(); 1644 } 1645 } 1646 1647 module_init(sunzilog_init); 1648 module_exit(sunzilog_exit); 1649 1650 MODULE_AUTHOR("David S. Miller"); 1651 MODULE_DESCRIPTION("Sun Zilog serial port driver"); 1652 MODULE_VERSION("2.0"); 1653 MODULE_LICENSE("GPL"); 1654