1 /* 2 * Copyright (C) Maxime Coquelin 2015 3 * Copyright (C) STMicroelectronics SA 2017 4 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 5 * Gerald Baeza <gerald_baeza@yahoo.fr> 6 * License terms: GNU General Public License (GPL), version 2 7 */ 8 9 #define DRIVER_NAME "stm32-usart" 10 11 struct stm32_usart_offsets { 12 u8 cr1; 13 u8 cr2; 14 u8 cr3; 15 u8 brr; 16 u8 gtpr; 17 u8 rtor; 18 u8 rqr; 19 u8 isr; 20 u8 icr; 21 u8 rdr; 22 u8 tdr; 23 }; 24 25 struct stm32_usart_config { 26 u8 uart_enable_bit; /* USART_CR1_UE */ 27 bool has_7bits_data; 28 }; 29 30 struct stm32_usart_info { 31 struct stm32_usart_offsets ofs; 32 struct stm32_usart_config cfg; 33 }; 34 35 #define UNDEF_REG 0xff 36 37 /* Register offsets */ 38 struct stm32_usart_info stm32f4_info = { 39 .ofs = { 40 .isr = 0x00, 41 .rdr = 0x04, 42 .tdr = 0x04, 43 .brr = 0x08, 44 .cr1 = 0x0c, 45 .cr2 = 0x10, 46 .cr3 = 0x14, 47 .gtpr = 0x18, 48 .rtor = UNDEF_REG, 49 .rqr = UNDEF_REG, 50 .icr = UNDEF_REG, 51 }, 52 .cfg = { 53 .uart_enable_bit = 13, 54 .has_7bits_data = false, 55 } 56 }; 57 58 struct stm32_usart_info stm32f7_info = { 59 .ofs = { 60 .cr1 = 0x00, 61 .cr2 = 0x04, 62 .cr3 = 0x08, 63 .brr = 0x0c, 64 .gtpr = 0x10, 65 .rtor = 0x14, 66 .rqr = 0x18, 67 .isr = 0x1c, 68 .icr = 0x20, 69 .rdr = 0x24, 70 .tdr = 0x28, 71 }, 72 .cfg = { 73 .uart_enable_bit = 0, 74 .has_7bits_data = true, 75 } 76 }; 77 78 /* USART_SR (F4) / USART_ISR (F7) */ 79 #define USART_SR_PE BIT(0) 80 #define USART_SR_FE BIT(1) 81 #define USART_SR_NF BIT(2) 82 #define USART_SR_ORE BIT(3) 83 #define USART_SR_IDLE BIT(4) 84 #define USART_SR_RXNE BIT(5) 85 #define USART_SR_TC BIT(6) 86 #define USART_SR_TXE BIT(7) 87 #define USART_SR_LBD BIT(8) 88 #define USART_SR_CTSIF BIT(9) 89 #define USART_SR_CTS BIT(10) /* F7 */ 90 #define USART_SR_RTOF BIT(11) /* F7 */ 91 #define USART_SR_EOBF BIT(12) /* F7 */ 92 #define USART_SR_ABRE BIT(14) /* F7 */ 93 #define USART_SR_ABRF BIT(15) /* F7 */ 94 #define USART_SR_BUSY BIT(16) /* F7 */ 95 #define USART_SR_CMF BIT(17) /* F7 */ 96 #define USART_SR_SBKF BIT(18) /* F7 */ 97 #define USART_SR_TEACK BIT(21) /* F7 */ 98 #define USART_SR_ERR_MASK (USART_SR_LBD | USART_SR_ORE | \ 99 USART_SR_FE | USART_SR_PE) 100 /* Dummy bits */ 101 #define USART_SR_DUMMY_RX BIT(16) 102 103 /* USART_ICR (F7) */ 104 #define USART_CR_TC BIT(6) 105 106 /* USART_DR */ 107 #define USART_DR_MASK GENMASK(8, 0) 108 109 /* USART_BRR */ 110 #define USART_BRR_DIV_F_MASK GENMASK(3, 0) 111 #define USART_BRR_DIV_M_MASK GENMASK(15, 4) 112 #define USART_BRR_DIV_M_SHIFT 4 113 114 /* USART_CR1 */ 115 #define USART_CR1_SBK BIT(0) 116 #define USART_CR1_RWU BIT(1) /* F4 */ 117 #define USART_CR1_RE BIT(2) 118 #define USART_CR1_TE BIT(3) 119 #define USART_CR1_IDLEIE BIT(4) 120 #define USART_CR1_RXNEIE BIT(5) 121 #define USART_CR1_TCIE BIT(6) 122 #define USART_CR1_TXEIE BIT(7) 123 #define USART_CR1_PEIE BIT(8) 124 #define USART_CR1_PS BIT(9) 125 #define USART_CR1_PCE BIT(10) 126 #define USART_CR1_WAKE BIT(11) 127 #define USART_CR1_M BIT(12) 128 #define USART_CR1_M0 BIT(12) /* F7 */ 129 #define USART_CR1_MME BIT(13) /* F7 */ 130 #define USART_CR1_CMIE BIT(14) /* F7 */ 131 #define USART_CR1_OVER8 BIT(15) 132 #define USART_CR1_DEDT_MASK GENMASK(20, 16) /* F7 */ 133 #define USART_CR1_DEAT_MASK GENMASK(25, 21) /* F7 */ 134 #define USART_CR1_RTOIE BIT(26) /* F7 */ 135 #define USART_CR1_EOBIE BIT(27) /* F7 */ 136 #define USART_CR1_M1 BIT(28) /* F7 */ 137 #define USART_CR1_IE_MASK (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27)) 138 139 /* USART_CR2 */ 140 #define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */ 141 #define USART_CR2_ADDM7 BIT(4) /* F7 */ 142 #define USART_CR2_LBDL BIT(5) 143 #define USART_CR2_LBDIE BIT(6) 144 #define USART_CR2_LBCL BIT(8) 145 #define USART_CR2_CPHA BIT(9) 146 #define USART_CR2_CPOL BIT(10) 147 #define USART_CR2_CLKEN BIT(11) 148 #define USART_CR2_STOP_2B BIT(13) 149 #define USART_CR2_STOP_MASK GENMASK(13, 12) 150 #define USART_CR2_LINEN BIT(14) 151 #define USART_CR2_SWAP BIT(15) /* F7 */ 152 #define USART_CR2_RXINV BIT(16) /* F7 */ 153 #define USART_CR2_TXINV BIT(17) /* F7 */ 154 #define USART_CR2_DATAINV BIT(18) /* F7 */ 155 #define USART_CR2_MSBFIRST BIT(19) /* F7 */ 156 #define USART_CR2_ABREN BIT(20) /* F7 */ 157 #define USART_CR2_ABRMOD_MASK GENMASK(22, 21) /* F7 */ 158 #define USART_CR2_RTOEN BIT(23) /* F7 */ 159 #define USART_CR2_ADD_F7_MASK GENMASK(31, 24) /* F7 */ 160 161 /* USART_CR3 */ 162 #define USART_CR3_EIE BIT(0) 163 #define USART_CR3_IREN BIT(1) 164 #define USART_CR3_IRLP BIT(2) 165 #define USART_CR3_HDSEL BIT(3) 166 #define USART_CR3_NACK BIT(4) 167 #define USART_CR3_SCEN BIT(5) 168 #define USART_CR3_DMAR BIT(6) 169 #define USART_CR3_DMAT BIT(7) 170 #define USART_CR3_RTSE BIT(8) 171 #define USART_CR3_CTSE BIT(9) 172 #define USART_CR3_CTSIE BIT(10) 173 #define USART_CR3_ONEBIT BIT(11) 174 #define USART_CR3_OVRDIS BIT(12) /* F7 */ 175 #define USART_CR3_DDRE BIT(13) /* F7 */ 176 #define USART_CR3_DEM BIT(14) /* F7 */ 177 #define USART_CR3_DEP BIT(15) /* F7 */ 178 #define USART_CR3_SCARCNT_MASK GENMASK(19, 17) /* F7 */ 179 180 /* USART_GTPR */ 181 #define USART_GTPR_PSC_MASK GENMASK(7, 0) 182 #define USART_GTPR_GT_MASK GENMASK(15, 8) 183 184 /* USART_RTOR */ 185 #define USART_RTOR_RTO_MASK GENMASK(23, 0) /* F7 */ 186 #define USART_RTOR_BLEN_MASK GENMASK(31, 24) /* F7 */ 187 188 /* USART_RQR */ 189 #define USART_RQR_ABRRQ BIT(0) /* F7 */ 190 #define USART_RQR_SBKRQ BIT(1) /* F7 */ 191 #define USART_RQR_MMRQ BIT(2) /* F7 */ 192 #define USART_RQR_RXFRQ BIT(3) /* F7 */ 193 #define USART_RQR_TXFRQ BIT(4) /* F7 */ 194 195 /* USART_ICR */ 196 #define USART_ICR_PECF BIT(0) /* F7 */ 197 #define USART_ICR_FFECF BIT(1) /* F7 */ 198 #define USART_ICR_NCF BIT(2) /* F7 */ 199 #define USART_ICR_ORECF BIT(3) /* F7 */ 200 #define USART_ICR_IDLECF BIT(4) /* F7 */ 201 #define USART_ICR_TCCF BIT(6) /* F7 */ 202 #define USART_ICR_LBDCF BIT(8) /* F7 */ 203 #define USART_ICR_CTSCF BIT(9) /* F7 */ 204 #define USART_ICR_RTOCF BIT(11) /* F7 */ 205 #define USART_ICR_EOBCF BIT(12) /* F7 */ 206 #define USART_ICR_CMCF BIT(17) /* F7 */ 207 208 #define STM32_SERIAL_NAME "ttyS" 209 #define STM32_MAX_PORTS 6 210 211 #define RX_BUF_L 200 /* dma rx buffer length */ 212 #define RX_BUF_P RX_BUF_L /* dma rx buffer period */ 213 #define TX_BUF_L 200 /* dma tx buffer length */ 214 215 struct stm32_port { 216 struct uart_port port; 217 struct clk *clk; 218 struct stm32_usart_info *info; 219 struct dma_chan *rx_ch; /* dma rx channel */ 220 dma_addr_t rx_dma_buf; /* dma rx buffer bus address */ 221 unsigned char *rx_buf; /* dma rx buffer cpu address */ 222 struct dma_chan *tx_ch; /* dma tx channel */ 223 dma_addr_t tx_dma_buf; /* dma tx buffer bus address */ 224 unsigned char *tx_buf; /* dma tx buffer cpu address */ 225 bool tx_dma_busy; /* dma tx busy */ 226 bool hw_flow_control; 227 }; 228 229 static struct stm32_port stm32_ports[STM32_MAX_PORTS]; 230 static struct uart_driver stm32_usart_driver; 231