1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@foss.st.com> 7 * Erwan Le Ray <erwan.leray@foss.st.com> 8 * 9 * Inspired by st-asc.c from STMicroelectronics (c) 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/delay.h> 15 #include <linux/dma-direction.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "serial_mctrl_gpio.h" 36 #include "stm32-usart.h" 37 38 static void stm32_usart_stop_tx(struct uart_port *port); 39 static void stm32_usart_transmit_chars(struct uart_port *port); 40 41 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 42 { 43 return container_of(port, struct stm32_port, port); 44 } 45 46 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 47 { 48 u32 val; 49 50 val = readl_relaxed(port->membase + reg); 51 val |= bits; 52 writel_relaxed(val, port->membase + reg); 53 } 54 55 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 56 { 57 u32 val; 58 59 val = readl_relaxed(port->membase + reg); 60 val &= ~bits; 61 writel_relaxed(val, port->membase + reg); 62 } 63 64 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 65 u32 delay_DDE, u32 baud) 66 { 67 u32 rs485_deat_dedt; 68 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 69 bool over8; 70 71 *cr3 |= USART_CR3_DEM; 72 over8 = *cr1 & USART_CR1_OVER8; 73 74 if (over8) 75 rs485_deat_dedt = delay_ADE * baud * 8; 76 else 77 rs485_deat_dedt = delay_ADE * baud * 16; 78 79 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 80 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 81 rs485_deat_dedt_max : rs485_deat_dedt; 82 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 83 USART_CR1_DEAT_MASK; 84 *cr1 |= rs485_deat_dedt; 85 86 if (over8) 87 rs485_deat_dedt = delay_DDE * baud * 8; 88 else 89 rs485_deat_dedt = delay_DDE * baud * 16; 90 91 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 92 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 93 rs485_deat_dedt_max : rs485_deat_dedt; 94 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 95 USART_CR1_DEDT_MASK; 96 *cr1 |= rs485_deat_dedt; 97 } 98 99 static int stm32_usart_config_rs485(struct uart_port *port, 100 struct serial_rs485 *rs485conf) 101 { 102 struct stm32_port *stm32_port = to_stm32_port(port); 103 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 104 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 105 u32 usartdiv, baud, cr1, cr3; 106 bool over8; 107 108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 109 110 port->rs485 = *rs485conf; 111 112 rs485conf->flags |= SER_RS485_RX_DURING_TX; 113 114 if (rs485conf->flags & SER_RS485_ENABLED) { 115 cr1 = readl_relaxed(port->membase + ofs->cr1); 116 cr3 = readl_relaxed(port->membase + ofs->cr3); 117 usartdiv = readl_relaxed(port->membase + ofs->brr); 118 usartdiv = usartdiv & GENMASK(15, 0); 119 over8 = cr1 & USART_CR1_OVER8; 120 121 if (over8) 122 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 123 << USART_BRR_04_R_SHIFT; 124 125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 126 stm32_usart_config_reg_rs485(&cr1, &cr3, 127 rs485conf->delay_rts_before_send, 128 rs485conf->delay_rts_after_send, 129 baud); 130 131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 132 cr3 &= ~USART_CR3_DEP; 133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 134 } else { 135 cr3 |= USART_CR3_DEP; 136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 137 } 138 139 writel_relaxed(cr3, port->membase + ofs->cr3); 140 writel_relaxed(cr1, port->membase + ofs->cr1); 141 } else { 142 stm32_usart_clr_bits(port, ofs->cr3, 143 USART_CR3_DEM | USART_CR3_DEP); 144 stm32_usart_clr_bits(port, ofs->cr1, 145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 146 } 147 148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 149 150 return 0; 151 } 152 153 static int stm32_usart_init_rs485(struct uart_port *port, 154 struct platform_device *pdev) 155 { 156 struct serial_rs485 *rs485conf = &port->rs485; 157 158 rs485conf->flags = 0; 159 rs485conf->delay_rts_before_send = 0; 160 rs485conf->delay_rts_after_send = 0; 161 162 if (!pdev->dev.of_node) 163 return -ENODEV; 164 165 return uart_get_rs485_mode(port); 166 } 167 168 static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr, 169 int *last_res, bool threaded) 170 { 171 struct stm32_port *stm32_port = to_stm32_port(port); 172 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 173 enum dma_status status; 174 struct dma_tx_state state; 175 176 *sr = readl_relaxed(port->membase + ofs->isr); 177 178 if (threaded && stm32_port->rx_ch) { 179 status = dmaengine_tx_status(stm32_port->rx_ch, 180 stm32_port->rx_ch->cookie, 181 &state); 182 if (status == DMA_IN_PROGRESS && (*last_res != state.residue)) 183 return 1; 184 else 185 return 0; 186 } else if (*sr & USART_SR_RXNE) { 187 return 1; 188 } 189 return 0; 190 } 191 192 static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr, 193 int *last_res) 194 { 195 struct stm32_port *stm32_port = to_stm32_port(port); 196 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 197 unsigned long c; 198 199 if (stm32_port->rx_ch) { 200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 201 if ((*last_res) == 0) 202 *last_res = RX_BUF_L; 203 } else { 204 c = readl_relaxed(port->membase + ofs->rdr); 205 /* apply RDR data mask */ 206 c &= stm32_port->rdr_mask; 207 } 208 209 return c; 210 } 211 212 static void stm32_usart_receive_chars(struct uart_port *port, bool threaded) 213 { 214 struct tty_port *tport = &port->state->port; 215 struct stm32_port *stm32_port = to_stm32_port(port); 216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 217 unsigned long c; 218 u32 sr; 219 char flag; 220 221 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 222 pm_wakeup_event(tport->tty->dev, 0); 223 224 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, 225 threaded)) { 226 sr |= USART_SR_DUMMY_RX; 227 flag = TTY_NORMAL; 228 229 /* 230 * Status bits has to be cleared before reading the RDR: 231 * In FIFO mode, reading the RDR will pop the next data 232 * (if any) along with its status bits into the SR. 233 * Not doing so leads to misalignement between RDR and SR, 234 * and clear status bits of the next rx data. 235 * 236 * Clear errors flags for stm32f7 and stm32h7 compatible 237 * devices. On stm32f4 compatible devices, the error bit is 238 * cleared by the sequence [read SR - read DR]. 239 */ 240 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 241 writel_relaxed(sr & USART_SR_ERR_MASK, 242 port->membase + ofs->icr); 243 244 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); 245 port->icount.rx++; 246 if (sr & USART_SR_ERR_MASK) { 247 if (sr & USART_SR_ORE) { 248 port->icount.overrun++; 249 } else if (sr & USART_SR_PE) { 250 port->icount.parity++; 251 } else if (sr & USART_SR_FE) { 252 /* Break detection if character is null */ 253 if (!c) { 254 port->icount.brk++; 255 if (uart_handle_break(port)) 256 continue; 257 } else { 258 port->icount.frame++; 259 } 260 } 261 262 sr &= port->read_status_mask; 263 264 if (sr & USART_SR_PE) { 265 flag = TTY_PARITY; 266 } else if (sr & USART_SR_FE) { 267 if (!c) 268 flag = TTY_BREAK; 269 else 270 flag = TTY_FRAME; 271 } 272 } 273 274 if (uart_handle_sysrq_char(port, c)) 275 continue; 276 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 277 } 278 279 spin_unlock(&port->lock); 280 tty_flip_buffer_push(tport); 281 spin_lock(&port->lock); 282 } 283 284 static void stm32_usart_tx_dma_complete(void *arg) 285 { 286 struct uart_port *port = arg; 287 struct stm32_port *stm32port = to_stm32_port(port); 288 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 289 290 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 291 stm32port->tx_dma_busy = false; 292 293 /* Let's see if we have pending data to send */ 294 stm32_usart_transmit_chars(port); 295 } 296 297 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 298 { 299 struct stm32_port *stm32_port = to_stm32_port(port); 300 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 301 302 /* 303 * Enables TX FIFO threashold irq when FIFO is enabled, 304 * or TX empty irq when FIFO is disabled 305 */ 306 if (stm32_port->fifoen) 307 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 308 else 309 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 310 } 311 312 static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 313 { 314 struct stm32_port *stm32_port = to_stm32_port(port); 315 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 316 317 if (stm32_port->fifoen) 318 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 319 else 320 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 321 } 322 323 static void stm32_usart_transmit_chars_pio(struct uart_port *port) 324 { 325 struct stm32_port *stm32_port = to_stm32_port(port); 326 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 327 struct circ_buf *xmit = &port->state->xmit; 328 329 if (stm32_port->tx_dma_busy) { 330 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 331 stm32_port->tx_dma_busy = false; 332 } 333 334 while (!uart_circ_empty(xmit)) { 335 /* Check that TDR is empty before filling FIFO */ 336 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 337 break; 338 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 339 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 340 port->icount.tx++; 341 } 342 343 /* rely on TXE irq (mask or unmask) for sending remaining data */ 344 if (uart_circ_empty(xmit)) 345 stm32_usart_tx_interrupt_disable(port); 346 else 347 stm32_usart_tx_interrupt_enable(port); 348 } 349 350 static void stm32_usart_transmit_chars_dma(struct uart_port *port) 351 { 352 struct stm32_port *stm32port = to_stm32_port(port); 353 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 354 struct circ_buf *xmit = &port->state->xmit; 355 struct dma_async_tx_descriptor *desc = NULL; 356 unsigned int count, i; 357 358 if (stm32port->tx_dma_busy) 359 return; 360 361 stm32port->tx_dma_busy = true; 362 363 count = uart_circ_chars_pending(xmit); 364 365 if (count > TX_BUF_L) 366 count = TX_BUF_L; 367 368 if (xmit->tail < xmit->head) { 369 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 370 } else { 371 size_t one = UART_XMIT_SIZE - xmit->tail; 372 size_t two; 373 374 if (one > count) 375 one = count; 376 two = count - one; 377 378 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 379 if (two) 380 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 381 } 382 383 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 384 stm32port->tx_dma_buf, 385 count, 386 DMA_MEM_TO_DEV, 387 DMA_PREP_INTERRUPT); 388 389 if (!desc) 390 goto fallback_err; 391 392 desc->callback = stm32_usart_tx_dma_complete; 393 desc->callback_param = port; 394 395 /* Push current DMA TX transaction in the pending queue */ 396 if (dma_submit_error(dmaengine_submit(desc))) { 397 /* dma no yet started, safe to free resources */ 398 dmaengine_terminate_async(stm32port->tx_ch); 399 goto fallback_err; 400 } 401 402 /* Issue pending DMA TX requests */ 403 dma_async_issue_pending(stm32port->tx_ch); 404 405 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 406 407 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 408 port->icount.tx += count; 409 return; 410 411 fallback_err: 412 for (i = count; i > 0; i--) 413 stm32_usart_transmit_chars_pio(port); 414 } 415 416 static void stm32_usart_transmit_chars(struct uart_port *port) 417 { 418 struct stm32_port *stm32_port = to_stm32_port(port); 419 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 420 struct circ_buf *xmit = &port->state->xmit; 421 422 if (port->x_char) { 423 if (stm32_port->tx_dma_busy) 424 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 425 writel_relaxed(port->x_char, port->membase + ofs->tdr); 426 port->x_char = 0; 427 port->icount.tx++; 428 if (stm32_port->tx_dma_busy) 429 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 430 return; 431 } 432 433 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 434 stm32_usart_tx_interrupt_disable(port); 435 return; 436 } 437 438 if (ofs->icr == UNDEF_REG) 439 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 440 else 441 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 442 443 if (stm32_port->tx_ch) 444 stm32_usart_transmit_chars_dma(port); 445 else 446 stm32_usart_transmit_chars_pio(port); 447 448 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 449 uart_write_wakeup(port); 450 451 if (uart_circ_empty(xmit)) 452 stm32_usart_tx_interrupt_disable(port); 453 } 454 455 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 456 { 457 struct uart_port *port = ptr; 458 struct stm32_port *stm32_port = to_stm32_port(port); 459 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 460 u32 sr; 461 462 spin_lock(&port->lock); 463 464 sr = readl_relaxed(port->membase + ofs->isr); 465 466 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 467 writel_relaxed(USART_ICR_RTOCF, 468 port->membase + ofs->icr); 469 470 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) 471 writel_relaxed(USART_ICR_WUCF, 472 port->membase + ofs->icr); 473 474 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 475 stm32_usart_receive_chars(port, false); 476 477 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 478 stm32_usart_transmit_chars(port); 479 480 spin_unlock(&port->lock); 481 482 if (stm32_port->rx_ch) 483 return IRQ_WAKE_THREAD; 484 else 485 return IRQ_HANDLED; 486 } 487 488 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr) 489 { 490 struct uart_port *port = ptr; 491 struct stm32_port *stm32_port = to_stm32_port(port); 492 493 spin_lock(&port->lock); 494 495 if (stm32_port->rx_ch) 496 stm32_usart_receive_chars(port, true); 497 498 spin_unlock(&port->lock); 499 500 return IRQ_HANDLED; 501 } 502 503 static unsigned int stm32_usart_tx_empty(struct uart_port *port) 504 { 505 struct stm32_port *stm32_port = to_stm32_port(port); 506 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 507 508 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 509 } 510 511 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 512 { 513 struct stm32_port *stm32_port = to_stm32_port(port); 514 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 515 516 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 517 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 518 else 519 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 520 521 mctrl_gpio_set(stm32_port->gpios, mctrl); 522 } 523 524 static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 525 { 526 struct stm32_port *stm32_port = to_stm32_port(port); 527 unsigned int ret; 528 529 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 530 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 531 532 return mctrl_gpio_get(stm32_port->gpios, &ret); 533 } 534 535 static void stm32_usart_enable_ms(struct uart_port *port) 536 { 537 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 538 } 539 540 static void stm32_usart_disable_ms(struct uart_port *port) 541 { 542 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 543 } 544 545 /* Transmit stop */ 546 static void stm32_usart_stop_tx(struct uart_port *port) 547 { 548 struct stm32_port *stm32_port = to_stm32_port(port); 549 struct serial_rs485 *rs485conf = &port->rs485; 550 551 stm32_usart_tx_interrupt_disable(port); 552 553 if (rs485conf->flags & SER_RS485_ENABLED) { 554 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 555 mctrl_gpio_set(stm32_port->gpios, 556 stm32_port->port.mctrl & ~TIOCM_RTS); 557 } else { 558 mctrl_gpio_set(stm32_port->gpios, 559 stm32_port->port.mctrl | TIOCM_RTS); 560 } 561 } 562 } 563 564 /* There are probably characters waiting to be transmitted. */ 565 static void stm32_usart_start_tx(struct uart_port *port) 566 { 567 struct stm32_port *stm32_port = to_stm32_port(port); 568 struct serial_rs485 *rs485conf = &port->rs485; 569 struct circ_buf *xmit = &port->state->xmit; 570 571 if (uart_circ_empty(xmit)) 572 return; 573 574 if (rs485conf->flags & SER_RS485_ENABLED) { 575 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 576 mctrl_gpio_set(stm32_port->gpios, 577 stm32_port->port.mctrl | TIOCM_RTS); 578 } else { 579 mctrl_gpio_set(stm32_port->gpios, 580 stm32_port->port.mctrl & ~TIOCM_RTS); 581 } 582 } 583 584 stm32_usart_transmit_chars(port); 585 } 586 587 /* Throttle the remote when input buffer is about to overflow. */ 588 static void stm32_usart_throttle(struct uart_port *port) 589 { 590 struct stm32_port *stm32_port = to_stm32_port(port); 591 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 592 unsigned long flags; 593 594 spin_lock_irqsave(&port->lock, flags); 595 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 596 if (stm32_port->cr3_irq) 597 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 598 599 spin_unlock_irqrestore(&port->lock, flags); 600 } 601 602 /* Unthrottle the remote, the input buffer can now accept data. */ 603 static void stm32_usart_unthrottle(struct uart_port *port) 604 { 605 struct stm32_port *stm32_port = to_stm32_port(port); 606 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 607 unsigned long flags; 608 609 spin_lock_irqsave(&port->lock, flags); 610 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 611 if (stm32_port->cr3_irq) 612 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 613 614 spin_unlock_irqrestore(&port->lock, flags); 615 } 616 617 /* Receive stop */ 618 static void stm32_usart_stop_rx(struct uart_port *port) 619 { 620 struct stm32_port *stm32_port = to_stm32_port(port); 621 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 622 623 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 624 if (stm32_port->cr3_irq) 625 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 626 } 627 628 /* Handle breaks - ignored by us */ 629 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 630 { 631 } 632 633 static int stm32_usart_startup(struct uart_port *port) 634 { 635 struct stm32_port *stm32_port = to_stm32_port(port); 636 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 637 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 638 const char *name = to_platform_device(port->dev)->name; 639 u32 val; 640 int ret; 641 642 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, 643 stm32_usart_threaded_interrupt, 644 IRQF_NO_SUSPEND, name, port); 645 if (ret) 646 return ret; 647 648 /* RX FIFO Flush */ 649 if (ofs->rqr != UNDEF_REG) 650 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); 651 652 /* Tx and RX FIFO configuration */ 653 if (stm32_port->fifoen) { 654 val = readl_relaxed(port->membase + ofs->cr3); 655 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 656 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 657 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 658 writel_relaxed(val, port->membase + ofs->cr3); 659 } 660 661 /* RX FIFO enabling */ 662 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 663 if (stm32_port->fifoen) 664 val |= USART_CR1_FIFOEN; 665 stm32_usart_set_bits(port, ofs->cr1, val); 666 667 return 0; 668 } 669 670 static void stm32_usart_shutdown(struct uart_port *port) 671 { 672 struct stm32_port *stm32_port = to_stm32_port(port); 673 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 674 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 675 u32 val, isr; 676 int ret; 677 678 /* Disable modem control interrupts */ 679 stm32_usart_disable_ms(port); 680 681 val = USART_CR1_TXEIE | USART_CR1_TE; 682 val |= stm32_port->cr1_irq | USART_CR1_RE; 683 val |= BIT(cfg->uart_enable_bit); 684 if (stm32_port->fifoen) 685 val |= USART_CR1_FIFOEN; 686 687 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 688 isr, (isr & USART_SR_TC), 689 10, 100000); 690 691 /* Send the TC error message only when ISR_TC is not set */ 692 if (ret) 693 dev_err(port->dev, "Transmission is not complete\n"); 694 695 stm32_usart_clr_bits(port, ofs->cr1, val); 696 697 free_irq(port->irq, port); 698 } 699 700 static unsigned int stm32_usart_get_databits(struct ktermios *termios) 701 { 702 unsigned int bits; 703 704 tcflag_t cflag = termios->c_cflag; 705 706 switch (cflag & CSIZE) { 707 /* 708 * CSIZE settings are not necessarily supported in hardware. 709 * CSIZE unsupported configurations are handled here to set word length 710 * to 8 bits word as default configuration and to print debug message. 711 */ 712 case CS5: 713 bits = 5; 714 break; 715 case CS6: 716 bits = 6; 717 break; 718 case CS7: 719 bits = 7; 720 break; 721 /* default including CS8 */ 722 default: 723 bits = 8; 724 break; 725 } 726 727 return bits; 728 } 729 730 static void stm32_usart_set_termios(struct uart_port *port, 731 struct ktermios *termios, 732 struct ktermios *old) 733 { 734 struct stm32_port *stm32_port = to_stm32_port(port); 735 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 736 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 737 struct serial_rs485 *rs485conf = &port->rs485; 738 unsigned int baud, bits; 739 u32 usartdiv, mantissa, fraction, oversampling; 740 tcflag_t cflag = termios->c_cflag; 741 u32 cr1, cr2, cr3; 742 unsigned long flags; 743 744 if (!stm32_port->hw_flow_control) 745 cflag &= ~CRTSCTS; 746 747 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 748 749 spin_lock_irqsave(&port->lock, flags); 750 751 /* Stop serial port and reset value */ 752 writel_relaxed(0, port->membase + ofs->cr1); 753 754 /* flush RX & TX FIFO */ 755 if (ofs->rqr != UNDEF_REG) 756 stm32_usart_set_bits(port, ofs->rqr, 757 USART_RQR_TXFRQ | USART_RQR_RXFRQ); 758 759 cr1 = USART_CR1_TE | USART_CR1_RE; 760 if (stm32_port->fifoen) 761 cr1 |= USART_CR1_FIFOEN; 762 cr2 = 0; 763 cr3 = readl_relaxed(port->membase + ofs->cr3); 764 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE 765 | USART_CR3_TXFTCFG_MASK; 766 767 if (cflag & CSTOPB) 768 cr2 |= USART_CR2_STOP_2B; 769 770 bits = stm32_usart_get_databits(termios); 771 stm32_port->rdr_mask = (BIT(bits) - 1); 772 773 if (cflag & PARENB) { 774 bits++; 775 cr1 |= USART_CR1_PCE; 776 } 777 778 /* 779 * Word length configuration: 780 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 781 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 782 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 783 * M0 and M1 already cleared by cr1 initialization. 784 */ 785 if (bits == 9) 786 cr1 |= USART_CR1_M0; 787 else if ((bits == 7) && cfg->has_7bits_data) 788 cr1 |= USART_CR1_M1; 789 else if (bits != 8) 790 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 791 , bits); 792 793 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 794 stm32_port->fifoen)) { 795 if (cflag & CSTOPB) 796 bits = bits + 3; /* 1 start bit + 2 stop bits */ 797 else 798 bits = bits + 2; /* 1 start bit + 1 stop bit */ 799 800 /* RX timeout irq to occur after last stop bit + bits */ 801 stm32_port->cr1_irq = USART_CR1_RTOIE; 802 writel_relaxed(bits, port->membase + ofs->rtor); 803 cr2 |= USART_CR2_RTOEN; 804 /* Not using dma, enable fifo threshold irq */ 805 if (!stm32_port->rx_ch) 806 stm32_port->cr3_irq = USART_CR3_RXFTIE; 807 } 808 809 cr1 |= stm32_port->cr1_irq; 810 cr3 |= stm32_port->cr3_irq; 811 812 if (cflag & PARODD) 813 cr1 |= USART_CR1_PS; 814 815 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 816 if (cflag & CRTSCTS) { 817 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 818 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 819 } 820 821 /* Handle modem control interrupts */ 822 if (UART_ENABLE_MS(port, termios->c_cflag)) 823 stm32_usart_enable_ms(port); 824 else 825 stm32_usart_disable_ms(port); 826 827 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 828 829 /* 830 * The USART supports 16 or 8 times oversampling. 831 * By default we prefer 16 times oversampling, so that the receiver 832 * has a better tolerance to clock deviations. 833 * 8 times oversampling is only used to achieve higher speeds. 834 */ 835 if (usartdiv < 16) { 836 oversampling = 8; 837 cr1 |= USART_CR1_OVER8; 838 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 839 } else { 840 oversampling = 16; 841 cr1 &= ~USART_CR1_OVER8; 842 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 843 } 844 845 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 846 fraction = usartdiv % oversampling; 847 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 848 849 uart_update_timeout(port, cflag, baud); 850 851 port->read_status_mask = USART_SR_ORE; 852 if (termios->c_iflag & INPCK) 853 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 854 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 855 port->read_status_mask |= USART_SR_FE; 856 857 /* Characters to ignore */ 858 port->ignore_status_mask = 0; 859 if (termios->c_iflag & IGNPAR) 860 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 861 if (termios->c_iflag & IGNBRK) { 862 port->ignore_status_mask |= USART_SR_FE; 863 /* 864 * If we're ignoring parity and break indicators, 865 * ignore overruns too (for real raw support). 866 */ 867 if (termios->c_iflag & IGNPAR) 868 port->ignore_status_mask |= USART_SR_ORE; 869 } 870 871 /* Ignore all characters if CREAD is not set */ 872 if ((termios->c_cflag & CREAD) == 0) 873 port->ignore_status_mask |= USART_SR_DUMMY_RX; 874 875 if (stm32_port->rx_ch) 876 cr3 |= USART_CR3_DMAR; 877 878 if (rs485conf->flags & SER_RS485_ENABLED) { 879 stm32_usart_config_reg_rs485(&cr1, &cr3, 880 rs485conf->delay_rts_before_send, 881 rs485conf->delay_rts_after_send, 882 baud); 883 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 884 cr3 &= ~USART_CR3_DEP; 885 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 886 } else { 887 cr3 |= USART_CR3_DEP; 888 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 889 } 890 891 } else { 892 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 893 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 894 } 895 896 writel_relaxed(cr3, port->membase + ofs->cr3); 897 writel_relaxed(cr2, port->membase + ofs->cr2); 898 writel_relaxed(cr1, port->membase + ofs->cr1); 899 900 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 901 spin_unlock_irqrestore(&port->lock, flags); 902 } 903 904 static const char *stm32_usart_type(struct uart_port *port) 905 { 906 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 907 } 908 909 static void stm32_usart_release_port(struct uart_port *port) 910 { 911 } 912 913 static int stm32_usart_request_port(struct uart_port *port) 914 { 915 return 0; 916 } 917 918 static void stm32_usart_config_port(struct uart_port *port, int flags) 919 { 920 if (flags & UART_CONFIG_TYPE) 921 port->type = PORT_STM32; 922 } 923 924 static int 925 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 926 { 927 /* No user changeable parameters */ 928 return -EINVAL; 929 } 930 931 static void stm32_usart_pm(struct uart_port *port, unsigned int state, 932 unsigned int oldstate) 933 { 934 struct stm32_port *stm32port = container_of(port, 935 struct stm32_port, port); 936 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 937 const struct stm32_usart_config *cfg = &stm32port->info->cfg; 938 unsigned long flags = 0; 939 940 switch (state) { 941 case UART_PM_STATE_ON: 942 pm_runtime_get_sync(port->dev); 943 break; 944 case UART_PM_STATE_OFF: 945 spin_lock_irqsave(&port->lock, flags); 946 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 947 spin_unlock_irqrestore(&port->lock, flags); 948 pm_runtime_put_sync(port->dev); 949 break; 950 } 951 } 952 953 static const struct uart_ops stm32_uart_ops = { 954 .tx_empty = stm32_usart_tx_empty, 955 .set_mctrl = stm32_usart_set_mctrl, 956 .get_mctrl = stm32_usart_get_mctrl, 957 .stop_tx = stm32_usart_stop_tx, 958 .start_tx = stm32_usart_start_tx, 959 .throttle = stm32_usart_throttle, 960 .unthrottle = stm32_usart_unthrottle, 961 .stop_rx = stm32_usart_stop_rx, 962 .enable_ms = stm32_usart_enable_ms, 963 .break_ctl = stm32_usart_break_ctl, 964 .startup = stm32_usart_startup, 965 .shutdown = stm32_usart_shutdown, 966 .set_termios = stm32_usart_set_termios, 967 .pm = stm32_usart_pm, 968 .type = stm32_usart_type, 969 .release_port = stm32_usart_release_port, 970 .request_port = stm32_usart_request_port, 971 .config_port = stm32_usart_config_port, 972 .verify_port = stm32_usart_verify_port, 973 }; 974 975 static void stm32_usart_deinit_port(struct stm32_port *stm32port) 976 { 977 clk_disable_unprepare(stm32port->clk); 978 } 979 980 static int stm32_usart_init_port(struct stm32_port *stm32port, 981 struct platform_device *pdev) 982 { 983 struct uart_port *port = &stm32port->port; 984 struct resource *res; 985 int ret, irq; 986 987 irq = platform_get_irq(pdev, 0); 988 if (irq <= 0) 989 return irq ? : -ENODEV; 990 991 port->iotype = UPIO_MEM; 992 port->flags = UPF_BOOT_AUTOCONF; 993 port->ops = &stm32_uart_ops; 994 port->dev = &pdev->dev; 995 port->fifosize = stm32port->info->cfg.fifosize; 996 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 997 port->irq = irq; 998 port->rs485_config = stm32_usart_config_rs485; 999 1000 ret = stm32_usart_init_rs485(port, pdev); 1001 if (ret) 1002 return ret; 1003 1004 if (stm32port->info->cfg.has_wakeup) { 1005 stm32port->wakeirq = platform_get_irq_optional(pdev, 1); 1006 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) 1007 return stm32port->wakeirq ? : -ENODEV; 1008 } 1009 1010 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1011 1012 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1013 port->membase = devm_ioremap_resource(&pdev->dev, res); 1014 if (IS_ERR(port->membase)) 1015 return PTR_ERR(port->membase); 1016 port->mapbase = res->start; 1017 1018 spin_lock_init(&port->lock); 1019 1020 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1021 if (IS_ERR(stm32port->clk)) 1022 return PTR_ERR(stm32port->clk); 1023 1024 /* Ensure that clk rate is correct by enabling the clk */ 1025 ret = clk_prepare_enable(stm32port->clk); 1026 if (ret) 1027 return ret; 1028 1029 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1030 if (!stm32port->port.uartclk) { 1031 ret = -EINVAL; 1032 goto err_clk; 1033 } 1034 1035 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1036 if (IS_ERR(stm32port->gpios)) { 1037 ret = PTR_ERR(stm32port->gpios); 1038 goto err_clk; 1039 } 1040 1041 /* 1042 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" 1043 * properties should not be specified. 1044 */ 1045 if (stm32port->hw_flow_control) { 1046 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1047 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1048 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1049 ret = -EINVAL; 1050 goto err_clk; 1051 } 1052 } 1053 1054 return ret; 1055 1056 err_clk: 1057 clk_disable_unprepare(stm32port->clk); 1058 1059 return ret; 1060 } 1061 1062 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1063 { 1064 struct device_node *np = pdev->dev.of_node; 1065 int id; 1066 1067 if (!np) 1068 return NULL; 1069 1070 id = of_alias_get_id(np, "serial"); 1071 if (id < 0) { 1072 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1073 return NULL; 1074 } 1075 1076 if (WARN_ON(id >= STM32_MAX_PORTS)) 1077 return NULL; 1078 1079 stm32_ports[id].hw_flow_control = 1080 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1081 of_property_read_bool (np, "uart-has-rtscts"); 1082 stm32_ports[id].port.line = id; 1083 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1084 stm32_ports[id].cr3_irq = 0; 1085 stm32_ports[id].last_res = RX_BUF_L; 1086 return &stm32_ports[id]; 1087 } 1088 1089 #ifdef CONFIG_OF 1090 static const struct of_device_id stm32_match[] = { 1091 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1092 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1093 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1094 {}, 1095 }; 1096 1097 MODULE_DEVICE_TABLE(of, stm32_match); 1098 #endif 1099 1100 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1101 struct platform_device *pdev) 1102 { 1103 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1104 struct uart_port *port = &stm32port->port; 1105 struct device *dev = &pdev->dev; 1106 struct dma_slave_config config; 1107 struct dma_async_tx_descriptor *desc = NULL; 1108 int ret; 1109 1110 /* Request DMA RX channel */ 1111 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1112 if (!stm32port->rx_ch) { 1113 dev_info(dev, "rx dma alloc failed\n"); 1114 return -ENODEV; 1115 } 1116 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1117 &stm32port->rx_dma_buf, 1118 GFP_KERNEL); 1119 if (!stm32port->rx_buf) { 1120 ret = -ENOMEM; 1121 goto alloc_err; 1122 } 1123 1124 /* Configure DMA channel */ 1125 memset(&config, 0, sizeof(config)); 1126 config.src_addr = port->mapbase + ofs->rdr; 1127 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1128 1129 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1130 if (ret < 0) { 1131 dev_err(dev, "rx dma channel config failed\n"); 1132 ret = -ENODEV; 1133 goto config_err; 1134 } 1135 1136 /* Prepare a DMA cyclic transaction */ 1137 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1138 stm32port->rx_dma_buf, 1139 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1140 DMA_PREP_INTERRUPT); 1141 if (!desc) { 1142 dev_err(dev, "rx dma prep cyclic failed\n"); 1143 ret = -ENODEV; 1144 goto config_err; 1145 } 1146 1147 /* No callback as dma buffer is drained on usart interrupt */ 1148 desc->callback = NULL; 1149 desc->callback_param = NULL; 1150 1151 /* Push current DMA transaction in the pending queue */ 1152 ret = dma_submit_error(dmaengine_submit(desc)); 1153 if (ret) { 1154 dmaengine_terminate_sync(stm32port->rx_ch); 1155 goto config_err; 1156 } 1157 1158 /* Issue pending DMA requests */ 1159 dma_async_issue_pending(stm32port->rx_ch); 1160 1161 return 0; 1162 1163 config_err: 1164 dma_free_coherent(&pdev->dev, 1165 RX_BUF_L, stm32port->rx_buf, 1166 stm32port->rx_dma_buf); 1167 1168 alloc_err: 1169 dma_release_channel(stm32port->rx_ch); 1170 stm32port->rx_ch = NULL; 1171 1172 return ret; 1173 } 1174 1175 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1176 struct platform_device *pdev) 1177 { 1178 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1179 struct uart_port *port = &stm32port->port; 1180 struct device *dev = &pdev->dev; 1181 struct dma_slave_config config; 1182 int ret; 1183 1184 stm32port->tx_dma_busy = false; 1185 1186 /* Request DMA TX channel */ 1187 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1188 if (!stm32port->tx_ch) { 1189 dev_info(dev, "tx dma alloc failed\n"); 1190 return -ENODEV; 1191 } 1192 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1193 &stm32port->tx_dma_buf, 1194 GFP_KERNEL); 1195 if (!stm32port->tx_buf) { 1196 ret = -ENOMEM; 1197 goto alloc_err; 1198 } 1199 1200 /* Configure DMA channel */ 1201 memset(&config, 0, sizeof(config)); 1202 config.dst_addr = port->mapbase + ofs->tdr; 1203 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1204 1205 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1206 if (ret < 0) { 1207 dev_err(dev, "tx dma channel config failed\n"); 1208 ret = -ENODEV; 1209 goto config_err; 1210 } 1211 1212 return 0; 1213 1214 config_err: 1215 dma_free_coherent(&pdev->dev, 1216 TX_BUF_L, stm32port->tx_buf, 1217 stm32port->tx_dma_buf); 1218 1219 alloc_err: 1220 dma_release_channel(stm32port->tx_ch); 1221 stm32port->tx_ch = NULL; 1222 1223 return ret; 1224 } 1225 1226 static int stm32_usart_serial_probe(struct platform_device *pdev) 1227 { 1228 struct stm32_port *stm32port; 1229 int ret; 1230 1231 stm32port = stm32_usart_of_get_port(pdev); 1232 if (!stm32port) 1233 return -ENODEV; 1234 1235 stm32port->info = of_device_get_match_data(&pdev->dev); 1236 if (!stm32port->info) 1237 return -EINVAL; 1238 1239 ret = stm32_usart_init_port(stm32port, pdev); 1240 if (ret) 1241 return ret; 1242 1243 if (stm32port->wakeirq > 0) { 1244 ret = device_init_wakeup(&pdev->dev, true); 1245 if (ret) 1246 goto err_uninit; 1247 1248 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1249 stm32port->wakeirq); 1250 if (ret) 1251 goto err_nowup; 1252 1253 device_set_wakeup_enable(&pdev->dev, false); 1254 } 1255 1256 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev); 1257 if (ret) 1258 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1259 1260 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev); 1261 if (ret) 1262 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1263 1264 platform_set_drvdata(pdev, &stm32port->port); 1265 1266 pm_runtime_get_noresume(&pdev->dev); 1267 pm_runtime_set_active(&pdev->dev); 1268 pm_runtime_enable(&pdev->dev); 1269 1270 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1271 if (ret) 1272 goto err_port; 1273 1274 pm_runtime_put_sync(&pdev->dev); 1275 1276 return 0; 1277 1278 err_port: 1279 pm_runtime_disable(&pdev->dev); 1280 pm_runtime_set_suspended(&pdev->dev); 1281 pm_runtime_put_noidle(&pdev->dev); 1282 1283 if (stm32port->rx_ch) { 1284 dmaengine_terminate_async(stm32port->rx_ch); 1285 dma_release_channel(stm32port->rx_ch); 1286 } 1287 1288 if (stm32port->rx_dma_buf) 1289 dma_free_coherent(&pdev->dev, 1290 RX_BUF_L, stm32port->rx_buf, 1291 stm32port->rx_dma_buf); 1292 1293 if (stm32port->tx_ch) { 1294 dmaengine_terminate_async(stm32port->tx_ch); 1295 dma_release_channel(stm32port->tx_ch); 1296 } 1297 1298 if (stm32port->tx_dma_buf) 1299 dma_free_coherent(&pdev->dev, 1300 TX_BUF_L, stm32port->tx_buf, 1301 stm32port->tx_dma_buf); 1302 1303 if (stm32port->wakeirq > 0) 1304 dev_pm_clear_wake_irq(&pdev->dev); 1305 1306 err_nowup: 1307 if (stm32port->wakeirq > 0) 1308 device_init_wakeup(&pdev->dev, false); 1309 1310 err_uninit: 1311 stm32_usart_deinit_port(stm32port); 1312 1313 return ret; 1314 } 1315 1316 static int stm32_usart_serial_remove(struct platform_device *pdev) 1317 { 1318 struct uart_port *port = platform_get_drvdata(pdev); 1319 struct stm32_port *stm32_port = to_stm32_port(port); 1320 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1321 int err; 1322 1323 pm_runtime_get_sync(&pdev->dev); 1324 err = uart_remove_one_port(&stm32_usart_driver, port); 1325 if (err) 1326 return(err); 1327 1328 pm_runtime_disable(&pdev->dev); 1329 pm_runtime_set_suspended(&pdev->dev); 1330 pm_runtime_put_noidle(&pdev->dev); 1331 1332 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1333 1334 if (stm32_port->rx_ch) { 1335 dmaengine_terminate_async(stm32_port->rx_ch); 1336 dma_release_channel(stm32_port->rx_ch); 1337 } 1338 1339 if (stm32_port->rx_dma_buf) 1340 dma_free_coherent(&pdev->dev, 1341 RX_BUF_L, stm32_port->rx_buf, 1342 stm32_port->rx_dma_buf); 1343 1344 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1345 1346 if (stm32_port->tx_ch) { 1347 dmaengine_terminate_async(stm32_port->tx_ch); 1348 dma_release_channel(stm32_port->tx_ch); 1349 } 1350 1351 if (stm32_port->tx_dma_buf) 1352 dma_free_coherent(&pdev->dev, 1353 TX_BUF_L, stm32_port->tx_buf, 1354 stm32_port->tx_dma_buf); 1355 1356 if (stm32_port->wakeirq > 0) { 1357 dev_pm_clear_wake_irq(&pdev->dev); 1358 device_init_wakeup(&pdev->dev, false); 1359 } 1360 1361 stm32_usart_deinit_port(stm32_port); 1362 1363 return 0; 1364 } 1365 1366 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1367 static void stm32_usart_console_putchar(struct uart_port *port, int ch) 1368 { 1369 struct stm32_port *stm32_port = to_stm32_port(port); 1370 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1371 1372 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1373 cpu_relax(); 1374 1375 writel_relaxed(ch, port->membase + ofs->tdr); 1376 } 1377 1378 static void stm32_usart_console_write(struct console *co, const char *s, 1379 unsigned int cnt) 1380 { 1381 struct uart_port *port = &stm32_ports[co->index].port; 1382 struct stm32_port *stm32_port = to_stm32_port(port); 1383 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1384 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1385 unsigned long flags; 1386 u32 old_cr1, new_cr1; 1387 int locked = 1; 1388 1389 local_irq_save(flags); 1390 if (port->sysrq) 1391 locked = 0; 1392 else if (oops_in_progress) 1393 locked = spin_trylock(&port->lock); 1394 else 1395 spin_lock(&port->lock); 1396 1397 /* Save and disable interrupts, enable the transmitter */ 1398 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1399 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1400 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1401 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1402 1403 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1404 1405 /* Restore interrupt state */ 1406 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1407 1408 if (locked) 1409 spin_unlock(&port->lock); 1410 local_irq_restore(flags); 1411 } 1412 1413 static int stm32_usart_console_setup(struct console *co, char *options) 1414 { 1415 struct stm32_port *stm32port; 1416 int baud = 9600; 1417 int bits = 8; 1418 int parity = 'n'; 1419 int flow = 'n'; 1420 1421 if (co->index >= STM32_MAX_PORTS) 1422 return -ENODEV; 1423 1424 stm32port = &stm32_ports[co->index]; 1425 1426 /* 1427 * This driver does not support early console initialization 1428 * (use ARM early printk support instead), so we only expect 1429 * this to be called during the uart port registration when the 1430 * driver gets probed and the port should be mapped at that point. 1431 */ 1432 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1433 return -ENXIO; 1434 1435 if (options) 1436 uart_parse_options(options, &baud, &parity, &bits, &flow); 1437 1438 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1439 } 1440 1441 static struct console stm32_console = { 1442 .name = STM32_SERIAL_NAME, 1443 .device = uart_console_device, 1444 .write = stm32_usart_console_write, 1445 .setup = stm32_usart_console_setup, 1446 .flags = CON_PRINTBUFFER, 1447 .index = -1, 1448 .data = &stm32_usart_driver, 1449 }; 1450 1451 #define STM32_SERIAL_CONSOLE (&stm32_console) 1452 1453 #else 1454 #define STM32_SERIAL_CONSOLE NULL 1455 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1456 1457 static struct uart_driver stm32_usart_driver = { 1458 .driver_name = DRIVER_NAME, 1459 .dev_name = STM32_SERIAL_NAME, 1460 .major = 0, 1461 .minor = 0, 1462 .nr = STM32_MAX_PORTS, 1463 .cons = STM32_SERIAL_CONSOLE, 1464 }; 1465 1466 static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1467 bool enable) 1468 { 1469 struct stm32_port *stm32_port = to_stm32_port(port); 1470 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1471 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1472 u32 val; 1473 1474 if (stm32_port->wakeirq <= 0) 1475 return; 1476 1477 if (enable) { 1478 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1479 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 1480 val = readl_relaxed(port->membase + ofs->cr3); 1481 val &= ~USART_CR3_WUS_MASK; 1482 /* Enable Wake up interrupt from low power on start bit */ 1483 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; 1484 writel_relaxed(val, port->membase + ofs->cr3); 1485 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1486 } else { 1487 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1488 } 1489 } 1490 1491 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 1492 { 1493 struct uart_port *port = dev_get_drvdata(dev); 1494 1495 uart_suspend_port(&stm32_usart_driver, port); 1496 1497 if (device_may_wakeup(dev)) 1498 stm32_usart_serial_en_wakeup(port, true); 1499 else 1500 stm32_usart_serial_en_wakeup(port, false); 1501 1502 /* 1503 * When "no_console_suspend" is enabled, keep the pinctrl default state 1504 * and rely on bootloader stage to restore this state upon resume. 1505 * Otherwise, apply the idle or sleep states depending on wakeup 1506 * capabilities. 1507 */ 1508 if (console_suspend_enabled || !uart_console(port)) { 1509 if (device_may_wakeup(dev)) 1510 pinctrl_pm_select_idle_state(dev); 1511 else 1512 pinctrl_pm_select_sleep_state(dev); 1513 } 1514 1515 return 0; 1516 } 1517 1518 static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 1519 { 1520 struct uart_port *port = dev_get_drvdata(dev); 1521 1522 pinctrl_pm_select_default_state(dev); 1523 1524 if (device_may_wakeup(dev)) 1525 stm32_usart_serial_en_wakeup(port, false); 1526 1527 return uart_resume_port(&stm32_usart_driver, port); 1528 } 1529 1530 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 1531 { 1532 struct uart_port *port = dev_get_drvdata(dev); 1533 struct stm32_port *stm32port = container_of(port, 1534 struct stm32_port, port); 1535 1536 clk_disable_unprepare(stm32port->clk); 1537 1538 return 0; 1539 } 1540 1541 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 1542 { 1543 struct uart_port *port = dev_get_drvdata(dev); 1544 struct stm32_port *stm32port = container_of(port, 1545 struct stm32_port, port); 1546 1547 return clk_prepare_enable(stm32port->clk); 1548 } 1549 1550 static const struct dev_pm_ops stm32_serial_pm_ops = { 1551 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 1552 stm32_usart_runtime_resume, NULL) 1553 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 1554 stm32_usart_serial_resume) 1555 }; 1556 1557 static struct platform_driver stm32_serial_driver = { 1558 .probe = stm32_usart_serial_probe, 1559 .remove = stm32_usart_serial_remove, 1560 .driver = { 1561 .name = DRIVER_NAME, 1562 .pm = &stm32_serial_pm_ops, 1563 .of_match_table = of_match_ptr(stm32_match), 1564 }, 1565 }; 1566 1567 static int __init stm32_usart_init(void) 1568 { 1569 static char banner[] __initdata = "STM32 USART driver initialized"; 1570 int ret; 1571 1572 pr_info("%s\n", banner); 1573 1574 ret = uart_register_driver(&stm32_usart_driver); 1575 if (ret) 1576 return ret; 1577 1578 ret = platform_driver_register(&stm32_serial_driver); 1579 if (ret) 1580 uart_unregister_driver(&stm32_usart_driver); 1581 1582 return ret; 1583 } 1584 1585 static void __exit stm32_usart_exit(void) 1586 { 1587 platform_driver_unregister(&stm32_serial_driver); 1588 uart_unregister_driver(&stm32_usart_driver); 1589 } 1590 1591 module_init(stm32_usart_init); 1592 module_exit(stm32_usart_exit); 1593 1594 MODULE_ALIAS("platform:" DRIVER_NAME); 1595 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1596 MODULE_LICENSE("GPL v2"); 1597