1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@foss.st.com> 7 * Erwan Le Ray <erwan.leray@foss.st.com> 8 * 9 * Inspired by st-asc.c from STMicroelectronics (c) 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/delay.h> 15 #include <linux/dma-direction.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "serial_mctrl_gpio.h" 36 #include "stm32-usart.h" 37 38 static void stm32_usart_stop_tx(struct uart_port *port); 39 static void stm32_usart_transmit_chars(struct uart_port *port); 40 41 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 42 { 43 return container_of(port, struct stm32_port, port); 44 } 45 46 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 47 { 48 u32 val; 49 50 val = readl_relaxed(port->membase + reg); 51 val |= bits; 52 writel_relaxed(val, port->membase + reg); 53 } 54 55 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 56 { 57 u32 val; 58 59 val = readl_relaxed(port->membase + reg); 60 val &= ~bits; 61 writel_relaxed(val, port->membase + reg); 62 } 63 64 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 65 u32 delay_DDE, u32 baud) 66 { 67 u32 rs485_deat_dedt; 68 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 69 bool over8; 70 71 *cr3 |= USART_CR3_DEM; 72 over8 = *cr1 & USART_CR1_OVER8; 73 74 if (over8) 75 rs485_deat_dedt = delay_ADE * baud * 8; 76 else 77 rs485_deat_dedt = delay_ADE * baud * 16; 78 79 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 80 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 81 rs485_deat_dedt_max : rs485_deat_dedt; 82 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 83 USART_CR1_DEAT_MASK; 84 *cr1 |= rs485_deat_dedt; 85 86 if (over8) 87 rs485_deat_dedt = delay_DDE * baud * 8; 88 else 89 rs485_deat_dedt = delay_DDE * baud * 16; 90 91 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 92 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 93 rs485_deat_dedt_max : rs485_deat_dedt; 94 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 95 USART_CR1_DEDT_MASK; 96 *cr1 |= rs485_deat_dedt; 97 } 98 99 static int stm32_usart_config_rs485(struct uart_port *port, 100 struct serial_rs485 *rs485conf) 101 { 102 struct stm32_port *stm32_port = to_stm32_port(port); 103 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 104 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 105 u32 usartdiv, baud, cr1, cr3; 106 bool over8; 107 108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 109 110 port->rs485 = *rs485conf; 111 112 rs485conf->flags |= SER_RS485_RX_DURING_TX; 113 114 if (rs485conf->flags & SER_RS485_ENABLED) { 115 cr1 = readl_relaxed(port->membase + ofs->cr1); 116 cr3 = readl_relaxed(port->membase + ofs->cr3); 117 usartdiv = readl_relaxed(port->membase + ofs->brr); 118 usartdiv = usartdiv & GENMASK(15, 0); 119 over8 = cr1 & USART_CR1_OVER8; 120 121 if (over8) 122 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 123 << USART_BRR_04_R_SHIFT; 124 125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 126 stm32_usart_config_reg_rs485(&cr1, &cr3, 127 rs485conf->delay_rts_before_send, 128 rs485conf->delay_rts_after_send, 129 baud); 130 131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 132 cr3 &= ~USART_CR3_DEP; 133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 134 } else { 135 cr3 |= USART_CR3_DEP; 136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 137 } 138 139 writel_relaxed(cr3, port->membase + ofs->cr3); 140 writel_relaxed(cr1, port->membase + ofs->cr1); 141 } else { 142 stm32_usart_clr_bits(port, ofs->cr3, 143 USART_CR3_DEM | USART_CR3_DEP); 144 stm32_usart_clr_bits(port, ofs->cr1, 145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 146 } 147 148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 149 150 return 0; 151 } 152 153 static int stm32_usart_init_rs485(struct uart_port *port, 154 struct platform_device *pdev) 155 { 156 struct serial_rs485 *rs485conf = &port->rs485; 157 158 rs485conf->flags = 0; 159 rs485conf->delay_rts_before_send = 0; 160 rs485conf->delay_rts_after_send = 0; 161 162 if (!pdev->dev.of_node) 163 return -ENODEV; 164 165 return uart_get_rs485_mode(port); 166 } 167 168 static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr, 169 int *last_res, bool threaded) 170 { 171 struct stm32_port *stm32_port = to_stm32_port(port); 172 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 173 enum dma_status status; 174 struct dma_tx_state state; 175 176 *sr = readl_relaxed(port->membase + ofs->isr); 177 178 if (threaded && stm32_port->rx_ch) { 179 status = dmaengine_tx_status(stm32_port->rx_ch, 180 stm32_port->rx_ch->cookie, 181 &state); 182 if (status == DMA_IN_PROGRESS && (*last_res != state.residue)) 183 return 1; 184 else 185 return 0; 186 } else if (*sr & USART_SR_RXNE) { 187 return 1; 188 } 189 return 0; 190 } 191 192 static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr, 193 int *last_res) 194 { 195 struct stm32_port *stm32_port = to_stm32_port(port); 196 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 197 unsigned long c; 198 199 if (stm32_port->rx_ch) { 200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 201 if ((*last_res) == 0) 202 *last_res = RX_BUF_L; 203 } else { 204 c = readl_relaxed(port->membase + ofs->rdr); 205 /* apply RDR data mask */ 206 c &= stm32_port->rdr_mask; 207 } 208 209 return c; 210 } 211 212 static void stm32_usart_receive_chars(struct uart_port *port, bool threaded) 213 { 214 struct tty_port *tport = &port->state->port; 215 struct stm32_port *stm32_port = to_stm32_port(port); 216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 217 unsigned long c; 218 u32 sr; 219 char flag; 220 221 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 222 pm_wakeup_event(tport->tty->dev, 0); 223 224 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, 225 threaded)) { 226 sr |= USART_SR_DUMMY_RX; 227 flag = TTY_NORMAL; 228 229 /* 230 * Status bits has to be cleared before reading the RDR: 231 * In FIFO mode, reading the RDR will pop the next data 232 * (if any) along with its status bits into the SR. 233 * Not doing so leads to misalignement between RDR and SR, 234 * and clear status bits of the next rx data. 235 * 236 * Clear errors flags for stm32f7 and stm32h7 compatible 237 * devices. On stm32f4 compatible devices, the error bit is 238 * cleared by the sequence [read SR - read DR]. 239 */ 240 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 241 writel_relaxed(sr & USART_SR_ERR_MASK, 242 port->membase + ofs->icr); 243 244 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); 245 port->icount.rx++; 246 if (sr & USART_SR_ERR_MASK) { 247 if (sr & USART_SR_ORE) { 248 port->icount.overrun++; 249 } else if (sr & USART_SR_PE) { 250 port->icount.parity++; 251 } else if (sr & USART_SR_FE) { 252 /* Break detection if character is null */ 253 if (!c) { 254 port->icount.brk++; 255 if (uart_handle_break(port)) 256 continue; 257 } else { 258 port->icount.frame++; 259 } 260 } 261 262 sr &= port->read_status_mask; 263 264 if (sr & USART_SR_PE) { 265 flag = TTY_PARITY; 266 } else if (sr & USART_SR_FE) { 267 if (!c) 268 flag = TTY_BREAK; 269 else 270 flag = TTY_FRAME; 271 } 272 } 273 274 if (uart_handle_sysrq_char(port, c)) 275 continue; 276 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 277 } 278 279 spin_unlock(&port->lock); 280 tty_flip_buffer_push(tport); 281 spin_lock(&port->lock); 282 } 283 284 static void stm32_usart_tx_dma_complete(void *arg) 285 { 286 struct uart_port *port = arg; 287 struct stm32_port *stm32port = to_stm32_port(port); 288 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 289 290 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 291 stm32port->tx_dma_busy = false; 292 293 /* Let's see if we have pending data to send */ 294 stm32_usart_transmit_chars(port); 295 } 296 297 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 298 { 299 struct stm32_port *stm32_port = to_stm32_port(port); 300 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 301 302 /* 303 * Enables TX FIFO threashold irq when FIFO is enabled, 304 * or TX empty irq when FIFO is disabled 305 */ 306 if (stm32_port->fifoen) 307 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 308 else 309 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 310 } 311 312 static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 313 { 314 struct stm32_port *stm32_port = to_stm32_port(port); 315 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 316 317 if (stm32_port->fifoen) 318 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 319 else 320 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 321 } 322 323 static void stm32_usart_transmit_chars_pio(struct uart_port *port) 324 { 325 struct stm32_port *stm32_port = to_stm32_port(port); 326 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 327 struct circ_buf *xmit = &port->state->xmit; 328 329 if (stm32_port->tx_dma_busy) { 330 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 331 stm32_port->tx_dma_busy = false; 332 } 333 334 while (!uart_circ_empty(xmit)) { 335 /* Check that TDR is empty before filling FIFO */ 336 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 337 break; 338 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 339 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 340 port->icount.tx++; 341 } 342 343 /* rely on TXE irq (mask or unmask) for sending remaining data */ 344 if (uart_circ_empty(xmit)) 345 stm32_usart_tx_interrupt_disable(port); 346 else 347 stm32_usart_tx_interrupt_enable(port); 348 } 349 350 static void stm32_usart_transmit_chars_dma(struct uart_port *port) 351 { 352 struct stm32_port *stm32port = to_stm32_port(port); 353 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 354 struct circ_buf *xmit = &port->state->xmit; 355 struct dma_async_tx_descriptor *desc = NULL; 356 unsigned int count, i; 357 358 if (stm32port->tx_dma_busy) 359 return; 360 361 stm32port->tx_dma_busy = true; 362 363 count = uart_circ_chars_pending(xmit); 364 365 if (count > TX_BUF_L) 366 count = TX_BUF_L; 367 368 if (xmit->tail < xmit->head) { 369 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 370 } else { 371 size_t one = UART_XMIT_SIZE - xmit->tail; 372 size_t two; 373 374 if (one > count) 375 one = count; 376 two = count - one; 377 378 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 379 if (two) 380 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 381 } 382 383 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 384 stm32port->tx_dma_buf, 385 count, 386 DMA_MEM_TO_DEV, 387 DMA_PREP_INTERRUPT); 388 389 if (!desc) 390 goto fallback_err; 391 392 desc->callback = stm32_usart_tx_dma_complete; 393 desc->callback_param = port; 394 395 /* Push current DMA TX transaction in the pending queue */ 396 if (dma_submit_error(dmaengine_submit(desc))) { 397 /* dma no yet started, safe to free resources */ 398 dmaengine_terminate_async(stm32port->tx_ch); 399 goto fallback_err; 400 } 401 402 /* Issue pending DMA TX requests */ 403 dma_async_issue_pending(stm32port->tx_ch); 404 405 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 406 407 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 408 port->icount.tx += count; 409 return; 410 411 fallback_err: 412 for (i = count; i > 0; i--) 413 stm32_usart_transmit_chars_pio(port); 414 } 415 416 static void stm32_usart_transmit_chars(struct uart_port *port) 417 { 418 struct stm32_port *stm32_port = to_stm32_port(port); 419 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 420 struct circ_buf *xmit = &port->state->xmit; 421 422 if (port->x_char) { 423 if (stm32_port->tx_dma_busy) 424 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 425 writel_relaxed(port->x_char, port->membase + ofs->tdr); 426 port->x_char = 0; 427 port->icount.tx++; 428 if (stm32_port->tx_dma_busy) 429 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 430 return; 431 } 432 433 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 434 stm32_usart_tx_interrupt_disable(port); 435 return; 436 } 437 438 if (ofs->icr == UNDEF_REG) 439 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 440 else 441 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 442 443 if (stm32_port->tx_ch) 444 stm32_usart_transmit_chars_dma(port); 445 else 446 stm32_usart_transmit_chars_pio(port); 447 448 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 449 uart_write_wakeup(port); 450 451 if (uart_circ_empty(xmit)) 452 stm32_usart_tx_interrupt_disable(port); 453 } 454 455 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 456 { 457 struct uart_port *port = ptr; 458 struct stm32_port *stm32_port = to_stm32_port(port); 459 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 460 u32 sr; 461 462 spin_lock(&port->lock); 463 464 sr = readl_relaxed(port->membase + ofs->isr); 465 466 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 467 writel_relaxed(USART_ICR_RTOCF, 468 port->membase + ofs->icr); 469 470 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) 471 writel_relaxed(USART_ICR_WUCF, 472 port->membase + ofs->icr); 473 474 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 475 stm32_usart_receive_chars(port, false); 476 477 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 478 stm32_usart_transmit_chars(port); 479 480 spin_unlock(&port->lock); 481 482 if (stm32_port->rx_ch) 483 return IRQ_WAKE_THREAD; 484 else 485 return IRQ_HANDLED; 486 } 487 488 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr) 489 { 490 struct uart_port *port = ptr; 491 struct stm32_port *stm32_port = to_stm32_port(port); 492 493 spin_lock(&port->lock); 494 495 if (stm32_port->rx_ch) 496 stm32_usart_receive_chars(port, true); 497 498 spin_unlock(&port->lock); 499 500 return IRQ_HANDLED; 501 } 502 503 static unsigned int stm32_usart_tx_empty(struct uart_port *port) 504 { 505 struct stm32_port *stm32_port = to_stm32_port(port); 506 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 507 508 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 509 } 510 511 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 512 { 513 struct stm32_port *stm32_port = to_stm32_port(port); 514 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 515 516 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 517 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 518 else 519 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 520 521 mctrl_gpio_set(stm32_port->gpios, mctrl); 522 } 523 524 static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 525 { 526 struct stm32_port *stm32_port = to_stm32_port(port); 527 unsigned int ret; 528 529 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 530 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 531 532 return mctrl_gpio_get(stm32_port->gpios, &ret); 533 } 534 535 static void stm32_usart_enable_ms(struct uart_port *port) 536 { 537 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 538 } 539 540 static void stm32_usart_disable_ms(struct uart_port *port) 541 { 542 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 543 } 544 545 /* Transmit stop */ 546 static void stm32_usart_stop_tx(struct uart_port *port) 547 { 548 struct stm32_port *stm32_port = to_stm32_port(port); 549 struct serial_rs485 *rs485conf = &port->rs485; 550 551 stm32_usart_tx_interrupt_disable(port); 552 553 if (rs485conf->flags & SER_RS485_ENABLED) { 554 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 555 mctrl_gpio_set(stm32_port->gpios, 556 stm32_port->port.mctrl & ~TIOCM_RTS); 557 } else { 558 mctrl_gpio_set(stm32_port->gpios, 559 stm32_port->port.mctrl | TIOCM_RTS); 560 } 561 } 562 } 563 564 /* There are probably characters waiting to be transmitted. */ 565 static void stm32_usart_start_tx(struct uart_port *port) 566 { 567 struct stm32_port *stm32_port = to_stm32_port(port); 568 struct serial_rs485 *rs485conf = &port->rs485; 569 struct circ_buf *xmit = &port->state->xmit; 570 571 if (uart_circ_empty(xmit)) 572 return; 573 574 if (rs485conf->flags & SER_RS485_ENABLED) { 575 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 576 mctrl_gpio_set(stm32_port->gpios, 577 stm32_port->port.mctrl | TIOCM_RTS); 578 } else { 579 mctrl_gpio_set(stm32_port->gpios, 580 stm32_port->port.mctrl & ~TIOCM_RTS); 581 } 582 } 583 584 stm32_usart_transmit_chars(port); 585 } 586 587 /* Throttle the remote when input buffer is about to overflow. */ 588 static void stm32_usart_throttle(struct uart_port *port) 589 { 590 struct stm32_port *stm32_port = to_stm32_port(port); 591 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 592 unsigned long flags; 593 594 spin_lock_irqsave(&port->lock, flags); 595 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 596 if (stm32_port->cr3_irq) 597 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 598 599 spin_unlock_irqrestore(&port->lock, flags); 600 } 601 602 /* Unthrottle the remote, the input buffer can now accept data. */ 603 static void stm32_usart_unthrottle(struct uart_port *port) 604 { 605 struct stm32_port *stm32_port = to_stm32_port(port); 606 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 607 unsigned long flags; 608 609 spin_lock_irqsave(&port->lock, flags); 610 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 611 if (stm32_port->cr3_irq) 612 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 613 614 spin_unlock_irqrestore(&port->lock, flags); 615 } 616 617 /* Receive stop */ 618 static void stm32_usart_stop_rx(struct uart_port *port) 619 { 620 struct stm32_port *stm32_port = to_stm32_port(port); 621 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 622 623 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 624 if (stm32_port->cr3_irq) 625 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 626 } 627 628 /* Handle breaks - ignored by us */ 629 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 630 { 631 } 632 633 static int stm32_usart_startup(struct uart_port *port) 634 { 635 struct stm32_port *stm32_port = to_stm32_port(port); 636 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 637 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 638 const char *name = to_platform_device(port->dev)->name; 639 u32 val; 640 int ret; 641 642 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, 643 stm32_usart_threaded_interrupt, 644 IRQF_NO_SUSPEND, name, port); 645 if (ret) 646 return ret; 647 648 /* RX FIFO Flush */ 649 if (ofs->rqr != UNDEF_REG) 650 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); 651 652 /* Tx and RX FIFO configuration */ 653 if (stm32_port->fifoen) { 654 val = readl_relaxed(port->membase + ofs->cr3); 655 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 656 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 657 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 658 writel_relaxed(val, port->membase + ofs->cr3); 659 } 660 661 /* RX FIFO enabling */ 662 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 663 if (stm32_port->fifoen) 664 val |= USART_CR1_FIFOEN; 665 stm32_usart_set_bits(port, ofs->cr1, val); 666 667 return 0; 668 } 669 670 static void stm32_usart_shutdown(struct uart_port *port) 671 { 672 struct stm32_port *stm32_port = to_stm32_port(port); 673 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 674 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 675 u32 val, isr; 676 int ret; 677 678 /* Disable modem control interrupts */ 679 stm32_usart_disable_ms(port); 680 681 val = USART_CR1_TXEIE | USART_CR1_TE; 682 val |= stm32_port->cr1_irq | USART_CR1_RE; 683 val |= BIT(cfg->uart_enable_bit); 684 if (stm32_port->fifoen) 685 val |= USART_CR1_FIFOEN; 686 687 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 688 isr, (isr & USART_SR_TC), 689 10, 100000); 690 691 /* Send the TC error message only when ISR_TC is not set */ 692 if (ret) 693 dev_err(port->dev, "Transmission is not complete\n"); 694 695 stm32_usart_clr_bits(port, ofs->cr1, val); 696 697 free_irq(port->irq, port); 698 } 699 700 static unsigned int stm32_usart_get_databits(struct ktermios *termios) 701 { 702 unsigned int bits; 703 704 tcflag_t cflag = termios->c_cflag; 705 706 switch (cflag & CSIZE) { 707 /* 708 * CSIZE settings are not necessarily supported in hardware. 709 * CSIZE unsupported configurations are handled here to set word length 710 * to 8 bits word as default configuration and to print debug message. 711 */ 712 case CS5: 713 bits = 5; 714 break; 715 case CS6: 716 bits = 6; 717 break; 718 case CS7: 719 bits = 7; 720 break; 721 /* default including CS8 */ 722 default: 723 bits = 8; 724 break; 725 } 726 727 return bits; 728 } 729 730 static void stm32_usart_set_termios(struct uart_port *port, 731 struct ktermios *termios, 732 struct ktermios *old) 733 { 734 struct stm32_port *stm32_port = to_stm32_port(port); 735 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 736 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 737 struct serial_rs485 *rs485conf = &port->rs485; 738 unsigned int baud, bits; 739 u32 usartdiv, mantissa, fraction, oversampling; 740 tcflag_t cflag = termios->c_cflag; 741 u32 cr1, cr2, cr3, isr; 742 unsigned long flags; 743 int ret; 744 745 if (!stm32_port->hw_flow_control) 746 cflag &= ~CRTSCTS; 747 748 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 749 750 spin_lock_irqsave(&port->lock, flags); 751 752 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 753 isr, 754 (isr & USART_SR_TC), 755 10, 100000); 756 757 /* Send the TC error message only when ISR_TC is not set. */ 758 if (ret) 759 dev_err(port->dev, "Transmission is not complete\n"); 760 761 /* Stop serial port and reset value */ 762 writel_relaxed(0, port->membase + ofs->cr1); 763 764 /* flush RX & TX FIFO */ 765 if (ofs->rqr != UNDEF_REG) 766 stm32_usart_set_bits(port, ofs->rqr, 767 USART_RQR_TXFRQ | USART_RQR_RXFRQ); 768 769 cr1 = USART_CR1_TE | USART_CR1_RE; 770 if (stm32_port->fifoen) 771 cr1 |= USART_CR1_FIFOEN; 772 cr2 = 0; 773 cr3 = readl_relaxed(port->membase + ofs->cr3); 774 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE 775 | USART_CR3_TXFTCFG_MASK; 776 777 if (cflag & CSTOPB) 778 cr2 |= USART_CR2_STOP_2B; 779 780 bits = stm32_usart_get_databits(termios); 781 stm32_port->rdr_mask = (BIT(bits) - 1); 782 783 if (cflag & PARENB) { 784 bits++; 785 cr1 |= USART_CR1_PCE; 786 } 787 788 /* 789 * Word length configuration: 790 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 791 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 792 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 793 * M0 and M1 already cleared by cr1 initialization. 794 */ 795 if (bits == 9) 796 cr1 |= USART_CR1_M0; 797 else if ((bits == 7) && cfg->has_7bits_data) 798 cr1 |= USART_CR1_M1; 799 else if (bits != 8) 800 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 801 , bits); 802 803 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 804 stm32_port->fifoen)) { 805 if (cflag & CSTOPB) 806 bits = bits + 3; /* 1 start bit + 2 stop bits */ 807 else 808 bits = bits + 2; /* 1 start bit + 1 stop bit */ 809 810 /* RX timeout irq to occur after last stop bit + bits */ 811 stm32_port->cr1_irq = USART_CR1_RTOIE; 812 writel_relaxed(bits, port->membase + ofs->rtor); 813 cr2 |= USART_CR2_RTOEN; 814 /* Not using dma, enable fifo threshold irq */ 815 if (!stm32_port->rx_ch) 816 stm32_port->cr3_irq = USART_CR3_RXFTIE; 817 } 818 819 cr1 |= stm32_port->cr1_irq; 820 cr3 |= stm32_port->cr3_irq; 821 822 if (cflag & PARODD) 823 cr1 |= USART_CR1_PS; 824 825 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 826 if (cflag & CRTSCTS) { 827 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 828 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 829 } 830 831 /* Handle modem control interrupts */ 832 if (UART_ENABLE_MS(port, termios->c_cflag)) 833 stm32_usart_enable_ms(port); 834 else 835 stm32_usart_disable_ms(port); 836 837 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 838 839 /* 840 * The USART supports 16 or 8 times oversampling. 841 * By default we prefer 16 times oversampling, so that the receiver 842 * has a better tolerance to clock deviations. 843 * 8 times oversampling is only used to achieve higher speeds. 844 */ 845 if (usartdiv < 16) { 846 oversampling = 8; 847 cr1 |= USART_CR1_OVER8; 848 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 849 } else { 850 oversampling = 16; 851 cr1 &= ~USART_CR1_OVER8; 852 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 853 } 854 855 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 856 fraction = usartdiv % oversampling; 857 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 858 859 uart_update_timeout(port, cflag, baud); 860 861 port->read_status_mask = USART_SR_ORE; 862 if (termios->c_iflag & INPCK) 863 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 864 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 865 port->read_status_mask |= USART_SR_FE; 866 867 /* Characters to ignore */ 868 port->ignore_status_mask = 0; 869 if (termios->c_iflag & IGNPAR) 870 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 871 if (termios->c_iflag & IGNBRK) { 872 port->ignore_status_mask |= USART_SR_FE; 873 /* 874 * If we're ignoring parity and break indicators, 875 * ignore overruns too (for real raw support). 876 */ 877 if (termios->c_iflag & IGNPAR) 878 port->ignore_status_mask |= USART_SR_ORE; 879 } 880 881 /* Ignore all characters if CREAD is not set */ 882 if ((termios->c_cflag & CREAD) == 0) 883 port->ignore_status_mask |= USART_SR_DUMMY_RX; 884 885 if (stm32_port->rx_ch) 886 cr3 |= USART_CR3_DMAR; 887 888 if (rs485conf->flags & SER_RS485_ENABLED) { 889 stm32_usart_config_reg_rs485(&cr1, &cr3, 890 rs485conf->delay_rts_before_send, 891 rs485conf->delay_rts_after_send, 892 baud); 893 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 894 cr3 &= ~USART_CR3_DEP; 895 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 896 } else { 897 cr3 |= USART_CR3_DEP; 898 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 899 } 900 901 } else { 902 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 903 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 904 } 905 906 writel_relaxed(cr3, port->membase + ofs->cr3); 907 writel_relaxed(cr2, port->membase + ofs->cr2); 908 writel_relaxed(cr1, port->membase + ofs->cr1); 909 910 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 911 spin_unlock_irqrestore(&port->lock, flags); 912 } 913 914 static const char *stm32_usart_type(struct uart_port *port) 915 { 916 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 917 } 918 919 static void stm32_usart_release_port(struct uart_port *port) 920 { 921 } 922 923 static int stm32_usart_request_port(struct uart_port *port) 924 { 925 return 0; 926 } 927 928 static void stm32_usart_config_port(struct uart_port *port, int flags) 929 { 930 if (flags & UART_CONFIG_TYPE) 931 port->type = PORT_STM32; 932 } 933 934 static int 935 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 936 { 937 /* No user changeable parameters */ 938 return -EINVAL; 939 } 940 941 static void stm32_usart_pm(struct uart_port *port, unsigned int state, 942 unsigned int oldstate) 943 { 944 struct stm32_port *stm32port = container_of(port, 945 struct stm32_port, port); 946 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 947 const struct stm32_usart_config *cfg = &stm32port->info->cfg; 948 unsigned long flags = 0; 949 950 switch (state) { 951 case UART_PM_STATE_ON: 952 pm_runtime_get_sync(port->dev); 953 break; 954 case UART_PM_STATE_OFF: 955 spin_lock_irqsave(&port->lock, flags); 956 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 957 spin_unlock_irqrestore(&port->lock, flags); 958 pm_runtime_put_sync(port->dev); 959 break; 960 } 961 } 962 963 static const struct uart_ops stm32_uart_ops = { 964 .tx_empty = stm32_usart_tx_empty, 965 .set_mctrl = stm32_usart_set_mctrl, 966 .get_mctrl = stm32_usart_get_mctrl, 967 .stop_tx = stm32_usart_stop_tx, 968 .start_tx = stm32_usart_start_tx, 969 .throttle = stm32_usart_throttle, 970 .unthrottle = stm32_usart_unthrottle, 971 .stop_rx = stm32_usart_stop_rx, 972 .enable_ms = stm32_usart_enable_ms, 973 .break_ctl = stm32_usart_break_ctl, 974 .startup = stm32_usart_startup, 975 .shutdown = stm32_usart_shutdown, 976 .set_termios = stm32_usart_set_termios, 977 .pm = stm32_usart_pm, 978 .type = stm32_usart_type, 979 .release_port = stm32_usart_release_port, 980 .request_port = stm32_usart_request_port, 981 .config_port = stm32_usart_config_port, 982 .verify_port = stm32_usart_verify_port, 983 }; 984 985 static void stm32_usart_deinit_port(struct stm32_port *stm32port) 986 { 987 clk_disable_unprepare(stm32port->clk); 988 } 989 990 static int stm32_usart_init_port(struct stm32_port *stm32port, 991 struct platform_device *pdev) 992 { 993 struct uart_port *port = &stm32port->port; 994 struct resource *res; 995 int ret, irq; 996 997 irq = platform_get_irq(pdev, 0); 998 if (irq <= 0) 999 return irq ? : -ENODEV; 1000 1001 port->iotype = UPIO_MEM; 1002 port->flags = UPF_BOOT_AUTOCONF; 1003 port->ops = &stm32_uart_ops; 1004 port->dev = &pdev->dev; 1005 port->fifosize = stm32port->info->cfg.fifosize; 1006 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 1007 port->irq = irq; 1008 port->rs485_config = stm32_usart_config_rs485; 1009 1010 ret = stm32_usart_init_rs485(port, pdev); 1011 if (ret) 1012 return ret; 1013 1014 if (stm32port->info->cfg.has_wakeup) { 1015 stm32port->wakeirq = platform_get_irq_optional(pdev, 1); 1016 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) 1017 return stm32port->wakeirq ? : -ENODEV; 1018 } 1019 1020 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1021 1022 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1023 port->membase = devm_ioremap_resource(&pdev->dev, res); 1024 if (IS_ERR(port->membase)) 1025 return PTR_ERR(port->membase); 1026 port->mapbase = res->start; 1027 1028 spin_lock_init(&port->lock); 1029 1030 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1031 if (IS_ERR(stm32port->clk)) 1032 return PTR_ERR(stm32port->clk); 1033 1034 /* Ensure that clk rate is correct by enabling the clk */ 1035 ret = clk_prepare_enable(stm32port->clk); 1036 if (ret) 1037 return ret; 1038 1039 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1040 if (!stm32port->port.uartclk) { 1041 ret = -EINVAL; 1042 goto err_clk; 1043 } 1044 1045 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1046 if (IS_ERR(stm32port->gpios)) { 1047 ret = PTR_ERR(stm32port->gpios); 1048 goto err_clk; 1049 } 1050 1051 /* 1052 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" 1053 * properties should not be specified. 1054 */ 1055 if (stm32port->hw_flow_control) { 1056 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1057 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1058 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1059 ret = -EINVAL; 1060 goto err_clk; 1061 } 1062 } 1063 1064 return ret; 1065 1066 err_clk: 1067 clk_disable_unprepare(stm32port->clk); 1068 1069 return ret; 1070 } 1071 1072 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1073 { 1074 struct device_node *np = pdev->dev.of_node; 1075 int id; 1076 1077 if (!np) 1078 return NULL; 1079 1080 id = of_alias_get_id(np, "serial"); 1081 if (id < 0) { 1082 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1083 return NULL; 1084 } 1085 1086 if (WARN_ON(id >= STM32_MAX_PORTS)) 1087 return NULL; 1088 1089 stm32_ports[id].hw_flow_control = 1090 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1091 of_property_read_bool (np, "uart-has-rtscts"); 1092 stm32_ports[id].port.line = id; 1093 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1094 stm32_ports[id].cr3_irq = 0; 1095 stm32_ports[id].last_res = RX_BUF_L; 1096 return &stm32_ports[id]; 1097 } 1098 1099 #ifdef CONFIG_OF 1100 static const struct of_device_id stm32_match[] = { 1101 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1102 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1103 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1104 {}, 1105 }; 1106 1107 MODULE_DEVICE_TABLE(of, stm32_match); 1108 #endif 1109 1110 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1111 struct platform_device *pdev) 1112 { 1113 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1114 struct uart_port *port = &stm32port->port; 1115 struct device *dev = &pdev->dev; 1116 struct dma_slave_config config; 1117 struct dma_async_tx_descriptor *desc = NULL; 1118 int ret; 1119 1120 /* Request DMA RX channel */ 1121 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1122 if (!stm32port->rx_ch) { 1123 dev_info(dev, "rx dma alloc failed\n"); 1124 return -ENODEV; 1125 } 1126 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1127 &stm32port->rx_dma_buf, 1128 GFP_KERNEL); 1129 if (!stm32port->rx_buf) { 1130 ret = -ENOMEM; 1131 goto alloc_err; 1132 } 1133 1134 /* Configure DMA channel */ 1135 memset(&config, 0, sizeof(config)); 1136 config.src_addr = port->mapbase + ofs->rdr; 1137 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1138 1139 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1140 if (ret < 0) { 1141 dev_err(dev, "rx dma channel config failed\n"); 1142 ret = -ENODEV; 1143 goto config_err; 1144 } 1145 1146 /* Prepare a DMA cyclic transaction */ 1147 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1148 stm32port->rx_dma_buf, 1149 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1150 DMA_PREP_INTERRUPT); 1151 if (!desc) { 1152 dev_err(dev, "rx dma prep cyclic failed\n"); 1153 ret = -ENODEV; 1154 goto config_err; 1155 } 1156 1157 /* No callback as dma buffer is drained on usart interrupt */ 1158 desc->callback = NULL; 1159 desc->callback_param = NULL; 1160 1161 /* Push current DMA transaction in the pending queue */ 1162 ret = dma_submit_error(dmaengine_submit(desc)); 1163 if (ret) { 1164 dmaengine_terminate_sync(stm32port->rx_ch); 1165 goto config_err; 1166 } 1167 1168 /* Issue pending DMA requests */ 1169 dma_async_issue_pending(stm32port->rx_ch); 1170 1171 return 0; 1172 1173 config_err: 1174 dma_free_coherent(&pdev->dev, 1175 RX_BUF_L, stm32port->rx_buf, 1176 stm32port->rx_dma_buf); 1177 1178 alloc_err: 1179 dma_release_channel(stm32port->rx_ch); 1180 stm32port->rx_ch = NULL; 1181 1182 return ret; 1183 } 1184 1185 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1186 struct platform_device *pdev) 1187 { 1188 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1189 struct uart_port *port = &stm32port->port; 1190 struct device *dev = &pdev->dev; 1191 struct dma_slave_config config; 1192 int ret; 1193 1194 stm32port->tx_dma_busy = false; 1195 1196 /* Request DMA TX channel */ 1197 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1198 if (!stm32port->tx_ch) { 1199 dev_info(dev, "tx dma alloc failed\n"); 1200 return -ENODEV; 1201 } 1202 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1203 &stm32port->tx_dma_buf, 1204 GFP_KERNEL); 1205 if (!stm32port->tx_buf) { 1206 ret = -ENOMEM; 1207 goto alloc_err; 1208 } 1209 1210 /* Configure DMA channel */ 1211 memset(&config, 0, sizeof(config)); 1212 config.dst_addr = port->mapbase + ofs->tdr; 1213 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1214 1215 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1216 if (ret < 0) { 1217 dev_err(dev, "tx dma channel config failed\n"); 1218 ret = -ENODEV; 1219 goto config_err; 1220 } 1221 1222 return 0; 1223 1224 config_err: 1225 dma_free_coherent(&pdev->dev, 1226 TX_BUF_L, stm32port->tx_buf, 1227 stm32port->tx_dma_buf); 1228 1229 alloc_err: 1230 dma_release_channel(stm32port->tx_ch); 1231 stm32port->tx_ch = NULL; 1232 1233 return ret; 1234 } 1235 1236 static int stm32_usart_serial_probe(struct platform_device *pdev) 1237 { 1238 struct stm32_port *stm32port; 1239 int ret; 1240 1241 stm32port = stm32_usart_of_get_port(pdev); 1242 if (!stm32port) 1243 return -ENODEV; 1244 1245 stm32port->info = of_device_get_match_data(&pdev->dev); 1246 if (!stm32port->info) 1247 return -EINVAL; 1248 1249 ret = stm32_usart_init_port(stm32port, pdev); 1250 if (ret) 1251 return ret; 1252 1253 if (stm32port->wakeirq > 0) { 1254 ret = device_init_wakeup(&pdev->dev, true); 1255 if (ret) 1256 goto err_uninit; 1257 1258 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1259 stm32port->wakeirq); 1260 if (ret) 1261 goto err_nowup; 1262 1263 device_set_wakeup_enable(&pdev->dev, false); 1264 } 1265 1266 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev); 1267 if (ret) 1268 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1269 1270 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev); 1271 if (ret) 1272 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1273 1274 platform_set_drvdata(pdev, &stm32port->port); 1275 1276 pm_runtime_get_noresume(&pdev->dev); 1277 pm_runtime_set_active(&pdev->dev); 1278 pm_runtime_enable(&pdev->dev); 1279 1280 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1281 if (ret) 1282 goto err_port; 1283 1284 pm_runtime_put_sync(&pdev->dev); 1285 1286 return 0; 1287 1288 err_port: 1289 pm_runtime_disable(&pdev->dev); 1290 pm_runtime_set_suspended(&pdev->dev); 1291 pm_runtime_put_noidle(&pdev->dev); 1292 1293 if (stm32port->rx_ch) { 1294 dmaengine_terminate_async(stm32port->rx_ch); 1295 dma_release_channel(stm32port->rx_ch); 1296 } 1297 1298 if (stm32port->rx_dma_buf) 1299 dma_free_coherent(&pdev->dev, 1300 RX_BUF_L, stm32port->rx_buf, 1301 stm32port->rx_dma_buf); 1302 1303 if (stm32port->tx_ch) { 1304 dmaengine_terminate_async(stm32port->tx_ch); 1305 dma_release_channel(stm32port->tx_ch); 1306 } 1307 1308 if (stm32port->tx_dma_buf) 1309 dma_free_coherent(&pdev->dev, 1310 TX_BUF_L, stm32port->tx_buf, 1311 stm32port->tx_dma_buf); 1312 1313 if (stm32port->wakeirq > 0) 1314 dev_pm_clear_wake_irq(&pdev->dev); 1315 1316 err_nowup: 1317 if (stm32port->wakeirq > 0) 1318 device_init_wakeup(&pdev->dev, false); 1319 1320 err_uninit: 1321 stm32_usart_deinit_port(stm32port); 1322 1323 return ret; 1324 } 1325 1326 static int stm32_usart_serial_remove(struct platform_device *pdev) 1327 { 1328 struct uart_port *port = platform_get_drvdata(pdev); 1329 struct stm32_port *stm32_port = to_stm32_port(port); 1330 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1331 int err; 1332 1333 pm_runtime_get_sync(&pdev->dev); 1334 err = uart_remove_one_port(&stm32_usart_driver, port); 1335 if (err) 1336 return(err); 1337 1338 pm_runtime_disable(&pdev->dev); 1339 pm_runtime_set_suspended(&pdev->dev); 1340 pm_runtime_put_noidle(&pdev->dev); 1341 1342 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1343 1344 if (stm32_port->rx_ch) { 1345 dmaengine_terminate_async(stm32_port->rx_ch); 1346 dma_release_channel(stm32_port->rx_ch); 1347 } 1348 1349 if (stm32_port->rx_dma_buf) 1350 dma_free_coherent(&pdev->dev, 1351 RX_BUF_L, stm32_port->rx_buf, 1352 stm32_port->rx_dma_buf); 1353 1354 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1355 1356 if (stm32_port->tx_ch) { 1357 dmaengine_terminate_async(stm32_port->tx_ch); 1358 dma_release_channel(stm32_port->tx_ch); 1359 } 1360 1361 if (stm32_port->tx_dma_buf) 1362 dma_free_coherent(&pdev->dev, 1363 TX_BUF_L, stm32_port->tx_buf, 1364 stm32_port->tx_dma_buf); 1365 1366 if (stm32_port->wakeirq > 0) { 1367 dev_pm_clear_wake_irq(&pdev->dev); 1368 device_init_wakeup(&pdev->dev, false); 1369 } 1370 1371 stm32_usart_deinit_port(stm32_port); 1372 1373 return 0; 1374 } 1375 1376 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1377 static void stm32_usart_console_putchar(struct uart_port *port, int ch) 1378 { 1379 struct stm32_port *stm32_port = to_stm32_port(port); 1380 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1381 1382 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1383 cpu_relax(); 1384 1385 writel_relaxed(ch, port->membase + ofs->tdr); 1386 } 1387 1388 static void stm32_usart_console_write(struct console *co, const char *s, 1389 unsigned int cnt) 1390 { 1391 struct uart_port *port = &stm32_ports[co->index].port; 1392 struct stm32_port *stm32_port = to_stm32_port(port); 1393 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1394 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1395 unsigned long flags; 1396 u32 old_cr1, new_cr1; 1397 int locked = 1; 1398 1399 local_irq_save(flags); 1400 if (port->sysrq) 1401 locked = 0; 1402 else if (oops_in_progress) 1403 locked = spin_trylock(&port->lock); 1404 else 1405 spin_lock(&port->lock); 1406 1407 /* Save and disable interrupts, enable the transmitter */ 1408 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1409 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1410 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1411 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1412 1413 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1414 1415 /* Restore interrupt state */ 1416 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1417 1418 if (locked) 1419 spin_unlock(&port->lock); 1420 local_irq_restore(flags); 1421 } 1422 1423 static int stm32_usart_console_setup(struct console *co, char *options) 1424 { 1425 struct stm32_port *stm32port; 1426 int baud = 9600; 1427 int bits = 8; 1428 int parity = 'n'; 1429 int flow = 'n'; 1430 1431 if (co->index >= STM32_MAX_PORTS) 1432 return -ENODEV; 1433 1434 stm32port = &stm32_ports[co->index]; 1435 1436 /* 1437 * This driver does not support early console initialization 1438 * (use ARM early printk support instead), so we only expect 1439 * this to be called during the uart port registration when the 1440 * driver gets probed and the port should be mapped at that point. 1441 */ 1442 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1443 return -ENXIO; 1444 1445 if (options) 1446 uart_parse_options(options, &baud, &parity, &bits, &flow); 1447 1448 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1449 } 1450 1451 static struct console stm32_console = { 1452 .name = STM32_SERIAL_NAME, 1453 .device = uart_console_device, 1454 .write = stm32_usart_console_write, 1455 .setup = stm32_usart_console_setup, 1456 .flags = CON_PRINTBUFFER, 1457 .index = -1, 1458 .data = &stm32_usart_driver, 1459 }; 1460 1461 #define STM32_SERIAL_CONSOLE (&stm32_console) 1462 1463 #else 1464 #define STM32_SERIAL_CONSOLE NULL 1465 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1466 1467 static struct uart_driver stm32_usart_driver = { 1468 .driver_name = DRIVER_NAME, 1469 .dev_name = STM32_SERIAL_NAME, 1470 .major = 0, 1471 .minor = 0, 1472 .nr = STM32_MAX_PORTS, 1473 .cons = STM32_SERIAL_CONSOLE, 1474 }; 1475 1476 static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1477 bool enable) 1478 { 1479 struct stm32_port *stm32_port = to_stm32_port(port); 1480 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1481 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1482 u32 val; 1483 1484 if (stm32_port->wakeirq <= 0) 1485 return; 1486 1487 if (enable) { 1488 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1489 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 1490 val = readl_relaxed(port->membase + ofs->cr3); 1491 val &= ~USART_CR3_WUS_MASK; 1492 /* Enable Wake up interrupt from low power on start bit */ 1493 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; 1494 writel_relaxed(val, port->membase + ofs->cr3); 1495 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1496 } else { 1497 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1498 } 1499 } 1500 1501 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 1502 { 1503 struct uart_port *port = dev_get_drvdata(dev); 1504 1505 uart_suspend_port(&stm32_usart_driver, port); 1506 1507 if (device_may_wakeup(dev)) 1508 stm32_usart_serial_en_wakeup(port, true); 1509 else 1510 stm32_usart_serial_en_wakeup(port, false); 1511 1512 /* 1513 * When "no_console_suspend" is enabled, keep the pinctrl default state 1514 * and rely on bootloader stage to restore this state upon resume. 1515 * Otherwise, apply the idle or sleep states depending on wakeup 1516 * capabilities. 1517 */ 1518 if (console_suspend_enabled || !uart_console(port)) { 1519 if (device_may_wakeup(dev)) 1520 pinctrl_pm_select_idle_state(dev); 1521 else 1522 pinctrl_pm_select_sleep_state(dev); 1523 } 1524 1525 return 0; 1526 } 1527 1528 static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 1529 { 1530 struct uart_port *port = dev_get_drvdata(dev); 1531 1532 pinctrl_pm_select_default_state(dev); 1533 1534 if (device_may_wakeup(dev)) 1535 stm32_usart_serial_en_wakeup(port, false); 1536 1537 return uart_resume_port(&stm32_usart_driver, port); 1538 } 1539 1540 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 1541 { 1542 struct uart_port *port = dev_get_drvdata(dev); 1543 struct stm32_port *stm32port = container_of(port, 1544 struct stm32_port, port); 1545 1546 clk_disable_unprepare(stm32port->clk); 1547 1548 return 0; 1549 } 1550 1551 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 1552 { 1553 struct uart_port *port = dev_get_drvdata(dev); 1554 struct stm32_port *stm32port = container_of(port, 1555 struct stm32_port, port); 1556 1557 return clk_prepare_enable(stm32port->clk); 1558 } 1559 1560 static const struct dev_pm_ops stm32_serial_pm_ops = { 1561 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 1562 stm32_usart_runtime_resume, NULL) 1563 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 1564 stm32_usart_serial_resume) 1565 }; 1566 1567 static struct platform_driver stm32_serial_driver = { 1568 .probe = stm32_usart_serial_probe, 1569 .remove = stm32_usart_serial_remove, 1570 .driver = { 1571 .name = DRIVER_NAME, 1572 .pm = &stm32_serial_pm_ops, 1573 .of_match_table = of_match_ptr(stm32_match), 1574 }, 1575 }; 1576 1577 static int __init stm32_usart_init(void) 1578 { 1579 static char banner[] __initdata = "STM32 USART driver initialized"; 1580 int ret; 1581 1582 pr_info("%s\n", banner); 1583 1584 ret = uart_register_driver(&stm32_usart_driver); 1585 if (ret) 1586 return ret; 1587 1588 ret = platform_driver_register(&stm32_serial_driver); 1589 if (ret) 1590 uart_unregister_driver(&stm32_usart_driver); 1591 1592 return ret; 1593 } 1594 1595 static void __exit stm32_usart_exit(void) 1596 { 1597 platform_driver_unregister(&stm32_serial_driver); 1598 uart_unregister_driver(&stm32_usart_driver); 1599 } 1600 1601 module_init(stm32_usart_init); 1602 module_exit(stm32_usart_exit); 1603 1604 MODULE_ALIAS("platform:" DRIVER_NAME); 1605 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1606 MODULE_LICENSE("GPL v2"); 1607