1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@st.com> 7 * 8 * Inspired by st-asc.c from STMicroelectronics (c) 9 */ 10 11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12 #define SUPPORT_SYSRQ 13 #endif 14 15 #include <linux/clk.h> 16 #include <linux/console.h> 17 #include <linux/delay.h> 18 #include <linux/dma-direction.h> 19 #include <linux/dmaengine.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/irq.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/pm_wakeirq.h> 30 #include <linux/serial_core.h> 31 #include <linux/serial.h> 32 #include <linux/spinlock.h> 33 #include <linux/sysrq.h> 34 #include <linux/tty_flip.h> 35 #include <linux/tty.h> 36 37 #include "stm32-usart.h" 38 39 static void stm32_stop_tx(struct uart_port *port); 40 static void stm32_transmit_chars(struct uart_port *port); 41 42 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 43 { 44 return container_of(port, struct stm32_port, port); 45 } 46 47 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) 48 { 49 u32 val; 50 51 val = readl_relaxed(port->membase + reg); 52 val |= bits; 53 writel_relaxed(val, port->membase + reg); 54 } 55 56 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) 57 { 58 u32 val; 59 60 val = readl_relaxed(port->membase + reg); 61 val &= ~bits; 62 writel_relaxed(val, port->membase + reg); 63 } 64 65 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 66 u32 delay_DDE, u32 baud) 67 { 68 u32 rs485_deat_dedt; 69 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 70 bool over8; 71 72 *cr3 |= USART_CR3_DEM; 73 over8 = *cr1 & USART_CR1_OVER8; 74 75 if (over8) 76 rs485_deat_dedt = delay_ADE * baud * 8; 77 else 78 rs485_deat_dedt = delay_ADE * baud * 16; 79 80 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 81 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 82 rs485_deat_dedt_max : rs485_deat_dedt; 83 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 84 USART_CR1_DEAT_MASK; 85 *cr1 |= rs485_deat_dedt; 86 87 if (over8) 88 rs485_deat_dedt = delay_DDE * baud * 8; 89 else 90 rs485_deat_dedt = delay_DDE * baud * 16; 91 92 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 93 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 94 rs485_deat_dedt_max : rs485_deat_dedt; 95 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 96 USART_CR1_DEDT_MASK; 97 *cr1 |= rs485_deat_dedt; 98 } 99 100 static int stm32_config_rs485(struct uart_port *port, 101 struct serial_rs485 *rs485conf) 102 { 103 struct stm32_port *stm32_port = to_stm32_port(port); 104 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 105 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 106 u32 usartdiv, baud, cr1, cr3; 107 bool over8; 108 unsigned long flags; 109 110 spin_lock_irqsave(&port->lock, flags); 111 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 112 113 port->rs485 = *rs485conf; 114 115 rs485conf->flags |= SER_RS485_RX_DURING_TX; 116 117 if (rs485conf->flags & SER_RS485_ENABLED) { 118 cr1 = readl_relaxed(port->membase + ofs->cr1); 119 cr3 = readl_relaxed(port->membase + ofs->cr3); 120 usartdiv = readl_relaxed(port->membase + ofs->brr); 121 usartdiv = usartdiv & GENMASK(15, 0); 122 over8 = cr1 & USART_CR1_OVER8; 123 124 if (over8) 125 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 126 << USART_BRR_04_R_SHIFT; 127 128 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 129 stm32_config_reg_rs485(&cr1, &cr3, 130 rs485conf->delay_rts_before_send, 131 rs485conf->delay_rts_after_send, baud); 132 133 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 134 cr3 &= ~USART_CR3_DEP; 135 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 136 } else { 137 cr3 |= USART_CR3_DEP; 138 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 139 } 140 141 writel_relaxed(cr3, port->membase + ofs->cr3); 142 writel_relaxed(cr1, port->membase + ofs->cr1); 143 } else { 144 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP); 145 stm32_clr_bits(port, ofs->cr1, 146 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 147 } 148 149 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 150 spin_unlock_irqrestore(&port->lock, flags); 151 152 return 0; 153 } 154 155 static int stm32_init_rs485(struct uart_port *port, 156 struct platform_device *pdev) 157 { 158 struct serial_rs485 *rs485conf = &port->rs485; 159 160 rs485conf->flags = 0; 161 rs485conf->delay_rts_before_send = 0; 162 rs485conf->delay_rts_after_send = 0; 163 164 if (!pdev->dev.of_node) 165 return -ENODEV; 166 167 uart_get_rs485_mode(&pdev->dev, rs485conf); 168 169 return 0; 170 } 171 172 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, 173 bool threaded) 174 { 175 struct stm32_port *stm32_port = to_stm32_port(port); 176 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 177 enum dma_status status; 178 struct dma_tx_state state; 179 180 *sr = readl_relaxed(port->membase + ofs->isr); 181 182 if (threaded && stm32_port->rx_ch) { 183 status = dmaengine_tx_status(stm32_port->rx_ch, 184 stm32_port->rx_ch->cookie, 185 &state); 186 if ((status == DMA_IN_PROGRESS) && 187 (*last_res != state.residue)) 188 return 1; 189 else 190 return 0; 191 } else if (*sr & USART_SR_RXNE) { 192 return 1; 193 } 194 return 0; 195 } 196 197 static unsigned long 198 stm32_get_char(struct uart_port *port, u32 *sr, int *last_res) 199 { 200 struct stm32_port *stm32_port = to_stm32_port(port); 201 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 202 unsigned long c; 203 204 if (stm32_port->rx_ch) { 205 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 206 if ((*last_res) == 0) 207 *last_res = RX_BUF_L; 208 return c; 209 } else { 210 return readl_relaxed(port->membase + ofs->rdr); 211 } 212 } 213 214 static void stm32_receive_chars(struct uart_port *port, bool threaded) 215 { 216 struct tty_port *tport = &port->state->port; 217 struct stm32_port *stm32_port = to_stm32_port(port); 218 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 219 unsigned long c; 220 u32 sr; 221 char flag; 222 223 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 224 pm_wakeup_event(tport->tty->dev, 0); 225 226 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) { 227 sr |= USART_SR_DUMMY_RX; 228 c = stm32_get_char(port, &sr, &stm32_port->last_res); 229 flag = TTY_NORMAL; 230 port->icount.rx++; 231 232 if (sr & USART_SR_ERR_MASK) { 233 if (sr & USART_SR_LBD) { 234 port->icount.brk++; 235 if (uart_handle_break(port)) 236 continue; 237 } else if (sr & USART_SR_ORE) { 238 if (ofs->icr != UNDEF_REG) 239 writel_relaxed(USART_ICR_ORECF, 240 port->membase + 241 ofs->icr); 242 port->icount.overrun++; 243 } else if (sr & USART_SR_PE) { 244 port->icount.parity++; 245 } else if (sr & USART_SR_FE) { 246 port->icount.frame++; 247 } 248 249 sr &= port->read_status_mask; 250 251 if (sr & USART_SR_LBD) 252 flag = TTY_BREAK; 253 else if (sr & USART_SR_PE) 254 flag = TTY_PARITY; 255 else if (sr & USART_SR_FE) 256 flag = TTY_FRAME; 257 } 258 259 if (uart_handle_sysrq_char(port, c)) 260 continue; 261 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 262 } 263 264 spin_unlock(&port->lock); 265 tty_flip_buffer_push(tport); 266 spin_lock(&port->lock); 267 } 268 269 static void stm32_tx_dma_complete(void *arg) 270 { 271 struct uart_port *port = arg; 272 struct stm32_port *stm32port = to_stm32_port(port); 273 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 274 unsigned int isr; 275 int ret; 276 277 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 278 isr, 279 (isr & USART_SR_TC), 280 10, 100000); 281 282 if (ret) 283 dev_err(port->dev, "terminal count not set\n"); 284 285 if (ofs->icr == UNDEF_REG) 286 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 287 else 288 stm32_set_bits(port, ofs->icr, USART_CR_TC); 289 290 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 291 stm32port->tx_dma_busy = false; 292 293 /* Let's see if we have pending data to send */ 294 stm32_transmit_chars(port); 295 } 296 297 static void stm32_transmit_chars_pio(struct uart_port *port) 298 { 299 struct stm32_port *stm32_port = to_stm32_port(port); 300 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 301 struct circ_buf *xmit = &port->state->xmit; 302 unsigned int isr; 303 int ret; 304 305 if (stm32_port->tx_dma_busy) { 306 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 307 stm32_port->tx_dma_busy = false; 308 } 309 310 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 311 isr, 312 (isr & USART_SR_TXE), 313 10, 100000); 314 315 if (ret) 316 dev_err(port->dev, "tx empty not set\n"); 317 318 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 319 320 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 321 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 322 port->icount.tx++; 323 } 324 325 static void stm32_transmit_chars_dma(struct uart_port *port) 326 { 327 struct stm32_port *stm32port = to_stm32_port(port); 328 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 329 struct circ_buf *xmit = &port->state->xmit; 330 struct dma_async_tx_descriptor *desc = NULL; 331 dma_cookie_t cookie; 332 unsigned int count, i; 333 334 if (stm32port->tx_dma_busy) 335 return; 336 337 stm32port->tx_dma_busy = true; 338 339 count = uart_circ_chars_pending(xmit); 340 341 if (count > TX_BUF_L) 342 count = TX_BUF_L; 343 344 if (xmit->tail < xmit->head) { 345 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 346 } else { 347 size_t one = UART_XMIT_SIZE - xmit->tail; 348 size_t two; 349 350 if (one > count) 351 one = count; 352 two = count - one; 353 354 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 355 if (two) 356 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 357 } 358 359 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 360 stm32port->tx_dma_buf, 361 count, 362 DMA_MEM_TO_DEV, 363 DMA_PREP_INTERRUPT); 364 365 if (!desc) { 366 for (i = count; i > 0; i--) 367 stm32_transmit_chars_pio(port); 368 return; 369 } 370 371 desc->callback = stm32_tx_dma_complete; 372 desc->callback_param = port; 373 374 /* Push current DMA TX transaction in the pending queue */ 375 cookie = dmaengine_submit(desc); 376 377 /* Issue pending DMA TX requests */ 378 dma_async_issue_pending(stm32port->tx_ch); 379 380 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 381 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 382 383 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 384 port->icount.tx += count; 385 } 386 387 static void stm32_transmit_chars(struct uart_port *port) 388 { 389 struct stm32_port *stm32_port = to_stm32_port(port); 390 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 391 struct circ_buf *xmit = &port->state->xmit; 392 393 if (port->x_char) { 394 if (stm32_port->tx_dma_busy) 395 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 396 writel_relaxed(port->x_char, port->membase + ofs->tdr); 397 port->x_char = 0; 398 port->icount.tx++; 399 if (stm32_port->tx_dma_busy) 400 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 401 return; 402 } 403 404 if (uart_tx_stopped(port)) { 405 stm32_stop_tx(port); 406 return; 407 } 408 409 if (uart_circ_empty(xmit)) { 410 stm32_stop_tx(port); 411 return; 412 } 413 414 if (stm32_port->tx_ch) 415 stm32_transmit_chars_dma(port); 416 else 417 stm32_transmit_chars_pio(port); 418 419 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 420 uart_write_wakeup(port); 421 422 if (uart_circ_empty(xmit)) 423 stm32_stop_tx(port); 424 } 425 426 static irqreturn_t stm32_interrupt(int irq, void *ptr) 427 { 428 struct uart_port *port = ptr; 429 struct stm32_port *stm32_port = to_stm32_port(port); 430 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 431 u32 sr; 432 433 spin_lock(&port->lock); 434 435 sr = readl_relaxed(port->membase + ofs->isr); 436 437 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG)) 438 writel_relaxed(USART_ICR_WUCF, 439 port->membase + ofs->icr); 440 441 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 442 stm32_receive_chars(port, false); 443 444 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 445 stm32_transmit_chars(port); 446 447 spin_unlock(&port->lock); 448 449 if (stm32_port->rx_ch) 450 return IRQ_WAKE_THREAD; 451 else 452 return IRQ_HANDLED; 453 } 454 455 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr) 456 { 457 struct uart_port *port = ptr; 458 struct stm32_port *stm32_port = to_stm32_port(port); 459 460 spin_lock(&port->lock); 461 462 if (stm32_port->rx_ch) 463 stm32_receive_chars(port, true); 464 465 spin_unlock(&port->lock); 466 467 return IRQ_HANDLED; 468 } 469 470 static unsigned int stm32_tx_empty(struct uart_port *port) 471 { 472 struct stm32_port *stm32_port = to_stm32_port(port); 473 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 474 475 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 476 } 477 478 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) 479 { 480 struct stm32_port *stm32_port = to_stm32_port(port); 481 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 482 483 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 484 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); 485 else 486 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 487 } 488 489 static unsigned int stm32_get_mctrl(struct uart_port *port) 490 { 491 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 492 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 493 } 494 495 /* Transmit stop */ 496 static void stm32_stop_tx(struct uart_port *port) 497 { 498 struct stm32_port *stm32_port = to_stm32_port(port); 499 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 500 501 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 502 } 503 504 /* There are probably characters waiting to be transmitted. */ 505 static void stm32_start_tx(struct uart_port *port) 506 { 507 struct circ_buf *xmit = &port->state->xmit; 508 509 if (uart_circ_empty(xmit)) 510 return; 511 512 stm32_transmit_chars(port); 513 } 514 515 /* Throttle the remote when input buffer is about to overflow. */ 516 static void stm32_throttle(struct uart_port *port) 517 { 518 struct stm32_port *stm32_port = to_stm32_port(port); 519 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 520 unsigned long flags; 521 522 spin_lock_irqsave(&port->lock, flags); 523 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 524 spin_unlock_irqrestore(&port->lock, flags); 525 } 526 527 /* Unthrottle the remote, the input buffer can now accept data. */ 528 static void stm32_unthrottle(struct uart_port *port) 529 { 530 struct stm32_port *stm32_port = to_stm32_port(port); 531 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 532 unsigned long flags; 533 534 spin_lock_irqsave(&port->lock, flags); 535 stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE); 536 spin_unlock_irqrestore(&port->lock, flags); 537 } 538 539 /* Receive stop */ 540 static void stm32_stop_rx(struct uart_port *port) 541 { 542 struct stm32_port *stm32_port = to_stm32_port(port); 543 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 544 545 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 546 } 547 548 /* Handle breaks - ignored by us */ 549 static void stm32_break_ctl(struct uart_port *port, int break_state) 550 { 551 } 552 553 static int stm32_startup(struct uart_port *port) 554 { 555 struct stm32_port *stm32_port = to_stm32_port(port); 556 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 557 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 558 const char *name = to_platform_device(port->dev)->name; 559 u32 val; 560 int ret; 561 562 ret = request_threaded_irq(port->irq, stm32_interrupt, 563 stm32_threaded_interrupt, 564 IRQF_NO_SUSPEND, name, port); 565 if (ret) 566 return ret; 567 568 if (cfg->has_wakeup && stm32_port->wakeirq >= 0) { 569 ret = dev_pm_set_dedicated_wake_irq(port->dev, 570 stm32_port->wakeirq); 571 if (ret) { 572 free_irq(port->irq, port); 573 return ret; 574 } 575 } 576 577 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 578 if (stm32_port->fifoen) 579 val |= USART_CR1_FIFOEN; 580 stm32_set_bits(port, ofs->cr1, val); 581 582 return 0; 583 } 584 585 static void stm32_shutdown(struct uart_port *port) 586 { 587 struct stm32_port *stm32_port = to_stm32_port(port); 588 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 589 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 590 u32 val; 591 592 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 593 val |= BIT(cfg->uart_enable_bit); 594 if (stm32_port->fifoen) 595 val |= USART_CR1_FIFOEN; 596 stm32_clr_bits(port, ofs->cr1, val); 597 598 dev_pm_clear_wake_irq(port->dev); 599 free_irq(port->irq, port); 600 } 601 602 unsigned int stm32_get_databits(struct ktermios *termios) 603 { 604 unsigned int bits; 605 606 tcflag_t cflag = termios->c_cflag; 607 608 switch (cflag & CSIZE) { 609 /* 610 * CSIZE settings are not necessarily supported in hardware. 611 * CSIZE unsupported configurations are handled here to set word length 612 * to 8 bits word as default configuration and to print debug message. 613 */ 614 case CS5: 615 bits = 5; 616 break; 617 case CS6: 618 bits = 6; 619 break; 620 case CS7: 621 bits = 7; 622 break; 623 /* default including CS8 */ 624 default: 625 bits = 8; 626 break; 627 } 628 629 return bits; 630 } 631 632 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, 633 struct ktermios *old) 634 { 635 struct stm32_port *stm32_port = to_stm32_port(port); 636 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 637 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 638 struct serial_rs485 *rs485conf = &port->rs485; 639 unsigned int baud, bits; 640 u32 usartdiv, mantissa, fraction, oversampling; 641 tcflag_t cflag = termios->c_cflag; 642 u32 cr1, cr2, cr3; 643 unsigned long flags; 644 645 if (!stm32_port->hw_flow_control) 646 cflag &= ~CRTSCTS; 647 648 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 649 650 spin_lock_irqsave(&port->lock, flags); 651 652 /* Stop serial port and reset value */ 653 writel_relaxed(0, port->membase + ofs->cr1); 654 655 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE; 656 657 if (stm32_port->fifoen) 658 cr1 |= USART_CR1_FIFOEN; 659 cr2 = 0; 660 cr3 = 0; 661 662 if (cflag & CSTOPB) 663 cr2 |= USART_CR2_STOP_2B; 664 665 bits = stm32_get_databits(termios); 666 667 if (cflag & PARENB) { 668 bits++; 669 cr1 |= USART_CR1_PCE; 670 } 671 672 /* 673 * Word length configuration: 674 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 675 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 676 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 677 * M0 and M1 already cleared by cr1 initialization. 678 */ 679 if (bits == 9) 680 cr1 |= USART_CR1_M0; 681 else if ((bits == 7) && cfg->has_7bits_data) 682 cr1 |= USART_CR1_M1; 683 else if (bits != 8) 684 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 685 , bits); 686 687 if (cflag & PARODD) 688 cr1 |= USART_CR1_PS; 689 690 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 691 if (cflag & CRTSCTS) { 692 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 693 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 694 } 695 696 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 697 698 /* 699 * The USART supports 16 or 8 times oversampling. 700 * By default we prefer 16 times oversampling, so that the receiver 701 * has a better tolerance to clock deviations. 702 * 8 times oversampling is only used to achieve higher speeds. 703 */ 704 if (usartdiv < 16) { 705 oversampling = 8; 706 cr1 |= USART_CR1_OVER8; 707 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); 708 } else { 709 oversampling = 16; 710 cr1 &= ~USART_CR1_OVER8; 711 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 712 } 713 714 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 715 fraction = usartdiv % oversampling; 716 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 717 718 uart_update_timeout(port, cflag, baud); 719 720 port->read_status_mask = USART_SR_ORE; 721 if (termios->c_iflag & INPCK) 722 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 723 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 724 port->read_status_mask |= USART_SR_LBD; 725 726 /* Characters to ignore */ 727 port->ignore_status_mask = 0; 728 if (termios->c_iflag & IGNPAR) 729 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 730 if (termios->c_iflag & IGNBRK) { 731 port->ignore_status_mask |= USART_SR_LBD; 732 /* 733 * If we're ignoring parity and break indicators, 734 * ignore overruns too (for real raw support). 735 */ 736 if (termios->c_iflag & IGNPAR) 737 port->ignore_status_mask |= USART_SR_ORE; 738 } 739 740 /* Ignore all characters if CREAD is not set */ 741 if ((termios->c_cflag & CREAD) == 0) 742 port->ignore_status_mask |= USART_SR_DUMMY_RX; 743 744 if (stm32_port->rx_ch) 745 cr3 |= USART_CR3_DMAR; 746 747 if (rs485conf->flags & SER_RS485_ENABLED) { 748 stm32_config_reg_rs485(&cr1, &cr3, 749 rs485conf->delay_rts_before_send, 750 rs485conf->delay_rts_after_send, baud); 751 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 752 cr3 &= ~USART_CR3_DEP; 753 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 754 } else { 755 cr3 |= USART_CR3_DEP; 756 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 757 } 758 759 } else { 760 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 761 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 762 } 763 764 writel_relaxed(cr3, port->membase + ofs->cr3); 765 writel_relaxed(cr2, port->membase + ofs->cr2); 766 writel_relaxed(cr1, port->membase + ofs->cr1); 767 768 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 769 spin_unlock_irqrestore(&port->lock, flags); 770 } 771 772 static const char *stm32_type(struct uart_port *port) 773 { 774 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 775 } 776 777 static void stm32_release_port(struct uart_port *port) 778 { 779 } 780 781 static int stm32_request_port(struct uart_port *port) 782 { 783 return 0; 784 } 785 786 static void stm32_config_port(struct uart_port *port, int flags) 787 { 788 if (flags & UART_CONFIG_TYPE) 789 port->type = PORT_STM32; 790 } 791 792 static int 793 stm32_verify_port(struct uart_port *port, struct serial_struct *ser) 794 { 795 /* No user changeable parameters */ 796 return -EINVAL; 797 } 798 799 static void stm32_pm(struct uart_port *port, unsigned int state, 800 unsigned int oldstate) 801 { 802 struct stm32_port *stm32port = container_of(port, 803 struct stm32_port, port); 804 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 805 struct stm32_usart_config *cfg = &stm32port->info->cfg; 806 unsigned long flags = 0; 807 808 switch (state) { 809 case UART_PM_STATE_ON: 810 clk_prepare_enable(stm32port->clk); 811 break; 812 case UART_PM_STATE_OFF: 813 spin_lock_irqsave(&port->lock, flags); 814 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 815 spin_unlock_irqrestore(&port->lock, flags); 816 clk_disable_unprepare(stm32port->clk); 817 break; 818 } 819 } 820 821 static const struct uart_ops stm32_uart_ops = { 822 .tx_empty = stm32_tx_empty, 823 .set_mctrl = stm32_set_mctrl, 824 .get_mctrl = stm32_get_mctrl, 825 .stop_tx = stm32_stop_tx, 826 .start_tx = stm32_start_tx, 827 .throttle = stm32_throttle, 828 .unthrottle = stm32_unthrottle, 829 .stop_rx = stm32_stop_rx, 830 .break_ctl = stm32_break_ctl, 831 .startup = stm32_startup, 832 .shutdown = stm32_shutdown, 833 .set_termios = stm32_set_termios, 834 .pm = stm32_pm, 835 .type = stm32_type, 836 .release_port = stm32_release_port, 837 .request_port = stm32_request_port, 838 .config_port = stm32_config_port, 839 .verify_port = stm32_verify_port, 840 }; 841 842 static int stm32_init_port(struct stm32_port *stm32port, 843 struct platform_device *pdev) 844 { 845 struct uart_port *port = &stm32port->port; 846 struct resource *res; 847 int ret; 848 849 port->iotype = UPIO_MEM; 850 port->flags = UPF_BOOT_AUTOCONF; 851 port->ops = &stm32_uart_ops; 852 port->dev = &pdev->dev; 853 port->irq = platform_get_irq(pdev, 0); 854 port->rs485_config = stm32_config_rs485; 855 856 stm32_init_rs485(port, pdev); 857 858 stm32port->wakeirq = platform_get_irq(pdev, 1); 859 stm32port->fifoen = stm32port->info->cfg.has_fifo; 860 861 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 862 port->membase = devm_ioremap_resource(&pdev->dev, res); 863 if (IS_ERR(port->membase)) 864 return PTR_ERR(port->membase); 865 port->mapbase = res->start; 866 867 spin_lock_init(&port->lock); 868 869 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 870 if (IS_ERR(stm32port->clk)) 871 return PTR_ERR(stm32port->clk); 872 873 /* Ensure that clk rate is correct by enabling the clk */ 874 ret = clk_prepare_enable(stm32port->clk); 875 if (ret) 876 return ret; 877 878 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 879 if (!stm32port->port.uartclk) { 880 clk_disable_unprepare(stm32port->clk); 881 ret = -EINVAL; 882 } 883 884 return ret; 885 } 886 887 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) 888 { 889 struct device_node *np = pdev->dev.of_node; 890 int id; 891 892 if (!np) 893 return NULL; 894 895 id = of_alias_get_id(np, "serial"); 896 if (id < 0) { 897 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 898 return NULL; 899 } 900 901 if (WARN_ON(id >= STM32_MAX_PORTS)) 902 return NULL; 903 904 stm32_ports[id].hw_flow_control = of_property_read_bool(np, 905 "st,hw-flow-ctrl"); 906 stm32_ports[id].port.line = id; 907 stm32_ports[id].last_res = RX_BUF_L; 908 return &stm32_ports[id]; 909 } 910 911 #ifdef CONFIG_OF 912 static const struct of_device_id stm32_match[] = { 913 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 914 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 915 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 916 {}, 917 }; 918 919 MODULE_DEVICE_TABLE(of, stm32_match); 920 #endif 921 922 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port, 923 struct platform_device *pdev) 924 { 925 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 926 struct uart_port *port = &stm32port->port; 927 struct device *dev = &pdev->dev; 928 struct dma_slave_config config; 929 struct dma_async_tx_descriptor *desc = NULL; 930 dma_cookie_t cookie; 931 int ret; 932 933 /* Request DMA RX channel */ 934 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 935 if (!stm32port->rx_ch) { 936 dev_info(dev, "rx dma alloc failed\n"); 937 return -ENODEV; 938 } 939 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 940 &stm32port->rx_dma_buf, 941 GFP_KERNEL); 942 if (!stm32port->rx_buf) { 943 ret = -ENOMEM; 944 goto alloc_err; 945 } 946 947 /* Configure DMA channel */ 948 memset(&config, 0, sizeof(config)); 949 config.src_addr = port->mapbase + ofs->rdr; 950 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 951 952 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 953 if (ret < 0) { 954 dev_err(dev, "rx dma channel config failed\n"); 955 ret = -ENODEV; 956 goto config_err; 957 } 958 959 /* Prepare a DMA cyclic transaction */ 960 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 961 stm32port->rx_dma_buf, 962 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 963 DMA_PREP_INTERRUPT); 964 if (!desc) { 965 dev_err(dev, "rx dma prep cyclic failed\n"); 966 ret = -ENODEV; 967 goto config_err; 968 } 969 970 /* No callback as dma buffer is drained on usart interrupt */ 971 desc->callback = NULL; 972 desc->callback_param = NULL; 973 974 /* Push current DMA transaction in the pending queue */ 975 cookie = dmaengine_submit(desc); 976 977 /* Issue pending DMA requests */ 978 dma_async_issue_pending(stm32port->rx_ch); 979 980 return 0; 981 982 config_err: 983 dma_free_coherent(&pdev->dev, 984 RX_BUF_L, stm32port->rx_buf, 985 stm32port->rx_dma_buf); 986 987 alloc_err: 988 dma_release_channel(stm32port->rx_ch); 989 stm32port->rx_ch = NULL; 990 991 return ret; 992 } 993 994 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port, 995 struct platform_device *pdev) 996 { 997 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 998 struct uart_port *port = &stm32port->port; 999 struct device *dev = &pdev->dev; 1000 struct dma_slave_config config; 1001 int ret; 1002 1003 stm32port->tx_dma_busy = false; 1004 1005 /* Request DMA TX channel */ 1006 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1007 if (!stm32port->tx_ch) { 1008 dev_info(dev, "tx dma alloc failed\n"); 1009 return -ENODEV; 1010 } 1011 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1012 &stm32port->tx_dma_buf, 1013 GFP_KERNEL); 1014 if (!stm32port->tx_buf) { 1015 ret = -ENOMEM; 1016 goto alloc_err; 1017 } 1018 1019 /* Configure DMA channel */ 1020 memset(&config, 0, sizeof(config)); 1021 config.dst_addr = port->mapbase + ofs->tdr; 1022 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1023 1024 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1025 if (ret < 0) { 1026 dev_err(dev, "tx dma channel config failed\n"); 1027 ret = -ENODEV; 1028 goto config_err; 1029 } 1030 1031 return 0; 1032 1033 config_err: 1034 dma_free_coherent(&pdev->dev, 1035 TX_BUF_L, stm32port->tx_buf, 1036 stm32port->tx_dma_buf); 1037 1038 alloc_err: 1039 dma_release_channel(stm32port->tx_ch); 1040 stm32port->tx_ch = NULL; 1041 1042 return ret; 1043 } 1044 1045 static int stm32_serial_probe(struct platform_device *pdev) 1046 { 1047 const struct of_device_id *match; 1048 struct stm32_port *stm32port; 1049 int ret; 1050 1051 stm32port = stm32_of_get_stm32_port(pdev); 1052 if (!stm32port) 1053 return -ENODEV; 1054 1055 match = of_match_device(stm32_match, &pdev->dev); 1056 if (match && match->data) 1057 stm32port->info = (struct stm32_usart_info *)match->data; 1058 else 1059 return -EINVAL; 1060 1061 ret = stm32_init_port(stm32port, pdev); 1062 if (ret) 1063 return ret; 1064 1065 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) { 1066 ret = device_init_wakeup(&pdev->dev, true); 1067 if (ret) 1068 goto err_uninit; 1069 } 1070 1071 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1072 if (ret) 1073 goto err_nowup; 1074 1075 ret = stm32_of_dma_rx_probe(stm32port, pdev); 1076 if (ret) 1077 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1078 1079 ret = stm32_of_dma_tx_probe(stm32port, pdev); 1080 if (ret) 1081 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1082 1083 platform_set_drvdata(pdev, &stm32port->port); 1084 1085 return 0; 1086 1087 err_nowup: 1088 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) 1089 device_init_wakeup(&pdev->dev, false); 1090 1091 err_uninit: 1092 clk_disable_unprepare(stm32port->clk); 1093 1094 return ret; 1095 } 1096 1097 static int stm32_serial_remove(struct platform_device *pdev) 1098 { 1099 struct uart_port *port = platform_get_drvdata(pdev); 1100 struct stm32_port *stm32_port = to_stm32_port(port); 1101 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1102 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1103 1104 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1105 1106 if (stm32_port->rx_ch) 1107 dma_release_channel(stm32_port->rx_ch); 1108 1109 if (stm32_port->rx_dma_buf) 1110 dma_free_coherent(&pdev->dev, 1111 RX_BUF_L, stm32_port->rx_buf, 1112 stm32_port->rx_dma_buf); 1113 1114 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1115 1116 if (stm32_port->tx_ch) 1117 dma_release_channel(stm32_port->tx_ch); 1118 1119 if (stm32_port->tx_dma_buf) 1120 dma_free_coherent(&pdev->dev, 1121 TX_BUF_L, stm32_port->tx_buf, 1122 stm32_port->tx_dma_buf); 1123 1124 if (cfg->has_wakeup && stm32_port->wakeirq >= 0) 1125 device_init_wakeup(&pdev->dev, false); 1126 1127 clk_disable_unprepare(stm32_port->clk); 1128 1129 return uart_remove_one_port(&stm32_usart_driver, port); 1130 } 1131 1132 1133 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1134 static void stm32_console_putchar(struct uart_port *port, int ch) 1135 { 1136 struct stm32_port *stm32_port = to_stm32_port(port); 1137 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1138 1139 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1140 cpu_relax(); 1141 1142 writel_relaxed(ch, port->membase + ofs->tdr); 1143 } 1144 1145 static void stm32_console_write(struct console *co, const char *s, unsigned cnt) 1146 { 1147 struct uart_port *port = &stm32_ports[co->index].port; 1148 struct stm32_port *stm32_port = to_stm32_port(port); 1149 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1150 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1151 unsigned long flags; 1152 u32 old_cr1, new_cr1; 1153 int locked = 1; 1154 1155 local_irq_save(flags); 1156 if (port->sysrq) 1157 locked = 0; 1158 else if (oops_in_progress) 1159 locked = spin_trylock(&port->lock); 1160 else 1161 spin_lock(&port->lock); 1162 1163 /* Save and disable interrupts, enable the transmitter */ 1164 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1165 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1166 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1167 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1168 1169 uart_console_write(port, s, cnt, stm32_console_putchar); 1170 1171 /* Restore interrupt state */ 1172 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1173 1174 if (locked) 1175 spin_unlock(&port->lock); 1176 local_irq_restore(flags); 1177 } 1178 1179 static int stm32_console_setup(struct console *co, char *options) 1180 { 1181 struct stm32_port *stm32port; 1182 int baud = 9600; 1183 int bits = 8; 1184 int parity = 'n'; 1185 int flow = 'n'; 1186 1187 if (co->index >= STM32_MAX_PORTS) 1188 return -ENODEV; 1189 1190 stm32port = &stm32_ports[co->index]; 1191 1192 /* 1193 * This driver does not support early console initialization 1194 * (use ARM early printk support instead), so we only expect 1195 * this to be called during the uart port registration when the 1196 * driver gets probed and the port should be mapped at that point. 1197 */ 1198 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) 1199 return -ENXIO; 1200 1201 if (options) 1202 uart_parse_options(options, &baud, &parity, &bits, &flow); 1203 1204 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1205 } 1206 1207 static struct console stm32_console = { 1208 .name = STM32_SERIAL_NAME, 1209 .device = uart_console_device, 1210 .write = stm32_console_write, 1211 .setup = stm32_console_setup, 1212 .flags = CON_PRINTBUFFER, 1213 .index = -1, 1214 .data = &stm32_usart_driver, 1215 }; 1216 1217 #define STM32_SERIAL_CONSOLE (&stm32_console) 1218 1219 #else 1220 #define STM32_SERIAL_CONSOLE NULL 1221 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1222 1223 static struct uart_driver stm32_usart_driver = { 1224 .driver_name = DRIVER_NAME, 1225 .dev_name = STM32_SERIAL_NAME, 1226 .major = 0, 1227 .minor = 0, 1228 .nr = STM32_MAX_PORTS, 1229 .cons = STM32_SERIAL_CONSOLE, 1230 }; 1231 1232 #ifdef CONFIG_PM_SLEEP 1233 static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable) 1234 { 1235 struct stm32_port *stm32_port = to_stm32_port(port); 1236 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1237 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1238 u32 val; 1239 1240 if (!cfg->has_wakeup || stm32_port->wakeirq < 0) 1241 return; 1242 1243 if (enable) { 1244 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1245 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM); 1246 val = readl_relaxed(port->membase + ofs->cr3); 1247 val &= ~USART_CR3_WUS_MASK; 1248 /* Enable Wake up interrupt from low power on start bit */ 1249 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; 1250 writel_relaxed(val, port->membase + ofs->cr3); 1251 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1252 } else { 1253 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1254 } 1255 } 1256 1257 static int stm32_serial_suspend(struct device *dev) 1258 { 1259 struct uart_port *port = dev_get_drvdata(dev); 1260 1261 uart_suspend_port(&stm32_usart_driver, port); 1262 1263 if (device_may_wakeup(dev)) 1264 stm32_serial_enable_wakeup(port, true); 1265 else 1266 stm32_serial_enable_wakeup(port, false); 1267 1268 return 0; 1269 } 1270 1271 static int stm32_serial_resume(struct device *dev) 1272 { 1273 struct uart_port *port = dev_get_drvdata(dev); 1274 1275 if (device_may_wakeup(dev)) 1276 stm32_serial_enable_wakeup(port, false); 1277 1278 return uart_resume_port(&stm32_usart_driver, port); 1279 } 1280 #endif /* CONFIG_PM_SLEEP */ 1281 1282 static const struct dev_pm_ops stm32_serial_pm_ops = { 1283 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume) 1284 }; 1285 1286 static struct platform_driver stm32_serial_driver = { 1287 .probe = stm32_serial_probe, 1288 .remove = stm32_serial_remove, 1289 .driver = { 1290 .name = DRIVER_NAME, 1291 .pm = &stm32_serial_pm_ops, 1292 .of_match_table = of_match_ptr(stm32_match), 1293 }, 1294 }; 1295 1296 static int __init usart_init(void) 1297 { 1298 static char banner[] __initdata = "STM32 USART driver initialized"; 1299 int ret; 1300 1301 pr_info("%s\n", banner); 1302 1303 ret = uart_register_driver(&stm32_usart_driver); 1304 if (ret) 1305 return ret; 1306 1307 ret = platform_driver_register(&stm32_serial_driver); 1308 if (ret) 1309 uart_unregister_driver(&stm32_usart_driver); 1310 1311 return ret; 1312 } 1313 1314 static void __exit usart_exit(void) 1315 { 1316 platform_driver_unregister(&stm32_serial_driver); 1317 uart_unregister_driver(&stm32_usart_driver); 1318 } 1319 1320 module_init(usart_init); 1321 module_exit(usart_exit); 1322 1323 MODULE_ALIAS("platform:" DRIVER_NAME); 1324 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1325 MODULE_LICENSE("GPL v2"); 1326