1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@foss.st.com> 7 * Erwan Le Ray <erwan.leray@foss.st.com> 8 * 9 * Inspired by st-asc.c from STMicroelectronics (c) 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/delay.h> 15 #include <linux/dma-direction.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "serial_mctrl_gpio.h" 36 #include "stm32-usart.h" 37 38 static void stm32_usart_stop_tx(struct uart_port *port); 39 static void stm32_usart_transmit_chars(struct uart_port *port); 40 41 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 42 { 43 return container_of(port, struct stm32_port, port); 44 } 45 46 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 47 { 48 u32 val; 49 50 val = readl_relaxed(port->membase + reg); 51 val |= bits; 52 writel_relaxed(val, port->membase + reg); 53 } 54 55 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 56 { 57 u32 val; 58 59 val = readl_relaxed(port->membase + reg); 60 val &= ~bits; 61 writel_relaxed(val, port->membase + reg); 62 } 63 64 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 65 u32 delay_DDE, u32 baud) 66 { 67 u32 rs485_deat_dedt; 68 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 69 bool over8; 70 71 *cr3 |= USART_CR3_DEM; 72 over8 = *cr1 & USART_CR1_OVER8; 73 74 if (over8) 75 rs485_deat_dedt = delay_ADE * baud * 8; 76 else 77 rs485_deat_dedt = delay_ADE * baud * 16; 78 79 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 80 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 81 rs485_deat_dedt_max : rs485_deat_dedt; 82 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 83 USART_CR1_DEAT_MASK; 84 *cr1 |= rs485_deat_dedt; 85 86 if (over8) 87 rs485_deat_dedt = delay_DDE * baud * 8; 88 else 89 rs485_deat_dedt = delay_DDE * baud * 16; 90 91 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 92 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 93 rs485_deat_dedt_max : rs485_deat_dedt; 94 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 95 USART_CR1_DEDT_MASK; 96 *cr1 |= rs485_deat_dedt; 97 } 98 99 static int stm32_usart_config_rs485(struct uart_port *port, 100 struct serial_rs485 *rs485conf) 101 { 102 struct stm32_port *stm32_port = to_stm32_port(port); 103 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 104 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 105 u32 usartdiv, baud, cr1, cr3; 106 bool over8; 107 108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 109 110 port->rs485 = *rs485conf; 111 112 rs485conf->flags |= SER_RS485_RX_DURING_TX; 113 114 if (rs485conf->flags & SER_RS485_ENABLED) { 115 cr1 = readl_relaxed(port->membase + ofs->cr1); 116 cr3 = readl_relaxed(port->membase + ofs->cr3); 117 usartdiv = readl_relaxed(port->membase + ofs->brr); 118 usartdiv = usartdiv & GENMASK(15, 0); 119 over8 = cr1 & USART_CR1_OVER8; 120 121 if (over8) 122 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 123 << USART_BRR_04_R_SHIFT; 124 125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 126 stm32_usart_config_reg_rs485(&cr1, &cr3, 127 rs485conf->delay_rts_before_send, 128 rs485conf->delay_rts_after_send, 129 baud); 130 131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 132 cr3 &= ~USART_CR3_DEP; 133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 134 } else { 135 cr3 |= USART_CR3_DEP; 136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 137 } 138 139 writel_relaxed(cr3, port->membase + ofs->cr3); 140 writel_relaxed(cr1, port->membase + ofs->cr1); 141 } else { 142 stm32_usart_clr_bits(port, ofs->cr3, 143 USART_CR3_DEM | USART_CR3_DEP); 144 stm32_usart_clr_bits(port, ofs->cr1, 145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 146 } 147 148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 149 150 return 0; 151 } 152 153 static int stm32_usart_init_rs485(struct uart_port *port, 154 struct platform_device *pdev) 155 { 156 struct serial_rs485 *rs485conf = &port->rs485; 157 158 rs485conf->flags = 0; 159 rs485conf->delay_rts_before_send = 0; 160 rs485conf->delay_rts_after_send = 0; 161 162 if (!pdev->dev.of_node) 163 return -ENODEV; 164 165 return uart_get_rs485_mode(port); 166 } 167 168 static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr, 169 int *last_res, bool threaded) 170 { 171 struct stm32_port *stm32_port = to_stm32_port(port); 172 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 173 enum dma_status status; 174 struct dma_tx_state state; 175 176 *sr = readl_relaxed(port->membase + ofs->isr); 177 178 if (threaded && stm32_port->rx_ch) { 179 status = dmaengine_tx_status(stm32_port->rx_ch, 180 stm32_port->rx_ch->cookie, 181 &state); 182 if (status == DMA_IN_PROGRESS && (*last_res != state.residue)) 183 return 1; 184 else 185 return 0; 186 } else if (*sr & USART_SR_RXNE) { 187 return 1; 188 } 189 return 0; 190 } 191 192 static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr, 193 int *last_res) 194 { 195 struct stm32_port *stm32_port = to_stm32_port(port); 196 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 197 unsigned long c; 198 199 if (stm32_port->rx_ch) { 200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 201 if ((*last_res) == 0) 202 *last_res = RX_BUF_L; 203 } else { 204 c = readl_relaxed(port->membase + ofs->rdr); 205 /* apply RDR data mask */ 206 c &= stm32_port->rdr_mask; 207 } 208 209 return c; 210 } 211 212 static void stm32_usart_receive_chars(struct uart_port *port, bool threaded) 213 { 214 struct tty_port *tport = &port->state->port; 215 struct stm32_port *stm32_port = to_stm32_port(port); 216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 217 unsigned long c, flags; 218 u32 sr; 219 char flag; 220 221 if (threaded) 222 spin_lock_irqsave(&port->lock, flags); 223 else 224 spin_lock(&port->lock); 225 226 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, 227 threaded)) { 228 sr |= USART_SR_DUMMY_RX; 229 flag = TTY_NORMAL; 230 231 /* 232 * Status bits has to be cleared before reading the RDR: 233 * In FIFO mode, reading the RDR will pop the next data 234 * (if any) along with its status bits into the SR. 235 * Not doing so leads to misalignement between RDR and SR, 236 * and clear status bits of the next rx data. 237 * 238 * Clear errors flags for stm32f7 and stm32h7 compatible 239 * devices. On stm32f4 compatible devices, the error bit is 240 * cleared by the sequence [read SR - read DR]. 241 */ 242 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 243 writel_relaxed(sr & USART_SR_ERR_MASK, 244 port->membase + ofs->icr); 245 246 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); 247 port->icount.rx++; 248 if (sr & USART_SR_ERR_MASK) { 249 if (sr & USART_SR_ORE) { 250 port->icount.overrun++; 251 } else if (sr & USART_SR_PE) { 252 port->icount.parity++; 253 } else if (sr & USART_SR_FE) { 254 /* Break detection if character is null */ 255 if (!c) { 256 port->icount.brk++; 257 if (uart_handle_break(port)) 258 continue; 259 } else { 260 port->icount.frame++; 261 } 262 } 263 264 sr &= port->read_status_mask; 265 266 if (sr & USART_SR_PE) { 267 flag = TTY_PARITY; 268 } else if (sr & USART_SR_FE) { 269 if (!c) 270 flag = TTY_BREAK; 271 else 272 flag = TTY_FRAME; 273 } 274 } 275 276 if (uart_handle_sysrq_char(port, c)) 277 continue; 278 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 279 } 280 281 if (threaded) 282 spin_unlock_irqrestore(&port->lock, flags); 283 else 284 spin_unlock(&port->lock); 285 286 tty_flip_buffer_push(tport); 287 } 288 289 static void stm32_usart_tx_dma_complete(void *arg) 290 { 291 struct uart_port *port = arg; 292 struct stm32_port *stm32port = to_stm32_port(port); 293 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 294 unsigned long flags; 295 296 dmaengine_terminate_async(stm32port->tx_ch); 297 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 298 stm32port->tx_dma_busy = false; 299 300 /* Let's see if we have pending data to send */ 301 spin_lock_irqsave(&port->lock, flags); 302 stm32_usart_transmit_chars(port); 303 spin_unlock_irqrestore(&port->lock, flags); 304 } 305 306 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 307 { 308 struct stm32_port *stm32_port = to_stm32_port(port); 309 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 310 311 /* 312 * Enables TX FIFO threashold irq when FIFO is enabled, 313 * or TX empty irq when FIFO is disabled 314 */ 315 if (stm32_port->fifoen) 316 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 317 else 318 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 319 } 320 321 static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 322 { 323 struct stm32_port *stm32_port = to_stm32_port(port); 324 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 325 326 if (stm32_port->fifoen) 327 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 328 else 329 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 330 } 331 332 static void stm32_usart_transmit_chars_pio(struct uart_port *port) 333 { 334 struct stm32_port *stm32_port = to_stm32_port(port); 335 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 336 struct circ_buf *xmit = &port->state->xmit; 337 338 if (stm32_port->tx_dma_busy) { 339 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 340 stm32_port->tx_dma_busy = false; 341 } 342 343 while (!uart_circ_empty(xmit)) { 344 /* Check that TDR is empty before filling FIFO */ 345 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 346 break; 347 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 348 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 349 port->icount.tx++; 350 } 351 352 /* rely on TXE irq (mask or unmask) for sending remaining data */ 353 if (uart_circ_empty(xmit)) 354 stm32_usart_tx_interrupt_disable(port); 355 else 356 stm32_usart_tx_interrupt_enable(port); 357 } 358 359 static void stm32_usart_transmit_chars_dma(struct uart_port *port) 360 { 361 struct stm32_port *stm32port = to_stm32_port(port); 362 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 363 struct circ_buf *xmit = &port->state->xmit; 364 struct dma_async_tx_descriptor *desc = NULL; 365 unsigned int count, i; 366 367 if (stm32port->tx_dma_busy) 368 return; 369 370 stm32port->tx_dma_busy = true; 371 372 count = uart_circ_chars_pending(xmit); 373 374 if (count > TX_BUF_L) 375 count = TX_BUF_L; 376 377 if (xmit->tail < xmit->head) { 378 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 379 } else { 380 size_t one = UART_XMIT_SIZE - xmit->tail; 381 size_t two; 382 383 if (one > count) 384 one = count; 385 two = count - one; 386 387 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 388 if (two) 389 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 390 } 391 392 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 393 stm32port->tx_dma_buf, 394 count, 395 DMA_MEM_TO_DEV, 396 DMA_PREP_INTERRUPT); 397 398 if (!desc) 399 goto fallback_err; 400 401 desc->callback = stm32_usart_tx_dma_complete; 402 desc->callback_param = port; 403 404 /* Push current DMA TX transaction in the pending queue */ 405 if (dma_submit_error(dmaengine_submit(desc))) { 406 /* dma no yet started, safe to free resources */ 407 dmaengine_terminate_async(stm32port->tx_ch); 408 goto fallback_err; 409 } 410 411 /* Issue pending DMA TX requests */ 412 dma_async_issue_pending(stm32port->tx_ch); 413 414 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 415 416 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 417 port->icount.tx += count; 418 return; 419 420 fallback_err: 421 for (i = count; i > 0; i--) 422 stm32_usart_transmit_chars_pio(port); 423 } 424 425 static void stm32_usart_transmit_chars(struct uart_port *port) 426 { 427 struct stm32_port *stm32_port = to_stm32_port(port); 428 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 429 struct circ_buf *xmit = &port->state->xmit; 430 431 if (port->x_char) { 432 if (stm32_port->tx_dma_busy) 433 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 434 writel_relaxed(port->x_char, port->membase + ofs->tdr); 435 port->x_char = 0; 436 port->icount.tx++; 437 if (stm32_port->tx_dma_busy) 438 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 439 return; 440 } 441 442 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 443 stm32_usart_tx_interrupt_disable(port); 444 return; 445 } 446 447 if (ofs->icr == UNDEF_REG) 448 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 449 else 450 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 451 452 if (stm32_port->tx_ch) 453 stm32_usart_transmit_chars_dma(port); 454 else 455 stm32_usart_transmit_chars_pio(port); 456 457 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 458 uart_write_wakeup(port); 459 460 if (uart_circ_empty(xmit)) 461 stm32_usart_tx_interrupt_disable(port); 462 } 463 464 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 465 { 466 struct uart_port *port = ptr; 467 struct tty_port *tport = &port->state->port; 468 struct stm32_port *stm32_port = to_stm32_port(port); 469 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 470 u32 sr; 471 472 sr = readl_relaxed(port->membase + ofs->isr); 473 474 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 475 writel_relaxed(USART_ICR_RTOCF, 476 port->membase + ofs->icr); 477 478 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { 479 /* Clear wake up flag and disable wake up interrupt */ 480 writel_relaxed(USART_ICR_WUCF, 481 port->membase + ofs->icr); 482 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 483 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 484 pm_wakeup_event(tport->tty->dev, 0); 485 } 486 487 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 488 stm32_usart_receive_chars(port, false); 489 490 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { 491 spin_lock(&port->lock); 492 stm32_usart_transmit_chars(port); 493 spin_unlock(&port->lock); 494 } 495 496 if (stm32_port->rx_ch) 497 return IRQ_WAKE_THREAD; 498 else 499 return IRQ_HANDLED; 500 } 501 502 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr) 503 { 504 struct uart_port *port = ptr; 505 struct stm32_port *stm32_port = to_stm32_port(port); 506 507 if (stm32_port->rx_ch) 508 stm32_usart_receive_chars(port, true); 509 510 return IRQ_HANDLED; 511 } 512 513 static unsigned int stm32_usart_tx_empty(struct uart_port *port) 514 { 515 struct stm32_port *stm32_port = to_stm32_port(port); 516 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 517 518 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 519 } 520 521 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 522 { 523 struct stm32_port *stm32_port = to_stm32_port(port); 524 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 525 526 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 527 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 528 else 529 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 530 531 mctrl_gpio_set(stm32_port->gpios, mctrl); 532 } 533 534 static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 535 { 536 struct stm32_port *stm32_port = to_stm32_port(port); 537 unsigned int ret; 538 539 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 540 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 541 542 return mctrl_gpio_get(stm32_port->gpios, &ret); 543 } 544 545 static void stm32_usart_enable_ms(struct uart_port *port) 546 { 547 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 548 } 549 550 static void stm32_usart_disable_ms(struct uart_port *port) 551 { 552 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 553 } 554 555 /* Transmit stop */ 556 static void stm32_usart_stop_tx(struct uart_port *port) 557 { 558 struct stm32_port *stm32_port = to_stm32_port(port); 559 struct serial_rs485 *rs485conf = &port->rs485; 560 561 stm32_usart_tx_interrupt_disable(port); 562 563 if (rs485conf->flags & SER_RS485_ENABLED) { 564 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 565 mctrl_gpio_set(stm32_port->gpios, 566 stm32_port->port.mctrl & ~TIOCM_RTS); 567 } else { 568 mctrl_gpio_set(stm32_port->gpios, 569 stm32_port->port.mctrl | TIOCM_RTS); 570 } 571 } 572 } 573 574 /* There are probably characters waiting to be transmitted. */ 575 static void stm32_usart_start_tx(struct uart_port *port) 576 { 577 struct stm32_port *stm32_port = to_stm32_port(port); 578 struct serial_rs485 *rs485conf = &port->rs485; 579 struct circ_buf *xmit = &port->state->xmit; 580 581 if (uart_circ_empty(xmit)) 582 return; 583 584 if (rs485conf->flags & SER_RS485_ENABLED) { 585 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 586 mctrl_gpio_set(stm32_port->gpios, 587 stm32_port->port.mctrl | TIOCM_RTS); 588 } else { 589 mctrl_gpio_set(stm32_port->gpios, 590 stm32_port->port.mctrl & ~TIOCM_RTS); 591 } 592 } 593 594 stm32_usart_transmit_chars(port); 595 } 596 597 /* Throttle the remote when input buffer is about to overflow. */ 598 static void stm32_usart_throttle(struct uart_port *port) 599 { 600 struct stm32_port *stm32_port = to_stm32_port(port); 601 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 602 unsigned long flags; 603 604 spin_lock_irqsave(&port->lock, flags); 605 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 606 if (stm32_port->cr3_irq) 607 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 608 609 spin_unlock_irqrestore(&port->lock, flags); 610 } 611 612 /* Unthrottle the remote, the input buffer can now accept data. */ 613 static void stm32_usart_unthrottle(struct uart_port *port) 614 { 615 struct stm32_port *stm32_port = to_stm32_port(port); 616 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 617 unsigned long flags; 618 619 spin_lock_irqsave(&port->lock, flags); 620 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 621 if (stm32_port->cr3_irq) 622 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 623 624 spin_unlock_irqrestore(&port->lock, flags); 625 } 626 627 /* Receive stop */ 628 static void stm32_usart_stop_rx(struct uart_port *port) 629 { 630 struct stm32_port *stm32_port = to_stm32_port(port); 631 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 632 633 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 634 if (stm32_port->cr3_irq) 635 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 636 } 637 638 /* Handle breaks - ignored by us */ 639 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 640 { 641 } 642 643 static int stm32_usart_startup(struct uart_port *port) 644 { 645 struct stm32_port *stm32_port = to_stm32_port(port); 646 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 647 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 648 const char *name = to_platform_device(port->dev)->name; 649 u32 val; 650 int ret; 651 652 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, 653 stm32_usart_threaded_interrupt, 654 IRQF_NO_SUSPEND, name, port); 655 if (ret) 656 return ret; 657 658 /* RX FIFO Flush */ 659 if (ofs->rqr != UNDEF_REG) 660 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); 661 662 /* RX enabling */ 663 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 664 stm32_usart_set_bits(port, ofs->cr1, val); 665 666 return 0; 667 } 668 669 static void stm32_usart_shutdown(struct uart_port *port) 670 { 671 struct stm32_port *stm32_port = to_stm32_port(port); 672 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 673 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 674 u32 val, isr; 675 int ret; 676 677 /* Disable modem control interrupts */ 678 stm32_usart_disable_ms(port); 679 680 val = USART_CR1_TXEIE | USART_CR1_TE; 681 val |= stm32_port->cr1_irq | USART_CR1_RE; 682 val |= BIT(cfg->uart_enable_bit); 683 if (stm32_port->fifoen) 684 val |= USART_CR1_FIFOEN; 685 686 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 687 isr, (isr & USART_SR_TC), 688 10, 100000); 689 690 /* Send the TC error message only when ISR_TC is not set */ 691 if (ret) 692 dev_err(port->dev, "Transmission is not complete\n"); 693 694 /* flush RX & TX FIFO */ 695 if (ofs->rqr != UNDEF_REG) 696 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 697 port->membase + ofs->rqr); 698 699 stm32_usart_clr_bits(port, ofs->cr1, val); 700 701 free_irq(port->irq, port); 702 } 703 704 static unsigned int stm32_usart_get_databits(struct ktermios *termios) 705 { 706 unsigned int bits; 707 708 tcflag_t cflag = termios->c_cflag; 709 710 switch (cflag & CSIZE) { 711 /* 712 * CSIZE settings are not necessarily supported in hardware. 713 * CSIZE unsupported configurations are handled here to set word length 714 * to 8 bits word as default configuration and to print debug message. 715 */ 716 case CS5: 717 bits = 5; 718 break; 719 case CS6: 720 bits = 6; 721 break; 722 case CS7: 723 bits = 7; 724 break; 725 /* default including CS8 */ 726 default: 727 bits = 8; 728 break; 729 } 730 731 return bits; 732 } 733 734 static void stm32_usart_set_termios(struct uart_port *port, 735 struct ktermios *termios, 736 struct ktermios *old) 737 { 738 struct stm32_port *stm32_port = to_stm32_port(port); 739 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 740 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 741 struct serial_rs485 *rs485conf = &port->rs485; 742 unsigned int baud, bits; 743 u32 usartdiv, mantissa, fraction, oversampling; 744 tcflag_t cflag = termios->c_cflag; 745 u32 cr1, cr2, cr3, isr; 746 unsigned long flags; 747 int ret; 748 749 if (!stm32_port->hw_flow_control) 750 cflag &= ~CRTSCTS; 751 752 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 753 754 spin_lock_irqsave(&port->lock, flags); 755 756 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 757 isr, 758 (isr & USART_SR_TC), 759 10, 100000); 760 761 /* Send the TC error message only when ISR_TC is not set. */ 762 if (ret) 763 dev_err(port->dev, "Transmission is not complete\n"); 764 765 /* Stop serial port and reset value */ 766 writel_relaxed(0, port->membase + ofs->cr1); 767 768 /* flush RX & TX FIFO */ 769 if (ofs->rqr != UNDEF_REG) 770 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 771 port->membase + ofs->rqr); 772 773 cr1 = USART_CR1_TE | USART_CR1_RE; 774 if (stm32_port->fifoen) 775 cr1 |= USART_CR1_FIFOEN; 776 cr2 = 0; 777 778 /* Tx and RX FIFO configuration */ 779 cr3 = readl_relaxed(port->membase + ofs->cr3); 780 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE; 781 if (stm32_port->fifoen) { 782 cr3 &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 783 cr3 |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 784 cr3 |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 785 } 786 787 if (cflag & CSTOPB) 788 cr2 |= USART_CR2_STOP_2B; 789 790 bits = stm32_usart_get_databits(termios); 791 stm32_port->rdr_mask = (BIT(bits) - 1); 792 793 if (cflag & PARENB) { 794 bits++; 795 cr1 |= USART_CR1_PCE; 796 } 797 798 /* 799 * Word length configuration: 800 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 801 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 802 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 803 * M0 and M1 already cleared by cr1 initialization. 804 */ 805 if (bits == 9) 806 cr1 |= USART_CR1_M0; 807 else if ((bits == 7) && cfg->has_7bits_data) 808 cr1 |= USART_CR1_M1; 809 else if (bits != 8) 810 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 811 , bits); 812 813 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 814 stm32_port->fifoen)) { 815 if (cflag & CSTOPB) 816 bits = bits + 3; /* 1 start bit + 2 stop bits */ 817 else 818 bits = bits + 2; /* 1 start bit + 1 stop bit */ 819 820 /* RX timeout irq to occur after last stop bit + bits */ 821 stm32_port->cr1_irq = USART_CR1_RTOIE; 822 writel_relaxed(bits, port->membase + ofs->rtor); 823 cr2 |= USART_CR2_RTOEN; 824 /* Not using dma, enable fifo threshold irq */ 825 if (!stm32_port->rx_ch) 826 stm32_port->cr3_irq = USART_CR3_RXFTIE; 827 } 828 829 cr1 |= stm32_port->cr1_irq; 830 cr3 |= stm32_port->cr3_irq; 831 832 if (cflag & PARODD) 833 cr1 |= USART_CR1_PS; 834 835 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 836 if (cflag & CRTSCTS) { 837 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 838 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 839 } 840 841 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 842 843 /* 844 * The USART supports 16 or 8 times oversampling. 845 * By default we prefer 16 times oversampling, so that the receiver 846 * has a better tolerance to clock deviations. 847 * 8 times oversampling is only used to achieve higher speeds. 848 */ 849 if (usartdiv < 16) { 850 oversampling = 8; 851 cr1 |= USART_CR1_OVER8; 852 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 853 } else { 854 oversampling = 16; 855 cr1 &= ~USART_CR1_OVER8; 856 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 857 } 858 859 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 860 fraction = usartdiv % oversampling; 861 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 862 863 uart_update_timeout(port, cflag, baud); 864 865 port->read_status_mask = USART_SR_ORE; 866 if (termios->c_iflag & INPCK) 867 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 868 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 869 port->read_status_mask |= USART_SR_FE; 870 871 /* Characters to ignore */ 872 port->ignore_status_mask = 0; 873 if (termios->c_iflag & IGNPAR) 874 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 875 if (termios->c_iflag & IGNBRK) { 876 port->ignore_status_mask |= USART_SR_FE; 877 /* 878 * If we're ignoring parity and break indicators, 879 * ignore overruns too (for real raw support). 880 */ 881 if (termios->c_iflag & IGNPAR) 882 port->ignore_status_mask |= USART_SR_ORE; 883 } 884 885 /* Ignore all characters if CREAD is not set */ 886 if ((termios->c_cflag & CREAD) == 0) 887 port->ignore_status_mask |= USART_SR_DUMMY_RX; 888 889 if (stm32_port->rx_ch) 890 cr3 |= USART_CR3_DMAR; 891 892 if (rs485conf->flags & SER_RS485_ENABLED) { 893 stm32_usart_config_reg_rs485(&cr1, &cr3, 894 rs485conf->delay_rts_before_send, 895 rs485conf->delay_rts_after_send, 896 baud); 897 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 898 cr3 &= ~USART_CR3_DEP; 899 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 900 } else { 901 cr3 |= USART_CR3_DEP; 902 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 903 } 904 905 } else { 906 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 907 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 908 } 909 910 /* Configure wake up from low power on start bit detection */ 911 if (stm32_port->wakeirq > 0) { 912 cr3 &= ~USART_CR3_WUS_MASK; 913 cr3 |= USART_CR3_WUS_START_BIT; 914 } 915 916 writel_relaxed(cr3, port->membase + ofs->cr3); 917 writel_relaxed(cr2, port->membase + ofs->cr2); 918 writel_relaxed(cr1, port->membase + ofs->cr1); 919 920 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 921 spin_unlock_irqrestore(&port->lock, flags); 922 923 /* Handle modem control interrupts */ 924 if (UART_ENABLE_MS(port, termios->c_cflag)) 925 stm32_usart_enable_ms(port); 926 else 927 stm32_usart_disable_ms(port); 928 } 929 930 static const char *stm32_usart_type(struct uart_port *port) 931 { 932 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 933 } 934 935 static void stm32_usart_release_port(struct uart_port *port) 936 { 937 } 938 939 static int stm32_usart_request_port(struct uart_port *port) 940 { 941 return 0; 942 } 943 944 static void stm32_usart_config_port(struct uart_port *port, int flags) 945 { 946 if (flags & UART_CONFIG_TYPE) 947 port->type = PORT_STM32; 948 } 949 950 static int 951 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 952 { 953 /* No user changeable parameters */ 954 return -EINVAL; 955 } 956 957 static void stm32_usart_pm(struct uart_port *port, unsigned int state, 958 unsigned int oldstate) 959 { 960 struct stm32_port *stm32port = container_of(port, 961 struct stm32_port, port); 962 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 963 const struct stm32_usart_config *cfg = &stm32port->info->cfg; 964 unsigned long flags = 0; 965 966 switch (state) { 967 case UART_PM_STATE_ON: 968 pm_runtime_get_sync(port->dev); 969 break; 970 case UART_PM_STATE_OFF: 971 spin_lock_irqsave(&port->lock, flags); 972 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 973 spin_unlock_irqrestore(&port->lock, flags); 974 pm_runtime_put_sync(port->dev); 975 break; 976 } 977 } 978 979 static const struct uart_ops stm32_uart_ops = { 980 .tx_empty = stm32_usart_tx_empty, 981 .set_mctrl = stm32_usart_set_mctrl, 982 .get_mctrl = stm32_usart_get_mctrl, 983 .stop_tx = stm32_usart_stop_tx, 984 .start_tx = stm32_usart_start_tx, 985 .throttle = stm32_usart_throttle, 986 .unthrottle = stm32_usart_unthrottle, 987 .stop_rx = stm32_usart_stop_rx, 988 .enable_ms = stm32_usart_enable_ms, 989 .break_ctl = stm32_usart_break_ctl, 990 .startup = stm32_usart_startup, 991 .shutdown = stm32_usart_shutdown, 992 .set_termios = stm32_usart_set_termios, 993 .pm = stm32_usart_pm, 994 .type = stm32_usart_type, 995 .release_port = stm32_usart_release_port, 996 .request_port = stm32_usart_request_port, 997 .config_port = stm32_usart_config_port, 998 .verify_port = stm32_usart_verify_port, 999 }; 1000 1001 static void stm32_usart_deinit_port(struct stm32_port *stm32port) 1002 { 1003 clk_disable_unprepare(stm32port->clk); 1004 } 1005 1006 static int stm32_usart_init_port(struct stm32_port *stm32port, 1007 struct platform_device *pdev) 1008 { 1009 struct uart_port *port = &stm32port->port; 1010 struct resource *res; 1011 int ret, irq; 1012 1013 irq = platform_get_irq(pdev, 0); 1014 if (irq <= 0) 1015 return irq ? : -ENODEV; 1016 1017 port->iotype = UPIO_MEM; 1018 port->flags = UPF_BOOT_AUTOCONF; 1019 port->ops = &stm32_uart_ops; 1020 port->dev = &pdev->dev; 1021 port->fifosize = stm32port->info->cfg.fifosize; 1022 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 1023 port->irq = irq; 1024 port->rs485_config = stm32_usart_config_rs485; 1025 1026 ret = stm32_usart_init_rs485(port, pdev); 1027 if (ret) 1028 return ret; 1029 1030 if (stm32port->info->cfg.has_wakeup) { 1031 stm32port->wakeirq = platform_get_irq_optional(pdev, 1); 1032 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) 1033 return stm32port->wakeirq ? : -ENODEV; 1034 } 1035 1036 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1037 1038 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1039 port->membase = devm_ioremap_resource(&pdev->dev, res); 1040 if (IS_ERR(port->membase)) 1041 return PTR_ERR(port->membase); 1042 port->mapbase = res->start; 1043 1044 spin_lock_init(&port->lock); 1045 1046 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1047 if (IS_ERR(stm32port->clk)) 1048 return PTR_ERR(stm32port->clk); 1049 1050 /* Ensure that clk rate is correct by enabling the clk */ 1051 ret = clk_prepare_enable(stm32port->clk); 1052 if (ret) 1053 return ret; 1054 1055 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1056 if (!stm32port->port.uartclk) { 1057 ret = -EINVAL; 1058 goto err_clk; 1059 } 1060 1061 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1062 if (IS_ERR(stm32port->gpios)) { 1063 ret = PTR_ERR(stm32port->gpios); 1064 goto err_clk; 1065 } 1066 1067 /* 1068 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" 1069 * properties should not be specified. 1070 */ 1071 if (stm32port->hw_flow_control) { 1072 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1073 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1074 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1075 ret = -EINVAL; 1076 goto err_clk; 1077 } 1078 } 1079 1080 return ret; 1081 1082 err_clk: 1083 clk_disable_unprepare(stm32port->clk); 1084 1085 return ret; 1086 } 1087 1088 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1089 { 1090 struct device_node *np = pdev->dev.of_node; 1091 int id; 1092 1093 if (!np) 1094 return NULL; 1095 1096 id = of_alias_get_id(np, "serial"); 1097 if (id < 0) { 1098 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1099 return NULL; 1100 } 1101 1102 if (WARN_ON(id >= STM32_MAX_PORTS)) 1103 return NULL; 1104 1105 stm32_ports[id].hw_flow_control = 1106 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1107 of_property_read_bool (np, "uart-has-rtscts"); 1108 stm32_ports[id].port.line = id; 1109 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1110 stm32_ports[id].cr3_irq = 0; 1111 stm32_ports[id].last_res = RX_BUF_L; 1112 return &stm32_ports[id]; 1113 } 1114 1115 #ifdef CONFIG_OF 1116 static const struct of_device_id stm32_match[] = { 1117 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1118 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1119 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1120 {}, 1121 }; 1122 1123 MODULE_DEVICE_TABLE(of, stm32_match); 1124 #endif 1125 1126 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1127 struct platform_device *pdev) 1128 { 1129 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1130 struct uart_port *port = &stm32port->port; 1131 struct device *dev = &pdev->dev; 1132 struct dma_slave_config config; 1133 struct dma_async_tx_descriptor *desc = NULL; 1134 int ret; 1135 1136 /* Request DMA RX channel */ 1137 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1138 if (!stm32port->rx_ch) { 1139 dev_info(dev, "rx dma alloc failed\n"); 1140 return -ENODEV; 1141 } 1142 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1143 &stm32port->rx_dma_buf, 1144 GFP_KERNEL); 1145 if (!stm32port->rx_buf) { 1146 ret = -ENOMEM; 1147 goto alloc_err; 1148 } 1149 1150 /* Configure DMA channel */ 1151 memset(&config, 0, sizeof(config)); 1152 config.src_addr = port->mapbase + ofs->rdr; 1153 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1154 1155 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1156 if (ret < 0) { 1157 dev_err(dev, "rx dma channel config failed\n"); 1158 ret = -ENODEV; 1159 goto config_err; 1160 } 1161 1162 /* Prepare a DMA cyclic transaction */ 1163 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1164 stm32port->rx_dma_buf, 1165 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1166 DMA_PREP_INTERRUPT); 1167 if (!desc) { 1168 dev_err(dev, "rx dma prep cyclic failed\n"); 1169 ret = -ENODEV; 1170 goto config_err; 1171 } 1172 1173 /* No callback as dma buffer is drained on usart interrupt */ 1174 desc->callback = NULL; 1175 desc->callback_param = NULL; 1176 1177 /* Push current DMA transaction in the pending queue */ 1178 ret = dma_submit_error(dmaengine_submit(desc)); 1179 if (ret) { 1180 dmaengine_terminate_sync(stm32port->rx_ch); 1181 goto config_err; 1182 } 1183 1184 /* Issue pending DMA requests */ 1185 dma_async_issue_pending(stm32port->rx_ch); 1186 1187 return 0; 1188 1189 config_err: 1190 dma_free_coherent(&pdev->dev, 1191 RX_BUF_L, stm32port->rx_buf, 1192 stm32port->rx_dma_buf); 1193 1194 alloc_err: 1195 dma_release_channel(stm32port->rx_ch); 1196 stm32port->rx_ch = NULL; 1197 1198 return ret; 1199 } 1200 1201 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1202 struct platform_device *pdev) 1203 { 1204 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1205 struct uart_port *port = &stm32port->port; 1206 struct device *dev = &pdev->dev; 1207 struct dma_slave_config config; 1208 int ret; 1209 1210 stm32port->tx_dma_busy = false; 1211 1212 /* Request DMA TX channel */ 1213 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1214 if (!stm32port->tx_ch) { 1215 dev_info(dev, "tx dma alloc failed\n"); 1216 return -ENODEV; 1217 } 1218 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1219 &stm32port->tx_dma_buf, 1220 GFP_KERNEL); 1221 if (!stm32port->tx_buf) { 1222 ret = -ENOMEM; 1223 goto alloc_err; 1224 } 1225 1226 /* Configure DMA channel */ 1227 memset(&config, 0, sizeof(config)); 1228 config.dst_addr = port->mapbase + ofs->tdr; 1229 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1230 1231 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1232 if (ret < 0) { 1233 dev_err(dev, "tx dma channel config failed\n"); 1234 ret = -ENODEV; 1235 goto config_err; 1236 } 1237 1238 return 0; 1239 1240 config_err: 1241 dma_free_coherent(&pdev->dev, 1242 TX_BUF_L, stm32port->tx_buf, 1243 stm32port->tx_dma_buf); 1244 1245 alloc_err: 1246 dma_release_channel(stm32port->tx_ch); 1247 stm32port->tx_ch = NULL; 1248 1249 return ret; 1250 } 1251 1252 static int stm32_usart_serial_probe(struct platform_device *pdev) 1253 { 1254 struct stm32_port *stm32port; 1255 int ret; 1256 1257 stm32port = stm32_usart_of_get_port(pdev); 1258 if (!stm32port) 1259 return -ENODEV; 1260 1261 stm32port->info = of_device_get_match_data(&pdev->dev); 1262 if (!stm32port->info) 1263 return -EINVAL; 1264 1265 ret = stm32_usart_init_port(stm32port, pdev); 1266 if (ret) 1267 return ret; 1268 1269 if (stm32port->wakeirq > 0) { 1270 ret = device_init_wakeup(&pdev->dev, true); 1271 if (ret) 1272 goto err_uninit; 1273 1274 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1275 stm32port->wakeirq); 1276 if (ret) 1277 goto err_nowup; 1278 1279 device_set_wakeup_enable(&pdev->dev, false); 1280 } 1281 1282 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev); 1283 if (ret) 1284 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1285 1286 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev); 1287 if (ret) 1288 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1289 1290 platform_set_drvdata(pdev, &stm32port->port); 1291 1292 pm_runtime_get_noresume(&pdev->dev); 1293 pm_runtime_set_active(&pdev->dev); 1294 pm_runtime_enable(&pdev->dev); 1295 1296 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1297 if (ret) 1298 goto err_port; 1299 1300 pm_runtime_put_sync(&pdev->dev); 1301 1302 return 0; 1303 1304 err_port: 1305 pm_runtime_disable(&pdev->dev); 1306 pm_runtime_set_suspended(&pdev->dev); 1307 pm_runtime_put_noidle(&pdev->dev); 1308 1309 if (stm32port->rx_ch) { 1310 dmaengine_terminate_async(stm32port->rx_ch); 1311 dma_release_channel(stm32port->rx_ch); 1312 } 1313 1314 if (stm32port->rx_dma_buf) 1315 dma_free_coherent(&pdev->dev, 1316 RX_BUF_L, stm32port->rx_buf, 1317 stm32port->rx_dma_buf); 1318 1319 if (stm32port->tx_ch) { 1320 dmaengine_terminate_async(stm32port->tx_ch); 1321 dma_release_channel(stm32port->tx_ch); 1322 } 1323 1324 if (stm32port->tx_dma_buf) 1325 dma_free_coherent(&pdev->dev, 1326 TX_BUF_L, stm32port->tx_buf, 1327 stm32port->tx_dma_buf); 1328 1329 if (stm32port->wakeirq > 0) 1330 dev_pm_clear_wake_irq(&pdev->dev); 1331 1332 err_nowup: 1333 if (stm32port->wakeirq > 0) 1334 device_init_wakeup(&pdev->dev, false); 1335 1336 err_uninit: 1337 stm32_usart_deinit_port(stm32port); 1338 1339 return ret; 1340 } 1341 1342 static int stm32_usart_serial_remove(struct platform_device *pdev) 1343 { 1344 struct uart_port *port = platform_get_drvdata(pdev); 1345 struct stm32_port *stm32_port = to_stm32_port(port); 1346 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1347 int err; 1348 1349 pm_runtime_get_sync(&pdev->dev); 1350 err = uart_remove_one_port(&stm32_usart_driver, port); 1351 if (err) 1352 return(err); 1353 1354 pm_runtime_disable(&pdev->dev); 1355 pm_runtime_set_suspended(&pdev->dev); 1356 pm_runtime_put_noidle(&pdev->dev); 1357 1358 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1359 1360 if (stm32_port->rx_ch) { 1361 dmaengine_terminate_async(stm32_port->rx_ch); 1362 dma_release_channel(stm32_port->rx_ch); 1363 } 1364 1365 if (stm32_port->rx_dma_buf) 1366 dma_free_coherent(&pdev->dev, 1367 RX_BUF_L, stm32_port->rx_buf, 1368 stm32_port->rx_dma_buf); 1369 1370 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1371 1372 if (stm32_port->tx_ch) { 1373 dmaengine_terminate_async(stm32_port->tx_ch); 1374 dma_release_channel(stm32_port->tx_ch); 1375 } 1376 1377 if (stm32_port->tx_dma_buf) 1378 dma_free_coherent(&pdev->dev, 1379 TX_BUF_L, stm32_port->tx_buf, 1380 stm32_port->tx_dma_buf); 1381 1382 if (stm32_port->wakeirq > 0) { 1383 dev_pm_clear_wake_irq(&pdev->dev); 1384 device_init_wakeup(&pdev->dev, false); 1385 } 1386 1387 stm32_usart_deinit_port(stm32_port); 1388 1389 return 0; 1390 } 1391 1392 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1393 static void stm32_usart_console_putchar(struct uart_port *port, int ch) 1394 { 1395 struct stm32_port *stm32_port = to_stm32_port(port); 1396 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1397 1398 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1399 cpu_relax(); 1400 1401 writel_relaxed(ch, port->membase + ofs->tdr); 1402 } 1403 1404 static void stm32_usart_console_write(struct console *co, const char *s, 1405 unsigned int cnt) 1406 { 1407 struct uart_port *port = &stm32_ports[co->index].port; 1408 struct stm32_port *stm32_port = to_stm32_port(port); 1409 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1410 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1411 unsigned long flags; 1412 u32 old_cr1, new_cr1; 1413 int locked = 1; 1414 1415 local_irq_save(flags); 1416 if (port->sysrq) 1417 locked = 0; 1418 else if (oops_in_progress) 1419 locked = spin_trylock(&port->lock); 1420 else 1421 spin_lock(&port->lock); 1422 1423 /* Save and disable interrupts, enable the transmitter */ 1424 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1425 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1426 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1427 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1428 1429 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1430 1431 /* Restore interrupt state */ 1432 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1433 1434 if (locked) 1435 spin_unlock(&port->lock); 1436 local_irq_restore(flags); 1437 } 1438 1439 static int stm32_usart_console_setup(struct console *co, char *options) 1440 { 1441 struct stm32_port *stm32port; 1442 int baud = 9600; 1443 int bits = 8; 1444 int parity = 'n'; 1445 int flow = 'n'; 1446 1447 if (co->index >= STM32_MAX_PORTS) 1448 return -ENODEV; 1449 1450 stm32port = &stm32_ports[co->index]; 1451 1452 /* 1453 * This driver does not support early console initialization 1454 * (use ARM early printk support instead), so we only expect 1455 * this to be called during the uart port registration when the 1456 * driver gets probed and the port should be mapped at that point. 1457 */ 1458 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1459 return -ENXIO; 1460 1461 if (options) 1462 uart_parse_options(options, &baud, &parity, &bits, &flow); 1463 1464 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1465 } 1466 1467 static struct console stm32_console = { 1468 .name = STM32_SERIAL_NAME, 1469 .device = uart_console_device, 1470 .write = stm32_usart_console_write, 1471 .setup = stm32_usart_console_setup, 1472 .flags = CON_PRINTBUFFER, 1473 .index = -1, 1474 .data = &stm32_usart_driver, 1475 }; 1476 1477 #define STM32_SERIAL_CONSOLE (&stm32_console) 1478 1479 #else 1480 #define STM32_SERIAL_CONSOLE NULL 1481 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1482 1483 static struct uart_driver stm32_usart_driver = { 1484 .driver_name = DRIVER_NAME, 1485 .dev_name = STM32_SERIAL_NAME, 1486 .major = 0, 1487 .minor = 0, 1488 .nr = STM32_MAX_PORTS, 1489 .cons = STM32_SERIAL_CONSOLE, 1490 }; 1491 1492 static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1493 bool enable) 1494 { 1495 struct stm32_port *stm32_port = to_stm32_port(port); 1496 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1497 1498 if (stm32_port->wakeirq <= 0) 1499 return; 1500 1501 /* 1502 * Enable low-power wake-up and wake-up irq if argument is set to 1503 * "enable", disable low-power wake-up and wake-up irq otherwise 1504 */ 1505 if (enable) { 1506 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 1507 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); 1508 } else { 1509 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1510 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 1511 } 1512 } 1513 1514 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 1515 { 1516 struct uart_port *port = dev_get_drvdata(dev); 1517 1518 uart_suspend_port(&stm32_usart_driver, port); 1519 1520 if (device_may_wakeup(dev)) 1521 stm32_usart_serial_en_wakeup(port, true); 1522 else 1523 stm32_usart_serial_en_wakeup(port, false); 1524 1525 /* 1526 * When "no_console_suspend" is enabled, keep the pinctrl default state 1527 * and rely on bootloader stage to restore this state upon resume. 1528 * Otherwise, apply the idle or sleep states depending on wakeup 1529 * capabilities. 1530 */ 1531 if (console_suspend_enabled || !uart_console(port)) { 1532 if (device_may_wakeup(dev)) 1533 pinctrl_pm_select_idle_state(dev); 1534 else 1535 pinctrl_pm_select_sleep_state(dev); 1536 } 1537 1538 return 0; 1539 } 1540 1541 static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 1542 { 1543 struct uart_port *port = dev_get_drvdata(dev); 1544 1545 pinctrl_pm_select_default_state(dev); 1546 1547 if (device_may_wakeup(dev)) 1548 stm32_usart_serial_en_wakeup(port, false); 1549 1550 return uart_resume_port(&stm32_usart_driver, port); 1551 } 1552 1553 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 1554 { 1555 struct uart_port *port = dev_get_drvdata(dev); 1556 struct stm32_port *stm32port = container_of(port, 1557 struct stm32_port, port); 1558 1559 clk_disable_unprepare(stm32port->clk); 1560 1561 return 0; 1562 } 1563 1564 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 1565 { 1566 struct uart_port *port = dev_get_drvdata(dev); 1567 struct stm32_port *stm32port = container_of(port, 1568 struct stm32_port, port); 1569 1570 return clk_prepare_enable(stm32port->clk); 1571 } 1572 1573 static const struct dev_pm_ops stm32_serial_pm_ops = { 1574 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 1575 stm32_usart_runtime_resume, NULL) 1576 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 1577 stm32_usart_serial_resume) 1578 }; 1579 1580 static struct platform_driver stm32_serial_driver = { 1581 .probe = stm32_usart_serial_probe, 1582 .remove = stm32_usart_serial_remove, 1583 .driver = { 1584 .name = DRIVER_NAME, 1585 .pm = &stm32_serial_pm_ops, 1586 .of_match_table = of_match_ptr(stm32_match), 1587 }, 1588 }; 1589 1590 static int __init stm32_usart_init(void) 1591 { 1592 static char banner[] __initdata = "STM32 USART driver initialized"; 1593 int ret; 1594 1595 pr_info("%s\n", banner); 1596 1597 ret = uart_register_driver(&stm32_usart_driver); 1598 if (ret) 1599 return ret; 1600 1601 ret = platform_driver_register(&stm32_serial_driver); 1602 if (ret) 1603 uart_unregister_driver(&stm32_usart_driver); 1604 1605 return ret; 1606 } 1607 1608 static void __exit stm32_usart_exit(void) 1609 { 1610 platform_driver_unregister(&stm32_serial_driver); 1611 uart_unregister_driver(&stm32_usart_driver); 1612 } 1613 1614 module_init(stm32_usart_init); 1615 module_exit(stm32_usart_exit); 1616 1617 MODULE_ALIAS("platform:" DRIVER_NAME); 1618 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1619 MODULE_LICENSE("GPL v2"); 1620