1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@foss.st.com> 7 * Erwan Le Ray <erwan.leray@foss.st.com> 8 * 9 * Inspired by st-asc.c from STMicroelectronics (c) 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/delay.h> 15 #include <linux/dma-direction.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "serial_mctrl_gpio.h" 36 #include "stm32-usart.h" 37 38 static void stm32_usart_stop_tx(struct uart_port *port); 39 static void stm32_usart_transmit_chars(struct uart_port *port); 40 41 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 42 { 43 return container_of(port, struct stm32_port, port); 44 } 45 46 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 47 { 48 u32 val; 49 50 val = readl_relaxed(port->membase + reg); 51 val |= bits; 52 writel_relaxed(val, port->membase + reg); 53 } 54 55 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 56 { 57 u32 val; 58 59 val = readl_relaxed(port->membase + reg); 60 val &= ~bits; 61 writel_relaxed(val, port->membase + reg); 62 } 63 64 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 65 u32 delay_DDE, u32 baud) 66 { 67 u32 rs485_deat_dedt; 68 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 69 bool over8; 70 71 *cr3 |= USART_CR3_DEM; 72 over8 = *cr1 & USART_CR1_OVER8; 73 74 if (over8) 75 rs485_deat_dedt = delay_ADE * baud * 8; 76 else 77 rs485_deat_dedt = delay_ADE * baud * 16; 78 79 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 80 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 81 rs485_deat_dedt_max : rs485_deat_dedt; 82 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 83 USART_CR1_DEAT_MASK; 84 *cr1 |= rs485_deat_dedt; 85 86 if (over8) 87 rs485_deat_dedt = delay_DDE * baud * 8; 88 else 89 rs485_deat_dedt = delay_DDE * baud * 16; 90 91 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 92 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 93 rs485_deat_dedt_max : rs485_deat_dedt; 94 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 95 USART_CR1_DEDT_MASK; 96 *cr1 |= rs485_deat_dedt; 97 } 98 99 static int stm32_usart_config_rs485(struct uart_port *port, 100 struct serial_rs485 *rs485conf) 101 { 102 struct stm32_port *stm32_port = to_stm32_port(port); 103 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 104 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 105 u32 usartdiv, baud, cr1, cr3; 106 bool over8; 107 108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 109 110 port->rs485 = *rs485conf; 111 112 rs485conf->flags |= SER_RS485_RX_DURING_TX; 113 114 if (rs485conf->flags & SER_RS485_ENABLED) { 115 cr1 = readl_relaxed(port->membase + ofs->cr1); 116 cr3 = readl_relaxed(port->membase + ofs->cr3); 117 usartdiv = readl_relaxed(port->membase + ofs->brr); 118 usartdiv = usartdiv & GENMASK(15, 0); 119 over8 = cr1 & USART_CR1_OVER8; 120 121 if (over8) 122 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 123 << USART_BRR_04_R_SHIFT; 124 125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 126 stm32_usart_config_reg_rs485(&cr1, &cr3, 127 rs485conf->delay_rts_before_send, 128 rs485conf->delay_rts_after_send, 129 baud); 130 131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 132 cr3 &= ~USART_CR3_DEP; 133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 134 } else { 135 cr3 |= USART_CR3_DEP; 136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 137 } 138 139 writel_relaxed(cr3, port->membase + ofs->cr3); 140 writel_relaxed(cr1, port->membase + ofs->cr1); 141 } else { 142 stm32_usart_clr_bits(port, ofs->cr3, 143 USART_CR3_DEM | USART_CR3_DEP); 144 stm32_usart_clr_bits(port, ofs->cr1, 145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 146 } 147 148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 149 150 return 0; 151 } 152 153 static int stm32_usart_init_rs485(struct uart_port *port, 154 struct platform_device *pdev) 155 { 156 struct serial_rs485 *rs485conf = &port->rs485; 157 158 rs485conf->flags = 0; 159 rs485conf->delay_rts_before_send = 0; 160 rs485conf->delay_rts_after_send = 0; 161 162 if (!pdev->dev.of_node) 163 return -ENODEV; 164 165 return uart_get_rs485_mode(port); 166 } 167 168 static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr, 169 int *last_res, bool threaded) 170 { 171 struct stm32_port *stm32_port = to_stm32_port(port); 172 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 173 enum dma_status status; 174 struct dma_tx_state state; 175 176 *sr = readl_relaxed(port->membase + ofs->isr); 177 178 if (threaded && stm32_port->rx_ch) { 179 status = dmaengine_tx_status(stm32_port->rx_ch, 180 stm32_port->rx_ch->cookie, 181 &state); 182 if (status == DMA_IN_PROGRESS && (*last_res != state.residue)) 183 return 1; 184 else 185 return 0; 186 } else if (*sr & USART_SR_RXNE) { 187 return 1; 188 } 189 return 0; 190 } 191 192 static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr, 193 int *last_res) 194 { 195 struct stm32_port *stm32_port = to_stm32_port(port); 196 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 197 unsigned long c; 198 199 if (stm32_port->rx_ch) { 200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 201 if ((*last_res) == 0) 202 *last_res = RX_BUF_L; 203 } else { 204 c = readl_relaxed(port->membase + ofs->rdr); 205 /* apply RDR data mask */ 206 c &= stm32_port->rdr_mask; 207 } 208 209 return c; 210 } 211 212 static void stm32_usart_receive_chars(struct uart_port *port, bool threaded) 213 { 214 struct tty_port *tport = &port->state->port; 215 struct stm32_port *stm32_port = to_stm32_port(port); 216 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 217 unsigned long c; 218 u32 sr; 219 char flag; 220 221 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 222 pm_wakeup_event(tport->tty->dev, 0); 223 224 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, 225 threaded)) { 226 sr |= USART_SR_DUMMY_RX; 227 flag = TTY_NORMAL; 228 229 /* 230 * Status bits has to be cleared before reading the RDR: 231 * In FIFO mode, reading the RDR will pop the next data 232 * (if any) along with its status bits into the SR. 233 * Not doing so leads to misalignement between RDR and SR, 234 * and clear status bits of the next rx data. 235 * 236 * Clear errors flags for stm32f7 and stm32h7 compatible 237 * devices. On stm32f4 compatible devices, the error bit is 238 * cleared by the sequence [read SR - read DR]. 239 */ 240 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 241 writel_relaxed(sr & USART_SR_ERR_MASK, 242 port->membase + ofs->icr); 243 244 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); 245 port->icount.rx++; 246 if (sr & USART_SR_ERR_MASK) { 247 if (sr & USART_SR_ORE) { 248 port->icount.overrun++; 249 } else if (sr & USART_SR_PE) { 250 port->icount.parity++; 251 } else if (sr & USART_SR_FE) { 252 /* Break detection if character is null */ 253 if (!c) { 254 port->icount.brk++; 255 if (uart_handle_break(port)) 256 continue; 257 } else { 258 port->icount.frame++; 259 } 260 } 261 262 sr &= port->read_status_mask; 263 264 if (sr & USART_SR_PE) { 265 flag = TTY_PARITY; 266 } else if (sr & USART_SR_FE) { 267 if (!c) 268 flag = TTY_BREAK; 269 else 270 flag = TTY_FRAME; 271 } 272 } 273 274 if (uart_handle_sysrq_char(port, c)) 275 continue; 276 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 277 } 278 279 spin_unlock(&port->lock); 280 tty_flip_buffer_push(tport); 281 spin_lock(&port->lock); 282 } 283 284 static void stm32_usart_tx_dma_complete(void *arg) 285 { 286 struct uart_port *port = arg; 287 struct stm32_port *stm32port = to_stm32_port(port); 288 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 289 290 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 291 stm32port->tx_dma_busy = false; 292 293 /* Let's see if we have pending data to send */ 294 stm32_usart_transmit_chars(port); 295 } 296 297 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 298 { 299 struct stm32_port *stm32_port = to_stm32_port(port); 300 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 301 302 /* 303 * Enables TX FIFO threashold irq when FIFO is enabled, 304 * or TX empty irq when FIFO is disabled 305 */ 306 if (stm32_port->fifoen) 307 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 308 else 309 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 310 } 311 312 static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 313 { 314 struct stm32_port *stm32_port = to_stm32_port(port); 315 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 316 317 if (stm32_port->fifoen) 318 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 319 else 320 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 321 } 322 323 static void stm32_usart_transmit_chars_pio(struct uart_port *port) 324 { 325 struct stm32_port *stm32_port = to_stm32_port(port); 326 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 327 struct circ_buf *xmit = &port->state->xmit; 328 329 if (stm32_port->tx_dma_busy) { 330 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 331 stm32_port->tx_dma_busy = false; 332 } 333 334 while (!uart_circ_empty(xmit)) { 335 /* Check that TDR is empty before filling FIFO */ 336 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 337 break; 338 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 339 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 340 port->icount.tx++; 341 } 342 343 /* rely on TXE irq (mask or unmask) for sending remaining data */ 344 if (uart_circ_empty(xmit)) 345 stm32_usart_tx_interrupt_disable(port); 346 else 347 stm32_usart_tx_interrupt_enable(port); 348 } 349 350 static void stm32_usart_transmit_chars_dma(struct uart_port *port) 351 { 352 struct stm32_port *stm32port = to_stm32_port(port); 353 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 354 struct circ_buf *xmit = &port->state->xmit; 355 struct dma_async_tx_descriptor *desc = NULL; 356 unsigned int count, i; 357 358 if (stm32port->tx_dma_busy) 359 return; 360 361 stm32port->tx_dma_busy = true; 362 363 count = uart_circ_chars_pending(xmit); 364 365 if (count > TX_BUF_L) 366 count = TX_BUF_L; 367 368 if (xmit->tail < xmit->head) { 369 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 370 } else { 371 size_t one = UART_XMIT_SIZE - xmit->tail; 372 size_t two; 373 374 if (one > count) 375 one = count; 376 two = count - one; 377 378 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 379 if (two) 380 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 381 } 382 383 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 384 stm32port->tx_dma_buf, 385 count, 386 DMA_MEM_TO_DEV, 387 DMA_PREP_INTERRUPT); 388 389 if (!desc) 390 goto fallback_err; 391 392 desc->callback = stm32_usart_tx_dma_complete; 393 desc->callback_param = port; 394 395 /* Push current DMA TX transaction in the pending queue */ 396 if (dma_submit_error(dmaengine_submit(desc))) { 397 /* dma no yet started, safe to free resources */ 398 dmaengine_terminate_async(stm32port->tx_ch); 399 goto fallback_err; 400 } 401 402 /* Issue pending DMA TX requests */ 403 dma_async_issue_pending(stm32port->tx_ch); 404 405 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 406 407 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 408 port->icount.tx += count; 409 return; 410 411 fallback_err: 412 for (i = count; i > 0; i--) 413 stm32_usart_transmit_chars_pio(port); 414 } 415 416 static void stm32_usart_transmit_chars(struct uart_port *port) 417 { 418 struct stm32_port *stm32_port = to_stm32_port(port); 419 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 420 struct circ_buf *xmit = &port->state->xmit; 421 422 if (port->x_char) { 423 if (stm32_port->tx_dma_busy) 424 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 425 writel_relaxed(port->x_char, port->membase + ofs->tdr); 426 port->x_char = 0; 427 port->icount.tx++; 428 if (stm32_port->tx_dma_busy) 429 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 430 return; 431 } 432 433 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 434 stm32_usart_tx_interrupt_disable(port); 435 return; 436 } 437 438 if (ofs->icr == UNDEF_REG) 439 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 440 else 441 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 442 443 if (stm32_port->tx_ch) 444 stm32_usart_transmit_chars_dma(port); 445 else 446 stm32_usart_transmit_chars_pio(port); 447 448 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 449 uart_write_wakeup(port); 450 451 if (uart_circ_empty(xmit)) 452 stm32_usart_tx_interrupt_disable(port); 453 } 454 455 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 456 { 457 struct uart_port *port = ptr; 458 struct stm32_port *stm32_port = to_stm32_port(port); 459 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 460 u32 sr; 461 462 spin_lock(&port->lock); 463 464 sr = readl_relaxed(port->membase + ofs->isr); 465 466 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 467 writel_relaxed(USART_ICR_RTOCF, 468 port->membase + ofs->icr); 469 470 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) 471 writel_relaxed(USART_ICR_WUCF, 472 port->membase + ofs->icr); 473 474 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 475 stm32_usart_receive_chars(port, false); 476 477 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 478 stm32_usart_transmit_chars(port); 479 480 spin_unlock(&port->lock); 481 482 if (stm32_port->rx_ch) 483 return IRQ_WAKE_THREAD; 484 else 485 return IRQ_HANDLED; 486 } 487 488 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr) 489 { 490 struct uart_port *port = ptr; 491 struct stm32_port *stm32_port = to_stm32_port(port); 492 493 spin_lock(&port->lock); 494 495 if (stm32_port->rx_ch) 496 stm32_usart_receive_chars(port, true); 497 498 spin_unlock(&port->lock); 499 500 return IRQ_HANDLED; 501 } 502 503 static unsigned int stm32_usart_tx_empty(struct uart_port *port) 504 { 505 struct stm32_port *stm32_port = to_stm32_port(port); 506 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 507 508 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 509 } 510 511 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 512 { 513 struct stm32_port *stm32_port = to_stm32_port(port); 514 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 515 516 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 517 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 518 else 519 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 520 521 mctrl_gpio_set(stm32_port->gpios, mctrl); 522 } 523 524 static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 525 { 526 struct stm32_port *stm32_port = to_stm32_port(port); 527 unsigned int ret; 528 529 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 530 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 531 532 return mctrl_gpio_get(stm32_port->gpios, &ret); 533 } 534 535 static void stm32_usart_enable_ms(struct uart_port *port) 536 { 537 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 538 } 539 540 static void stm32_usart_disable_ms(struct uart_port *port) 541 { 542 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 543 } 544 545 /* Transmit stop */ 546 static void stm32_usart_stop_tx(struct uart_port *port) 547 { 548 struct stm32_port *stm32_port = to_stm32_port(port); 549 struct serial_rs485 *rs485conf = &port->rs485; 550 551 stm32_usart_tx_interrupt_disable(port); 552 553 if (rs485conf->flags & SER_RS485_ENABLED) { 554 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 555 mctrl_gpio_set(stm32_port->gpios, 556 stm32_port->port.mctrl & ~TIOCM_RTS); 557 } else { 558 mctrl_gpio_set(stm32_port->gpios, 559 stm32_port->port.mctrl | TIOCM_RTS); 560 } 561 } 562 } 563 564 /* There are probably characters waiting to be transmitted. */ 565 static void stm32_usart_start_tx(struct uart_port *port) 566 { 567 struct stm32_port *stm32_port = to_stm32_port(port); 568 struct serial_rs485 *rs485conf = &port->rs485; 569 struct circ_buf *xmit = &port->state->xmit; 570 571 if (uart_circ_empty(xmit)) 572 return; 573 574 if (rs485conf->flags & SER_RS485_ENABLED) { 575 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 576 mctrl_gpio_set(stm32_port->gpios, 577 stm32_port->port.mctrl | TIOCM_RTS); 578 } else { 579 mctrl_gpio_set(stm32_port->gpios, 580 stm32_port->port.mctrl & ~TIOCM_RTS); 581 } 582 } 583 584 stm32_usart_transmit_chars(port); 585 } 586 587 /* Throttle the remote when input buffer is about to overflow. */ 588 static void stm32_usart_throttle(struct uart_port *port) 589 { 590 struct stm32_port *stm32_port = to_stm32_port(port); 591 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 592 unsigned long flags; 593 594 spin_lock_irqsave(&port->lock, flags); 595 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 596 if (stm32_port->cr3_irq) 597 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 598 599 spin_unlock_irqrestore(&port->lock, flags); 600 } 601 602 /* Unthrottle the remote, the input buffer can now accept data. */ 603 static void stm32_usart_unthrottle(struct uart_port *port) 604 { 605 struct stm32_port *stm32_port = to_stm32_port(port); 606 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 607 unsigned long flags; 608 609 spin_lock_irqsave(&port->lock, flags); 610 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 611 if (stm32_port->cr3_irq) 612 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 613 614 spin_unlock_irqrestore(&port->lock, flags); 615 } 616 617 /* Receive stop */ 618 static void stm32_usart_stop_rx(struct uart_port *port) 619 { 620 struct stm32_port *stm32_port = to_stm32_port(port); 621 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 622 623 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 624 if (stm32_port->cr3_irq) 625 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 626 } 627 628 /* Handle breaks - ignored by us */ 629 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 630 { 631 } 632 633 static int stm32_usart_startup(struct uart_port *port) 634 { 635 struct stm32_port *stm32_port = to_stm32_port(port); 636 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 637 const char *name = to_platform_device(port->dev)->name; 638 u32 val; 639 int ret; 640 641 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, 642 stm32_usart_threaded_interrupt, 643 IRQF_NO_SUSPEND, name, port); 644 if (ret) 645 return ret; 646 647 /* RX FIFO Flush */ 648 if (ofs->rqr != UNDEF_REG) 649 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); 650 651 /* Tx and RX FIFO configuration */ 652 if (stm32_port->fifoen) { 653 val = readl_relaxed(port->membase + ofs->cr3); 654 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 655 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 656 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 657 writel_relaxed(val, port->membase + ofs->cr3); 658 } 659 660 /* RX FIFO enabling */ 661 val = stm32_port->cr1_irq | USART_CR1_RE; 662 if (stm32_port->fifoen) 663 val |= USART_CR1_FIFOEN; 664 stm32_usart_set_bits(port, ofs->cr1, val); 665 666 return 0; 667 } 668 669 static void stm32_usart_shutdown(struct uart_port *port) 670 { 671 struct stm32_port *stm32_port = to_stm32_port(port); 672 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 673 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 674 u32 val, isr; 675 int ret; 676 677 /* Disable modem control interrupts */ 678 stm32_usart_disable_ms(port); 679 680 val = USART_CR1_TXEIE | USART_CR1_TE; 681 val |= stm32_port->cr1_irq | USART_CR1_RE; 682 val |= BIT(cfg->uart_enable_bit); 683 if (stm32_port->fifoen) 684 val |= USART_CR1_FIFOEN; 685 686 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 687 isr, (isr & USART_SR_TC), 688 10, 100000); 689 690 if (ret) 691 dev_err(port->dev, "transmission complete not set\n"); 692 693 stm32_usart_clr_bits(port, ofs->cr1, val); 694 695 free_irq(port->irq, port); 696 } 697 698 static unsigned int stm32_usart_get_databits(struct ktermios *termios) 699 { 700 unsigned int bits; 701 702 tcflag_t cflag = termios->c_cflag; 703 704 switch (cflag & CSIZE) { 705 /* 706 * CSIZE settings are not necessarily supported in hardware. 707 * CSIZE unsupported configurations are handled here to set word length 708 * to 8 bits word as default configuration and to print debug message. 709 */ 710 case CS5: 711 bits = 5; 712 break; 713 case CS6: 714 bits = 6; 715 break; 716 case CS7: 717 bits = 7; 718 break; 719 /* default including CS8 */ 720 default: 721 bits = 8; 722 break; 723 } 724 725 return bits; 726 } 727 728 static void stm32_usart_set_termios(struct uart_port *port, 729 struct ktermios *termios, 730 struct ktermios *old) 731 { 732 struct stm32_port *stm32_port = to_stm32_port(port); 733 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 734 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 735 struct serial_rs485 *rs485conf = &port->rs485; 736 unsigned int baud, bits; 737 u32 usartdiv, mantissa, fraction, oversampling; 738 tcflag_t cflag = termios->c_cflag; 739 u32 cr1, cr2, cr3; 740 unsigned long flags; 741 742 if (!stm32_port->hw_flow_control) 743 cflag &= ~CRTSCTS; 744 745 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 746 747 spin_lock_irqsave(&port->lock, flags); 748 749 /* Stop serial port and reset value */ 750 writel_relaxed(0, port->membase + ofs->cr1); 751 752 /* flush RX & TX FIFO */ 753 if (ofs->rqr != UNDEF_REG) 754 stm32_usart_set_bits(port, ofs->rqr, 755 USART_RQR_TXFRQ | USART_RQR_RXFRQ); 756 757 cr1 = USART_CR1_TE | USART_CR1_RE; 758 if (stm32_port->fifoen) 759 cr1 |= USART_CR1_FIFOEN; 760 cr2 = 0; 761 cr3 = readl_relaxed(port->membase + ofs->cr3); 762 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE 763 | USART_CR3_TXFTCFG_MASK; 764 765 if (cflag & CSTOPB) 766 cr2 |= USART_CR2_STOP_2B; 767 768 bits = stm32_usart_get_databits(termios); 769 stm32_port->rdr_mask = (BIT(bits) - 1); 770 771 if (cflag & PARENB) { 772 bits++; 773 cr1 |= USART_CR1_PCE; 774 } 775 776 /* 777 * Word length configuration: 778 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 779 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 780 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 781 * M0 and M1 already cleared by cr1 initialization. 782 */ 783 if (bits == 9) 784 cr1 |= USART_CR1_M0; 785 else if ((bits == 7) && cfg->has_7bits_data) 786 cr1 |= USART_CR1_M1; 787 else if (bits != 8) 788 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 789 , bits); 790 791 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 792 stm32_port->fifoen)) { 793 if (cflag & CSTOPB) 794 bits = bits + 3; /* 1 start bit + 2 stop bits */ 795 else 796 bits = bits + 2; /* 1 start bit + 1 stop bit */ 797 798 /* RX timeout irq to occur after last stop bit + bits */ 799 stm32_port->cr1_irq = USART_CR1_RTOIE; 800 writel_relaxed(bits, port->membase + ofs->rtor); 801 cr2 |= USART_CR2_RTOEN; 802 /* Not using dma, enable fifo threshold irq */ 803 if (!stm32_port->rx_ch) 804 stm32_port->cr3_irq = USART_CR3_RXFTIE; 805 } 806 807 cr1 |= stm32_port->cr1_irq; 808 cr3 |= stm32_port->cr3_irq; 809 810 if (cflag & PARODD) 811 cr1 |= USART_CR1_PS; 812 813 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 814 if (cflag & CRTSCTS) { 815 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 816 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 817 } 818 819 /* Handle modem control interrupts */ 820 if (UART_ENABLE_MS(port, termios->c_cflag)) 821 stm32_usart_enable_ms(port); 822 else 823 stm32_usart_disable_ms(port); 824 825 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 826 827 /* 828 * The USART supports 16 or 8 times oversampling. 829 * By default we prefer 16 times oversampling, so that the receiver 830 * has a better tolerance to clock deviations. 831 * 8 times oversampling is only used to achieve higher speeds. 832 */ 833 if (usartdiv < 16) { 834 oversampling = 8; 835 cr1 |= USART_CR1_OVER8; 836 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 837 } else { 838 oversampling = 16; 839 cr1 &= ~USART_CR1_OVER8; 840 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 841 } 842 843 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 844 fraction = usartdiv % oversampling; 845 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 846 847 uart_update_timeout(port, cflag, baud); 848 849 port->read_status_mask = USART_SR_ORE; 850 if (termios->c_iflag & INPCK) 851 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 852 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 853 port->read_status_mask |= USART_SR_FE; 854 855 /* Characters to ignore */ 856 port->ignore_status_mask = 0; 857 if (termios->c_iflag & IGNPAR) 858 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 859 if (termios->c_iflag & IGNBRK) { 860 port->ignore_status_mask |= USART_SR_FE; 861 /* 862 * If we're ignoring parity and break indicators, 863 * ignore overruns too (for real raw support). 864 */ 865 if (termios->c_iflag & IGNPAR) 866 port->ignore_status_mask |= USART_SR_ORE; 867 } 868 869 /* Ignore all characters if CREAD is not set */ 870 if ((termios->c_cflag & CREAD) == 0) 871 port->ignore_status_mask |= USART_SR_DUMMY_RX; 872 873 if (stm32_port->rx_ch) 874 cr3 |= USART_CR3_DMAR; 875 876 if (rs485conf->flags & SER_RS485_ENABLED) { 877 stm32_usart_config_reg_rs485(&cr1, &cr3, 878 rs485conf->delay_rts_before_send, 879 rs485conf->delay_rts_after_send, 880 baud); 881 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 882 cr3 &= ~USART_CR3_DEP; 883 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 884 } else { 885 cr3 |= USART_CR3_DEP; 886 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 887 } 888 889 } else { 890 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 891 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 892 } 893 894 writel_relaxed(cr3, port->membase + ofs->cr3); 895 writel_relaxed(cr2, port->membase + ofs->cr2); 896 writel_relaxed(cr1, port->membase + ofs->cr1); 897 898 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 899 spin_unlock_irqrestore(&port->lock, flags); 900 } 901 902 static const char *stm32_usart_type(struct uart_port *port) 903 { 904 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 905 } 906 907 static void stm32_usart_release_port(struct uart_port *port) 908 { 909 } 910 911 static int stm32_usart_request_port(struct uart_port *port) 912 { 913 return 0; 914 } 915 916 static void stm32_usart_config_port(struct uart_port *port, int flags) 917 { 918 if (flags & UART_CONFIG_TYPE) 919 port->type = PORT_STM32; 920 } 921 922 static int 923 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 924 { 925 /* No user changeable parameters */ 926 return -EINVAL; 927 } 928 929 static void stm32_usart_pm(struct uart_port *port, unsigned int state, 930 unsigned int oldstate) 931 { 932 struct stm32_port *stm32port = container_of(port, 933 struct stm32_port, port); 934 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 935 struct stm32_usart_config *cfg = &stm32port->info->cfg; 936 unsigned long flags = 0; 937 938 switch (state) { 939 case UART_PM_STATE_ON: 940 pm_runtime_get_sync(port->dev); 941 break; 942 case UART_PM_STATE_OFF: 943 spin_lock_irqsave(&port->lock, flags); 944 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 945 spin_unlock_irqrestore(&port->lock, flags); 946 pm_runtime_put_sync(port->dev); 947 break; 948 } 949 } 950 951 static const struct uart_ops stm32_uart_ops = { 952 .tx_empty = stm32_usart_tx_empty, 953 .set_mctrl = stm32_usart_set_mctrl, 954 .get_mctrl = stm32_usart_get_mctrl, 955 .stop_tx = stm32_usart_stop_tx, 956 .start_tx = stm32_usart_start_tx, 957 .throttle = stm32_usart_throttle, 958 .unthrottle = stm32_usart_unthrottle, 959 .stop_rx = stm32_usart_stop_rx, 960 .enable_ms = stm32_usart_enable_ms, 961 .break_ctl = stm32_usart_break_ctl, 962 .startup = stm32_usart_startup, 963 .shutdown = stm32_usart_shutdown, 964 .set_termios = stm32_usart_set_termios, 965 .pm = stm32_usart_pm, 966 .type = stm32_usart_type, 967 .release_port = stm32_usart_release_port, 968 .request_port = stm32_usart_request_port, 969 .config_port = stm32_usart_config_port, 970 .verify_port = stm32_usart_verify_port, 971 }; 972 973 static int stm32_usart_init_port(struct stm32_port *stm32port, 974 struct platform_device *pdev) 975 { 976 struct uart_port *port = &stm32port->port; 977 struct resource *res; 978 int ret; 979 980 ret = platform_get_irq(pdev, 0); 981 if (ret <= 0) 982 return ret ? : -ENODEV; 983 984 port->iotype = UPIO_MEM; 985 port->flags = UPF_BOOT_AUTOCONF; 986 port->ops = &stm32_uart_ops; 987 port->dev = &pdev->dev; 988 port->fifosize = stm32port->info->cfg.fifosize; 989 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 990 port->irq = ret; 991 port->rs485_config = stm32_usart_config_rs485; 992 993 ret = stm32_usart_init_rs485(port, pdev); 994 if (ret) 995 return ret; 996 997 if (stm32port->info->cfg.has_wakeup) { 998 stm32port->wakeirq = platform_get_irq_optional(pdev, 1); 999 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) 1000 return stm32port->wakeirq ? : -ENODEV; 1001 } 1002 1003 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1004 1005 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1006 port->membase = devm_ioremap_resource(&pdev->dev, res); 1007 if (IS_ERR(port->membase)) 1008 return PTR_ERR(port->membase); 1009 port->mapbase = res->start; 1010 1011 spin_lock_init(&port->lock); 1012 1013 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1014 if (IS_ERR(stm32port->clk)) 1015 return PTR_ERR(stm32port->clk); 1016 1017 /* Ensure that clk rate is correct by enabling the clk */ 1018 ret = clk_prepare_enable(stm32port->clk); 1019 if (ret) 1020 return ret; 1021 1022 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1023 if (!stm32port->port.uartclk) { 1024 ret = -EINVAL; 1025 goto err_clk; 1026 } 1027 1028 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1029 if (IS_ERR(stm32port->gpios)) { 1030 ret = PTR_ERR(stm32port->gpios); 1031 goto err_clk; 1032 } 1033 1034 /* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */ 1035 if (stm32port->hw_flow_control) { 1036 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1037 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1038 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1039 ret = -EINVAL; 1040 goto err_clk; 1041 } 1042 } 1043 1044 return ret; 1045 1046 err_clk: 1047 clk_disable_unprepare(stm32port->clk); 1048 1049 return ret; 1050 } 1051 1052 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1053 { 1054 struct device_node *np = pdev->dev.of_node; 1055 int id; 1056 1057 if (!np) 1058 return NULL; 1059 1060 id = of_alias_get_id(np, "serial"); 1061 if (id < 0) { 1062 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1063 return NULL; 1064 } 1065 1066 if (WARN_ON(id >= STM32_MAX_PORTS)) 1067 return NULL; 1068 1069 stm32_ports[id].hw_flow_control = 1070 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1071 of_property_read_bool (np, "uart-has-rtscts"); 1072 stm32_ports[id].port.line = id; 1073 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1074 stm32_ports[id].cr3_irq = 0; 1075 stm32_ports[id].last_res = RX_BUF_L; 1076 return &stm32_ports[id]; 1077 } 1078 1079 #ifdef CONFIG_OF 1080 static const struct of_device_id stm32_match[] = { 1081 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1082 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1083 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1084 {}, 1085 }; 1086 1087 MODULE_DEVICE_TABLE(of, stm32_match); 1088 #endif 1089 1090 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1091 struct platform_device *pdev) 1092 { 1093 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1094 struct uart_port *port = &stm32port->port; 1095 struct device *dev = &pdev->dev; 1096 struct dma_slave_config config; 1097 struct dma_async_tx_descriptor *desc = NULL; 1098 int ret; 1099 1100 /* Request DMA RX channel */ 1101 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1102 if (!stm32port->rx_ch) { 1103 dev_info(dev, "rx dma alloc failed\n"); 1104 return -ENODEV; 1105 } 1106 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1107 &stm32port->rx_dma_buf, 1108 GFP_KERNEL); 1109 if (!stm32port->rx_buf) { 1110 ret = -ENOMEM; 1111 goto alloc_err; 1112 } 1113 1114 /* Configure DMA channel */ 1115 memset(&config, 0, sizeof(config)); 1116 config.src_addr = port->mapbase + ofs->rdr; 1117 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1118 1119 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1120 if (ret < 0) { 1121 dev_err(dev, "rx dma channel config failed\n"); 1122 ret = -ENODEV; 1123 goto config_err; 1124 } 1125 1126 /* Prepare a DMA cyclic transaction */ 1127 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1128 stm32port->rx_dma_buf, 1129 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1130 DMA_PREP_INTERRUPT); 1131 if (!desc) { 1132 dev_err(dev, "rx dma prep cyclic failed\n"); 1133 ret = -ENODEV; 1134 goto config_err; 1135 } 1136 1137 /* No callback as dma buffer is drained on usart interrupt */ 1138 desc->callback = NULL; 1139 desc->callback_param = NULL; 1140 1141 /* Push current DMA transaction in the pending queue */ 1142 ret = dma_submit_error(dmaengine_submit(desc)); 1143 if (ret) { 1144 dmaengine_terminate_sync(stm32port->rx_ch); 1145 goto config_err; 1146 } 1147 1148 /* Issue pending DMA requests */ 1149 dma_async_issue_pending(stm32port->rx_ch); 1150 1151 return 0; 1152 1153 config_err: 1154 dma_free_coherent(&pdev->dev, 1155 RX_BUF_L, stm32port->rx_buf, 1156 stm32port->rx_dma_buf); 1157 1158 alloc_err: 1159 dma_release_channel(stm32port->rx_ch); 1160 stm32port->rx_ch = NULL; 1161 1162 return ret; 1163 } 1164 1165 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1166 struct platform_device *pdev) 1167 { 1168 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1169 struct uart_port *port = &stm32port->port; 1170 struct device *dev = &pdev->dev; 1171 struct dma_slave_config config; 1172 int ret; 1173 1174 stm32port->tx_dma_busy = false; 1175 1176 /* Request DMA TX channel */ 1177 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1178 if (!stm32port->tx_ch) { 1179 dev_info(dev, "tx dma alloc failed\n"); 1180 return -ENODEV; 1181 } 1182 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1183 &stm32port->tx_dma_buf, 1184 GFP_KERNEL); 1185 if (!stm32port->tx_buf) { 1186 ret = -ENOMEM; 1187 goto alloc_err; 1188 } 1189 1190 /* Configure DMA channel */ 1191 memset(&config, 0, sizeof(config)); 1192 config.dst_addr = port->mapbase + ofs->tdr; 1193 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1194 1195 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1196 if (ret < 0) { 1197 dev_err(dev, "tx dma channel config failed\n"); 1198 ret = -ENODEV; 1199 goto config_err; 1200 } 1201 1202 return 0; 1203 1204 config_err: 1205 dma_free_coherent(&pdev->dev, 1206 TX_BUF_L, stm32port->tx_buf, 1207 stm32port->tx_dma_buf); 1208 1209 alloc_err: 1210 dma_release_channel(stm32port->tx_ch); 1211 stm32port->tx_ch = NULL; 1212 1213 return ret; 1214 } 1215 1216 static int stm32_usart_serial_probe(struct platform_device *pdev) 1217 { 1218 const struct of_device_id *match; 1219 struct stm32_port *stm32port; 1220 int ret; 1221 1222 stm32port = stm32_usart_of_get_port(pdev); 1223 if (!stm32port) 1224 return -ENODEV; 1225 1226 match = of_match_device(stm32_match, &pdev->dev); 1227 if (match && match->data) 1228 stm32port->info = (struct stm32_usart_info *)match->data; 1229 else 1230 return -EINVAL; 1231 1232 ret = stm32_usart_init_port(stm32port, pdev); 1233 if (ret) 1234 return ret; 1235 1236 if (stm32port->wakeirq > 0) { 1237 ret = device_init_wakeup(&pdev->dev, true); 1238 if (ret) 1239 goto err_uninit; 1240 1241 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1242 stm32port->wakeirq); 1243 if (ret) 1244 goto err_nowup; 1245 1246 device_set_wakeup_enable(&pdev->dev, false); 1247 } 1248 1249 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1250 if (ret) 1251 goto err_wirq; 1252 1253 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev); 1254 if (ret) 1255 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1256 1257 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev); 1258 if (ret) 1259 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1260 1261 platform_set_drvdata(pdev, &stm32port->port); 1262 1263 pm_runtime_get_noresume(&pdev->dev); 1264 pm_runtime_set_active(&pdev->dev); 1265 pm_runtime_enable(&pdev->dev); 1266 pm_runtime_put_sync(&pdev->dev); 1267 1268 return 0; 1269 1270 err_wirq: 1271 if (stm32port->wakeirq > 0) 1272 dev_pm_clear_wake_irq(&pdev->dev); 1273 1274 err_nowup: 1275 if (stm32port->wakeirq > 0) 1276 device_init_wakeup(&pdev->dev, false); 1277 1278 err_uninit: 1279 clk_disable_unprepare(stm32port->clk); 1280 1281 return ret; 1282 } 1283 1284 static int stm32_usart_serial_remove(struct platform_device *pdev) 1285 { 1286 struct uart_port *port = platform_get_drvdata(pdev); 1287 struct stm32_port *stm32_port = to_stm32_port(port); 1288 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1289 int err; 1290 1291 pm_runtime_get_sync(&pdev->dev); 1292 1293 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1294 1295 if (stm32_port->rx_ch) 1296 dma_release_channel(stm32_port->rx_ch); 1297 1298 if (stm32_port->rx_dma_buf) 1299 dma_free_coherent(&pdev->dev, 1300 RX_BUF_L, stm32_port->rx_buf, 1301 stm32_port->rx_dma_buf); 1302 1303 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1304 1305 if (stm32_port->tx_ch) 1306 dma_release_channel(stm32_port->tx_ch); 1307 1308 if (stm32_port->tx_dma_buf) 1309 dma_free_coherent(&pdev->dev, 1310 TX_BUF_L, stm32_port->tx_buf, 1311 stm32_port->tx_dma_buf); 1312 1313 if (stm32_port->wakeirq > 0) { 1314 dev_pm_clear_wake_irq(&pdev->dev); 1315 device_init_wakeup(&pdev->dev, false); 1316 } 1317 1318 clk_disable_unprepare(stm32_port->clk); 1319 1320 err = uart_remove_one_port(&stm32_usart_driver, port); 1321 1322 pm_runtime_disable(&pdev->dev); 1323 pm_runtime_put_noidle(&pdev->dev); 1324 1325 return err; 1326 } 1327 1328 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1329 static void stm32_usart_console_putchar(struct uart_port *port, int ch) 1330 { 1331 struct stm32_port *stm32_port = to_stm32_port(port); 1332 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1333 1334 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1335 cpu_relax(); 1336 1337 writel_relaxed(ch, port->membase + ofs->tdr); 1338 } 1339 1340 static void stm32_usart_console_write(struct console *co, const char *s, 1341 unsigned int cnt) 1342 { 1343 struct uart_port *port = &stm32_ports[co->index].port; 1344 struct stm32_port *stm32_port = to_stm32_port(port); 1345 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1346 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1347 unsigned long flags; 1348 u32 old_cr1, new_cr1; 1349 int locked = 1; 1350 1351 local_irq_save(flags); 1352 if (port->sysrq) 1353 locked = 0; 1354 else if (oops_in_progress) 1355 locked = spin_trylock(&port->lock); 1356 else 1357 spin_lock(&port->lock); 1358 1359 /* Save and disable interrupts, enable the transmitter */ 1360 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1361 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1362 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1363 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1364 1365 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1366 1367 /* Restore interrupt state */ 1368 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1369 1370 if (locked) 1371 spin_unlock(&port->lock); 1372 local_irq_restore(flags); 1373 } 1374 1375 static int stm32_usart_console_setup(struct console *co, char *options) 1376 { 1377 struct stm32_port *stm32port; 1378 int baud = 9600; 1379 int bits = 8; 1380 int parity = 'n'; 1381 int flow = 'n'; 1382 1383 if (co->index >= STM32_MAX_PORTS) 1384 return -ENODEV; 1385 1386 stm32port = &stm32_ports[co->index]; 1387 1388 /* 1389 * This driver does not support early console initialization 1390 * (use ARM early printk support instead), so we only expect 1391 * this to be called during the uart port registration when the 1392 * driver gets probed and the port should be mapped at that point. 1393 */ 1394 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1395 return -ENXIO; 1396 1397 if (options) 1398 uart_parse_options(options, &baud, &parity, &bits, &flow); 1399 1400 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1401 } 1402 1403 static struct console stm32_console = { 1404 .name = STM32_SERIAL_NAME, 1405 .device = uart_console_device, 1406 .write = stm32_usart_console_write, 1407 .setup = stm32_usart_console_setup, 1408 .flags = CON_PRINTBUFFER, 1409 .index = -1, 1410 .data = &stm32_usart_driver, 1411 }; 1412 1413 #define STM32_SERIAL_CONSOLE (&stm32_console) 1414 1415 #else 1416 #define STM32_SERIAL_CONSOLE NULL 1417 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1418 1419 static struct uart_driver stm32_usart_driver = { 1420 .driver_name = DRIVER_NAME, 1421 .dev_name = STM32_SERIAL_NAME, 1422 .major = 0, 1423 .minor = 0, 1424 .nr = STM32_MAX_PORTS, 1425 .cons = STM32_SERIAL_CONSOLE, 1426 }; 1427 1428 static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1429 bool enable) 1430 { 1431 struct stm32_port *stm32_port = to_stm32_port(port); 1432 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1433 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1434 u32 val; 1435 1436 if (stm32_port->wakeirq <= 0) 1437 return; 1438 1439 if (enable) { 1440 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1441 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 1442 val = readl_relaxed(port->membase + ofs->cr3); 1443 val &= ~USART_CR3_WUS_MASK; 1444 /* Enable Wake up interrupt from low power on start bit */ 1445 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; 1446 writel_relaxed(val, port->membase + ofs->cr3); 1447 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1448 } else { 1449 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1450 } 1451 } 1452 1453 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 1454 { 1455 struct uart_port *port = dev_get_drvdata(dev); 1456 1457 uart_suspend_port(&stm32_usart_driver, port); 1458 1459 if (device_may_wakeup(dev)) 1460 stm32_usart_serial_en_wakeup(port, true); 1461 else 1462 stm32_usart_serial_en_wakeup(port, false); 1463 1464 /* 1465 * When "no_console_suspend" is enabled, keep the pinctrl default state 1466 * and rely on bootloader stage to restore this state upon resume. 1467 * Otherwise, apply the idle or sleep states depending on wakeup 1468 * capabilities. 1469 */ 1470 if (console_suspend_enabled || !uart_console(port)) { 1471 if (device_may_wakeup(dev)) 1472 pinctrl_pm_select_idle_state(dev); 1473 else 1474 pinctrl_pm_select_sleep_state(dev); 1475 } 1476 1477 return 0; 1478 } 1479 1480 static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 1481 { 1482 struct uart_port *port = dev_get_drvdata(dev); 1483 1484 pinctrl_pm_select_default_state(dev); 1485 1486 if (device_may_wakeup(dev)) 1487 stm32_usart_serial_en_wakeup(port, false); 1488 1489 return uart_resume_port(&stm32_usart_driver, port); 1490 } 1491 1492 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 1493 { 1494 struct uart_port *port = dev_get_drvdata(dev); 1495 struct stm32_port *stm32port = container_of(port, 1496 struct stm32_port, port); 1497 1498 clk_disable_unprepare(stm32port->clk); 1499 1500 return 0; 1501 } 1502 1503 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 1504 { 1505 struct uart_port *port = dev_get_drvdata(dev); 1506 struct stm32_port *stm32port = container_of(port, 1507 struct stm32_port, port); 1508 1509 return clk_prepare_enable(stm32port->clk); 1510 } 1511 1512 static const struct dev_pm_ops stm32_serial_pm_ops = { 1513 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 1514 stm32_usart_runtime_resume, NULL) 1515 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 1516 stm32_usart_serial_resume) 1517 }; 1518 1519 static struct platform_driver stm32_serial_driver = { 1520 .probe = stm32_usart_serial_probe, 1521 .remove = stm32_usart_serial_remove, 1522 .driver = { 1523 .name = DRIVER_NAME, 1524 .pm = &stm32_serial_pm_ops, 1525 .of_match_table = of_match_ptr(stm32_match), 1526 }, 1527 }; 1528 1529 static int __init stm32_usart_init(void) 1530 { 1531 static char banner[] __initdata = "STM32 USART driver initialized"; 1532 int ret; 1533 1534 pr_info("%s\n", banner); 1535 1536 ret = uart_register_driver(&stm32_usart_driver); 1537 if (ret) 1538 return ret; 1539 1540 ret = platform_driver_register(&stm32_serial_driver); 1541 if (ret) 1542 uart_unregister_driver(&stm32_usart_driver); 1543 1544 return ret; 1545 } 1546 1547 static void __exit stm32_usart_exit(void) 1548 { 1549 platform_driver_unregister(&stm32_serial_driver); 1550 uart_unregister_driver(&stm32_usart_driver); 1551 } 1552 1553 module_init(stm32_usart_init); 1554 module_exit(stm32_usart_exit); 1555 1556 MODULE_ALIAS("platform:" DRIVER_NAME); 1557 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1558 MODULE_LICENSE("GPL v2"); 1559