1 /* 2 * Copyright (C) Maxime Coquelin 2015 3 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 4 * Gerald Baeza <gerald.baeza@st.com> 5 * License terms: GNU General Public License (GPL), version 2 6 * 7 * Inspired by st-asc.c from STMicroelectronics (c) 8 */ 9 10 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 11 #define SUPPORT_SYSRQ 12 #endif 13 14 #include <linux/clk.h> 15 #include <linux/console.h> 16 #include <linux/delay.h> 17 #include <linux/dma-direction.h> 18 #include <linux/dmaengine.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/irq.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "stm32-usart.h" 36 37 static void stm32_stop_tx(struct uart_port *port); 38 static void stm32_transmit_chars(struct uart_port *port); 39 40 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 41 { 42 return container_of(port, struct stm32_port, port); 43 } 44 45 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) 46 { 47 u32 val; 48 49 val = readl_relaxed(port->membase + reg); 50 val |= bits; 51 writel_relaxed(val, port->membase + reg); 52 } 53 54 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) 55 { 56 u32 val; 57 58 val = readl_relaxed(port->membase + reg); 59 val &= ~bits; 60 writel_relaxed(val, port->membase + reg); 61 } 62 63 int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, 64 bool threaded) 65 { 66 struct stm32_port *stm32_port = to_stm32_port(port); 67 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 68 enum dma_status status; 69 struct dma_tx_state state; 70 71 *sr = readl_relaxed(port->membase + ofs->isr); 72 73 if (threaded && stm32_port->rx_ch) { 74 status = dmaengine_tx_status(stm32_port->rx_ch, 75 stm32_port->rx_ch->cookie, 76 &state); 77 if ((status == DMA_IN_PROGRESS) && 78 (*last_res != state.residue)) 79 return 1; 80 else 81 return 0; 82 } else if (*sr & USART_SR_RXNE) { 83 return 1; 84 } 85 return 0; 86 } 87 88 unsigned long stm32_get_char(struct uart_port *port, u32 *sr, int *last_res) 89 { 90 struct stm32_port *stm32_port = to_stm32_port(port); 91 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 92 unsigned long c; 93 94 if (stm32_port->rx_ch) { 95 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 96 if ((*last_res) == 0) 97 *last_res = RX_BUF_L; 98 return c; 99 } else { 100 return readl_relaxed(port->membase + ofs->rdr); 101 } 102 } 103 104 static void stm32_receive_chars(struct uart_port *port, bool threaded) 105 { 106 struct tty_port *tport = &port->state->port; 107 struct stm32_port *stm32_port = to_stm32_port(port); 108 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 109 unsigned long c; 110 u32 sr; 111 char flag; 112 static int last_res = RX_BUF_L; 113 114 if (port->irq_wake) 115 pm_wakeup_event(tport->tty->dev, 0); 116 117 while (stm32_pending_rx(port, &sr, &last_res, threaded)) { 118 sr |= USART_SR_DUMMY_RX; 119 c = stm32_get_char(port, &sr, &last_res); 120 flag = TTY_NORMAL; 121 port->icount.rx++; 122 123 if (sr & USART_SR_ERR_MASK) { 124 if (sr & USART_SR_LBD) { 125 port->icount.brk++; 126 if (uart_handle_break(port)) 127 continue; 128 } else if (sr & USART_SR_ORE) { 129 if (ofs->icr != UNDEF_REG) 130 writel_relaxed(USART_ICR_ORECF, 131 port->membase + 132 ofs->icr); 133 port->icount.overrun++; 134 } else if (sr & USART_SR_PE) { 135 port->icount.parity++; 136 } else if (sr & USART_SR_FE) { 137 port->icount.frame++; 138 } 139 140 sr &= port->read_status_mask; 141 142 if (sr & USART_SR_LBD) 143 flag = TTY_BREAK; 144 else if (sr & USART_SR_PE) 145 flag = TTY_PARITY; 146 else if (sr & USART_SR_FE) 147 flag = TTY_FRAME; 148 } 149 150 if (uart_handle_sysrq_char(port, c)) 151 continue; 152 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 153 } 154 155 spin_unlock(&port->lock); 156 tty_flip_buffer_push(tport); 157 spin_lock(&port->lock); 158 } 159 160 static void stm32_tx_dma_complete(void *arg) 161 { 162 struct uart_port *port = arg; 163 struct stm32_port *stm32port = to_stm32_port(port); 164 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 165 unsigned int isr; 166 int ret; 167 168 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 169 isr, 170 (isr & USART_SR_TC), 171 10, 100000); 172 173 if (ret) 174 dev_err(port->dev, "terminal count not set\n"); 175 176 if (ofs->icr == UNDEF_REG) 177 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 178 else 179 stm32_set_bits(port, ofs->icr, USART_CR_TC); 180 181 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 182 stm32port->tx_dma_busy = false; 183 184 /* Let's see if we have pending data to send */ 185 stm32_transmit_chars(port); 186 } 187 188 static void stm32_transmit_chars_pio(struct uart_port *port) 189 { 190 struct stm32_port *stm32_port = to_stm32_port(port); 191 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 192 struct circ_buf *xmit = &port->state->xmit; 193 unsigned int isr; 194 int ret; 195 196 if (stm32_port->tx_dma_busy) { 197 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 198 stm32_port->tx_dma_busy = false; 199 } 200 201 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 202 isr, 203 (isr & USART_SR_TXE), 204 10, 100); 205 206 if (ret) 207 dev_err(port->dev, "tx empty not set\n"); 208 209 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 210 211 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 212 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 213 port->icount.tx++; 214 } 215 216 static void stm32_transmit_chars_dma(struct uart_port *port) 217 { 218 struct stm32_port *stm32port = to_stm32_port(port); 219 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 220 struct circ_buf *xmit = &port->state->xmit; 221 struct dma_async_tx_descriptor *desc = NULL; 222 dma_cookie_t cookie; 223 unsigned int count, i; 224 225 if (stm32port->tx_dma_busy) 226 return; 227 228 stm32port->tx_dma_busy = true; 229 230 count = uart_circ_chars_pending(xmit); 231 232 if (count > TX_BUF_L) 233 count = TX_BUF_L; 234 235 if (xmit->tail < xmit->head) { 236 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 237 } else { 238 size_t one = UART_XMIT_SIZE - xmit->tail; 239 size_t two; 240 241 if (one > count) 242 one = count; 243 two = count - one; 244 245 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 246 if (two) 247 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 248 } 249 250 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 251 stm32port->tx_dma_buf, 252 count, 253 DMA_MEM_TO_DEV, 254 DMA_PREP_INTERRUPT); 255 256 if (!desc) { 257 for (i = count; i > 0; i--) 258 stm32_transmit_chars_pio(port); 259 return; 260 } 261 262 desc->callback = stm32_tx_dma_complete; 263 desc->callback_param = port; 264 265 /* Push current DMA TX transaction in the pending queue */ 266 cookie = dmaengine_submit(desc); 267 268 /* Issue pending DMA TX requests */ 269 dma_async_issue_pending(stm32port->tx_ch); 270 271 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 272 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 273 274 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 275 port->icount.tx += count; 276 } 277 278 static void stm32_transmit_chars(struct uart_port *port) 279 { 280 struct stm32_port *stm32_port = to_stm32_port(port); 281 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 282 struct circ_buf *xmit = &port->state->xmit; 283 284 if (port->x_char) { 285 if (stm32_port->tx_dma_busy) 286 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 287 writel_relaxed(port->x_char, port->membase + ofs->tdr); 288 port->x_char = 0; 289 port->icount.tx++; 290 if (stm32_port->tx_dma_busy) 291 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 292 return; 293 } 294 295 if (uart_tx_stopped(port)) { 296 stm32_stop_tx(port); 297 return; 298 } 299 300 if (uart_circ_empty(xmit)) { 301 stm32_stop_tx(port); 302 return; 303 } 304 305 if (stm32_port->tx_ch) 306 stm32_transmit_chars_dma(port); 307 else 308 stm32_transmit_chars_pio(port); 309 310 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 311 uart_write_wakeup(port); 312 313 if (uart_circ_empty(xmit)) 314 stm32_stop_tx(port); 315 } 316 317 static irqreturn_t stm32_interrupt(int irq, void *ptr) 318 { 319 struct uart_port *port = ptr; 320 struct stm32_port *stm32_port = to_stm32_port(port); 321 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 322 u32 sr; 323 324 spin_lock(&port->lock); 325 326 sr = readl_relaxed(port->membase + ofs->isr); 327 328 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 329 stm32_receive_chars(port, false); 330 331 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 332 stm32_transmit_chars(port); 333 334 spin_unlock(&port->lock); 335 336 if (stm32_port->rx_ch) 337 return IRQ_WAKE_THREAD; 338 else 339 return IRQ_HANDLED; 340 } 341 342 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr) 343 { 344 struct uart_port *port = ptr; 345 struct stm32_port *stm32_port = to_stm32_port(port); 346 347 spin_lock(&port->lock); 348 349 if (stm32_port->rx_ch) 350 stm32_receive_chars(port, true); 351 352 spin_unlock(&port->lock); 353 354 return IRQ_HANDLED; 355 } 356 357 static unsigned int stm32_tx_empty(struct uart_port *port) 358 { 359 struct stm32_port *stm32_port = to_stm32_port(port); 360 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 361 362 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 363 } 364 365 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) 366 { 367 struct stm32_port *stm32_port = to_stm32_port(port); 368 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 369 370 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 371 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); 372 else 373 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 374 } 375 376 static unsigned int stm32_get_mctrl(struct uart_port *port) 377 { 378 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 379 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 380 } 381 382 /* Transmit stop */ 383 static void stm32_stop_tx(struct uart_port *port) 384 { 385 struct stm32_port *stm32_port = to_stm32_port(port); 386 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 387 388 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 389 } 390 391 /* There are probably characters waiting to be transmitted. */ 392 static void stm32_start_tx(struct uart_port *port) 393 { 394 struct circ_buf *xmit = &port->state->xmit; 395 396 if (uart_circ_empty(xmit)) 397 return; 398 399 stm32_transmit_chars(port); 400 } 401 402 /* Throttle the remote when input buffer is about to overflow. */ 403 static void stm32_throttle(struct uart_port *port) 404 { 405 struct stm32_port *stm32_port = to_stm32_port(port); 406 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 407 unsigned long flags; 408 409 spin_lock_irqsave(&port->lock, flags); 410 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 411 spin_unlock_irqrestore(&port->lock, flags); 412 } 413 414 /* Unthrottle the remote, the input buffer can now accept data. */ 415 static void stm32_unthrottle(struct uart_port *port) 416 { 417 struct stm32_port *stm32_port = to_stm32_port(port); 418 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 419 unsigned long flags; 420 421 spin_lock_irqsave(&port->lock, flags); 422 stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE); 423 spin_unlock_irqrestore(&port->lock, flags); 424 } 425 426 /* Receive stop */ 427 static void stm32_stop_rx(struct uart_port *port) 428 { 429 struct stm32_port *stm32_port = to_stm32_port(port); 430 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 431 432 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 433 } 434 435 /* Handle breaks - ignored by us */ 436 static void stm32_break_ctl(struct uart_port *port, int break_state) 437 { 438 } 439 440 static int stm32_startup(struct uart_port *port) 441 { 442 struct stm32_port *stm32_port = to_stm32_port(port); 443 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 444 const char *name = to_platform_device(port->dev)->name; 445 u32 val; 446 int ret; 447 448 ret = request_threaded_irq(port->irq, stm32_interrupt, 449 stm32_threaded_interrupt, 450 IRQF_NO_SUSPEND, name, port); 451 if (ret) 452 return ret; 453 454 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 455 stm32_set_bits(port, ofs->cr1, val); 456 457 return 0; 458 } 459 460 static void stm32_shutdown(struct uart_port *port) 461 { 462 struct stm32_port *stm32_port = to_stm32_port(port); 463 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 464 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 465 u32 val; 466 467 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 468 val |= BIT(cfg->uart_enable_bit); 469 stm32_clr_bits(port, ofs->cr1, val); 470 471 free_irq(port->irq, port); 472 } 473 474 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, 475 struct ktermios *old) 476 { 477 struct stm32_port *stm32_port = to_stm32_port(port); 478 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 479 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 480 unsigned int baud; 481 u32 usartdiv, mantissa, fraction, oversampling; 482 tcflag_t cflag = termios->c_cflag; 483 u32 cr1, cr2, cr3; 484 unsigned long flags; 485 486 if (!stm32_port->hw_flow_control) 487 cflag &= ~CRTSCTS; 488 489 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 490 491 spin_lock_irqsave(&port->lock, flags); 492 493 /* Stop serial port and reset value */ 494 writel_relaxed(0, port->membase + ofs->cr1); 495 496 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE; 497 cr1 |= BIT(cfg->uart_enable_bit); 498 cr2 = 0; 499 cr3 = 0; 500 501 if (cflag & CSTOPB) 502 cr2 |= USART_CR2_STOP_2B; 503 504 if (cflag & PARENB) { 505 cr1 |= USART_CR1_PCE; 506 if ((cflag & CSIZE) == CS8) { 507 if (cfg->has_7bits_data) 508 cr1 |= USART_CR1_M0; 509 else 510 cr1 |= USART_CR1_M; 511 } 512 } 513 514 if (cflag & PARODD) 515 cr1 |= USART_CR1_PS; 516 517 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 518 if (cflag & CRTSCTS) { 519 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 520 cr3 |= USART_CR3_CTSE; 521 } 522 523 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 524 525 /* 526 * The USART supports 16 or 8 times oversampling. 527 * By default we prefer 16 times oversampling, so that the receiver 528 * has a better tolerance to clock deviations. 529 * 8 times oversampling is only used to achieve higher speeds. 530 */ 531 if (usartdiv < 16) { 532 oversampling = 8; 533 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); 534 } else { 535 oversampling = 16; 536 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 537 } 538 539 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 540 fraction = usartdiv % oversampling; 541 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 542 543 uart_update_timeout(port, cflag, baud); 544 545 port->read_status_mask = USART_SR_ORE; 546 if (termios->c_iflag & INPCK) 547 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 548 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 549 port->read_status_mask |= USART_SR_LBD; 550 551 /* Characters to ignore */ 552 port->ignore_status_mask = 0; 553 if (termios->c_iflag & IGNPAR) 554 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 555 if (termios->c_iflag & IGNBRK) { 556 port->ignore_status_mask |= USART_SR_LBD; 557 /* 558 * If we're ignoring parity and break indicators, 559 * ignore overruns too (for real raw support). 560 */ 561 if (termios->c_iflag & IGNPAR) 562 port->ignore_status_mask |= USART_SR_ORE; 563 } 564 565 /* Ignore all characters if CREAD is not set */ 566 if ((termios->c_cflag & CREAD) == 0) 567 port->ignore_status_mask |= USART_SR_DUMMY_RX; 568 569 if (stm32_port->rx_ch) 570 cr3 |= USART_CR3_DMAR; 571 572 writel_relaxed(cr3, port->membase + ofs->cr3); 573 writel_relaxed(cr2, port->membase + ofs->cr2); 574 writel_relaxed(cr1, port->membase + ofs->cr1); 575 576 spin_unlock_irqrestore(&port->lock, flags); 577 } 578 579 static const char *stm32_type(struct uart_port *port) 580 { 581 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 582 } 583 584 static void stm32_release_port(struct uart_port *port) 585 { 586 } 587 588 static int stm32_request_port(struct uart_port *port) 589 { 590 return 0; 591 } 592 593 static void stm32_config_port(struct uart_port *port, int flags) 594 { 595 if (flags & UART_CONFIG_TYPE) 596 port->type = PORT_STM32; 597 } 598 599 static int 600 stm32_verify_port(struct uart_port *port, struct serial_struct *ser) 601 { 602 /* No user changeable parameters */ 603 return -EINVAL; 604 } 605 606 static void stm32_pm(struct uart_port *port, unsigned int state, 607 unsigned int oldstate) 608 { 609 struct stm32_port *stm32port = container_of(port, 610 struct stm32_port, port); 611 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 612 struct stm32_usart_config *cfg = &stm32port->info->cfg; 613 unsigned long flags = 0; 614 615 switch (state) { 616 case UART_PM_STATE_ON: 617 clk_prepare_enable(stm32port->clk); 618 break; 619 case UART_PM_STATE_OFF: 620 spin_lock_irqsave(&port->lock, flags); 621 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 622 spin_unlock_irqrestore(&port->lock, flags); 623 clk_disable_unprepare(stm32port->clk); 624 break; 625 } 626 } 627 628 static const struct uart_ops stm32_uart_ops = { 629 .tx_empty = stm32_tx_empty, 630 .set_mctrl = stm32_set_mctrl, 631 .get_mctrl = stm32_get_mctrl, 632 .stop_tx = stm32_stop_tx, 633 .start_tx = stm32_start_tx, 634 .throttle = stm32_throttle, 635 .unthrottle = stm32_unthrottle, 636 .stop_rx = stm32_stop_rx, 637 .break_ctl = stm32_break_ctl, 638 .startup = stm32_startup, 639 .shutdown = stm32_shutdown, 640 .set_termios = stm32_set_termios, 641 .pm = stm32_pm, 642 .type = stm32_type, 643 .release_port = stm32_release_port, 644 .request_port = stm32_request_port, 645 .config_port = stm32_config_port, 646 .verify_port = stm32_verify_port, 647 }; 648 649 static int stm32_init_port(struct stm32_port *stm32port, 650 struct platform_device *pdev) 651 { 652 struct uart_port *port = &stm32port->port; 653 struct resource *res; 654 int ret; 655 656 port->iotype = UPIO_MEM; 657 port->flags = UPF_BOOT_AUTOCONF; 658 port->ops = &stm32_uart_ops; 659 port->dev = &pdev->dev; 660 port->irq = platform_get_irq(pdev, 0); 661 662 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 663 port->membase = devm_ioremap_resource(&pdev->dev, res); 664 if (IS_ERR(port->membase)) 665 return PTR_ERR(port->membase); 666 port->mapbase = res->start; 667 668 spin_lock_init(&port->lock); 669 670 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 671 if (IS_ERR(stm32port->clk)) 672 return PTR_ERR(stm32port->clk); 673 674 /* Ensure that clk rate is correct by enabling the clk */ 675 ret = clk_prepare_enable(stm32port->clk); 676 if (ret) 677 return ret; 678 679 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 680 if (!stm32port->port.uartclk) 681 ret = -EINVAL; 682 683 return ret; 684 } 685 686 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) 687 { 688 struct device_node *np = pdev->dev.of_node; 689 int id; 690 691 if (!np) 692 return NULL; 693 694 id = of_alias_get_id(np, "serial"); 695 if (id < 0) 696 id = 0; 697 698 if (WARN_ON(id >= STM32_MAX_PORTS)) 699 return NULL; 700 701 stm32_ports[id].hw_flow_control = of_property_read_bool(np, 702 "st,hw-flow-ctrl"); 703 stm32_ports[id].port.line = id; 704 return &stm32_ports[id]; 705 } 706 707 #ifdef CONFIG_OF 708 static const struct of_device_id stm32_match[] = { 709 { .compatible = "st,stm32-usart", .data = &stm32f4_info}, 710 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 711 { .compatible = "st,stm32f7-usart", .data = &stm32f7_info}, 712 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 713 {}, 714 }; 715 716 MODULE_DEVICE_TABLE(of, stm32_match); 717 #endif 718 719 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port, 720 struct platform_device *pdev) 721 { 722 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 723 struct uart_port *port = &stm32port->port; 724 struct device *dev = &pdev->dev; 725 struct dma_slave_config config; 726 struct dma_async_tx_descriptor *desc = NULL; 727 dma_cookie_t cookie; 728 int ret; 729 730 /* Request DMA RX channel */ 731 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 732 if (!stm32port->rx_ch) { 733 dev_info(dev, "rx dma alloc failed\n"); 734 return -ENODEV; 735 } 736 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 737 &stm32port->rx_dma_buf, 738 GFP_KERNEL); 739 if (!stm32port->rx_buf) { 740 ret = -ENOMEM; 741 goto alloc_err; 742 } 743 744 /* Configure DMA channel */ 745 memset(&config, 0, sizeof(config)); 746 config.src_addr = port->mapbase + ofs->rdr; 747 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 748 749 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 750 if (ret < 0) { 751 dev_err(dev, "rx dma channel config failed\n"); 752 ret = -ENODEV; 753 goto config_err; 754 } 755 756 /* Prepare a DMA cyclic transaction */ 757 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 758 stm32port->rx_dma_buf, 759 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 760 DMA_PREP_INTERRUPT); 761 if (!desc) { 762 dev_err(dev, "rx dma prep cyclic failed\n"); 763 ret = -ENODEV; 764 goto config_err; 765 } 766 767 /* No callback as dma buffer is drained on usart interrupt */ 768 desc->callback = NULL; 769 desc->callback_param = NULL; 770 771 /* Push current DMA transaction in the pending queue */ 772 cookie = dmaengine_submit(desc); 773 774 /* Issue pending DMA requests */ 775 dma_async_issue_pending(stm32port->rx_ch); 776 777 return 0; 778 779 config_err: 780 dma_free_coherent(&pdev->dev, 781 RX_BUF_L, stm32port->rx_buf, 782 stm32port->rx_dma_buf); 783 784 alloc_err: 785 dma_release_channel(stm32port->rx_ch); 786 stm32port->rx_ch = NULL; 787 788 return ret; 789 } 790 791 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port, 792 struct platform_device *pdev) 793 { 794 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 795 struct uart_port *port = &stm32port->port; 796 struct device *dev = &pdev->dev; 797 struct dma_slave_config config; 798 int ret; 799 800 stm32port->tx_dma_busy = false; 801 802 /* Request DMA TX channel */ 803 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 804 if (!stm32port->tx_ch) { 805 dev_info(dev, "tx dma alloc failed\n"); 806 return -ENODEV; 807 } 808 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 809 &stm32port->tx_dma_buf, 810 GFP_KERNEL); 811 if (!stm32port->tx_buf) { 812 ret = -ENOMEM; 813 goto alloc_err; 814 } 815 816 /* Configure DMA channel */ 817 memset(&config, 0, sizeof(config)); 818 config.dst_addr = port->mapbase + ofs->tdr; 819 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 820 821 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 822 if (ret < 0) { 823 dev_err(dev, "tx dma channel config failed\n"); 824 ret = -ENODEV; 825 goto config_err; 826 } 827 828 return 0; 829 830 config_err: 831 dma_free_coherent(&pdev->dev, 832 TX_BUF_L, stm32port->tx_buf, 833 stm32port->tx_dma_buf); 834 835 alloc_err: 836 dma_release_channel(stm32port->tx_ch); 837 stm32port->tx_ch = NULL; 838 839 return ret; 840 } 841 842 static int stm32_serial_probe(struct platform_device *pdev) 843 { 844 const struct of_device_id *match; 845 struct stm32_port *stm32port; 846 int ret; 847 848 stm32port = stm32_of_get_stm32_port(pdev); 849 if (!stm32port) 850 return -ENODEV; 851 852 match = of_match_device(stm32_match, &pdev->dev); 853 if (match && match->data) 854 stm32port->info = (struct stm32_usart_info *)match->data; 855 else 856 return -EINVAL; 857 858 ret = stm32_init_port(stm32port, pdev); 859 if (ret) 860 return ret; 861 862 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 863 if (ret) 864 return ret; 865 866 ret = stm32_of_dma_rx_probe(stm32port, pdev); 867 if (ret) 868 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 869 870 ret = stm32_of_dma_tx_probe(stm32port, pdev); 871 if (ret) 872 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 873 874 platform_set_drvdata(pdev, &stm32port->port); 875 876 return 0; 877 } 878 879 static int stm32_serial_remove(struct platform_device *pdev) 880 { 881 struct uart_port *port = platform_get_drvdata(pdev); 882 struct stm32_port *stm32_port = to_stm32_port(port); 883 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 884 885 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 886 887 if (stm32_port->rx_ch) 888 dma_release_channel(stm32_port->rx_ch); 889 890 if (stm32_port->rx_dma_buf) 891 dma_free_coherent(&pdev->dev, 892 RX_BUF_L, stm32_port->rx_buf, 893 stm32_port->rx_dma_buf); 894 895 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 896 897 if (stm32_port->tx_ch) 898 dma_release_channel(stm32_port->tx_ch); 899 900 if (stm32_port->tx_dma_buf) 901 dma_free_coherent(&pdev->dev, 902 TX_BUF_L, stm32_port->tx_buf, 903 stm32_port->tx_dma_buf); 904 905 clk_disable_unprepare(stm32_port->clk); 906 907 return uart_remove_one_port(&stm32_usart_driver, port); 908 } 909 910 911 #ifdef CONFIG_SERIAL_STM32_CONSOLE 912 static void stm32_console_putchar(struct uart_port *port, int ch) 913 { 914 struct stm32_port *stm32_port = to_stm32_port(port); 915 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 916 917 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 918 cpu_relax(); 919 920 writel_relaxed(ch, port->membase + ofs->tdr); 921 } 922 923 static void stm32_console_write(struct console *co, const char *s, unsigned cnt) 924 { 925 struct uart_port *port = &stm32_ports[co->index].port; 926 struct stm32_port *stm32_port = to_stm32_port(port); 927 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 928 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 929 unsigned long flags; 930 u32 old_cr1, new_cr1; 931 int locked = 1; 932 933 local_irq_save(flags); 934 if (port->sysrq) 935 locked = 0; 936 else if (oops_in_progress) 937 locked = spin_trylock(&port->lock); 938 else 939 spin_lock(&port->lock); 940 941 /* Save and disable interrupts, enable the transmitter */ 942 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 943 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 944 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 945 writel_relaxed(new_cr1, port->membase + ofs->cr1); 946 947 uart_console_write(port, s, cnt, stm32_console_putchar); 948 949 /* Restore interrupt state */ 950 writel_relaxed(old_cr1, port->membase + ofs->cr1); 951 952 if (locked) 953 spin_unlock(&port->lock); 954 local_irq_restore(flags); 955 } 956 957 static int stm32_console_setup(struct console *co, char *options) 958 { 959 struct stm32_port *stm32port; 960 int baud = 9600; 961 int bits = 8; 962 int parity = 'n'; 963 int flow = 'n'; 964 965 if (co->index >= STM32_MAX_PORTS) 966 return -ENODEV; 967 968 stm32port = &stm32_ports[co->index]; 969 970 /* 971 * This driver does not support early console initialization 972 * (use ARM early printk support instead), so we only expect 973 * this to be called during the uart port registration when the 974 * driver gets probed and the port should be mapped at that point. 975 */ 976 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) 977 return -ENXIO; 978 979 if (options) 980 uart_parse_options(options, &baud, &parity, &bits, &flow); 981 982 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 983 } 984 985 static struct console stm32_console = { 986 .name = STM32_SERIAL_NAME, 987 .device = uart_console_device, 988 .write = stm32_console_write, 989 .setup = stm32_console_setup, 990 .flags = CON_PRINTBUFFER, 991 .index = -1, 992 .data = &stm32_usart_driver, 993 }; 994 995 #define STM32_SERIAL_CONSOLE (&stm32_console) 996 997 #else 998 #define STM32_SERIAL_CONSOLE NULL 999 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1000 1001 static struct uart_driver stm32_usart_driver = { 1002 .driver_name = DRIVER_NAME, 1003 .dev_name = STM32_SERIAL_NAME, 1004 .major = 0, 1005 .minor = 0, 1006 .nr = STM32_MAX_PORTS, 1007 .cons = STM32_SERIAL_CONSOLE, 1008 }; 1009 1010 static struct platform_driver stm32_serial_driver = { 1011 .probe = stm32_serial_probe, 1012 .remove = stm32_serial_remove, 1013 .driver = { 1014 .name = DRIVER_NAME, 1015 .of_match_table = of_match_ptr(stm32_match), 1016 }, 1017 }; 1018 1019 static int __init usart_init(void) 1020 { 1021 static char banner[] __initdata = "STM32 USART driver initialized"; 1022 int ret; 1023 1024 pr_info("%s\n", banner); 1025 1026 ret = uart_register_driver(&stm32_usart_driver); 1027 if (ret) 1028 return ret; 1029 1030 ret = platform_driver_register(&stm32_serial_driver); 1031 if (ret) 1032 uart_unregister_driver(&stm32_usart_driver); 1033 1034 return ret; 1035 } 1036 1037 static void __exit usart_exit(void) 1038 { 1039 platform_driver_unregister(&stm32_serial_driver); 1040 uart_unregister_driver(&stm32_usart_driver); 1041 } 1042 1043 module_init(usart_init); 1044 module_exit(usart_exit); 1045 1046 MODULE_ALIAS("platform:" DRIVER_NAME); 1047 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1048 MODULE_LICENSE("GPL v2"); 1049